Red Rapids Front End 000-009 User manual

Publication No. REF-000-009-R00
Red Rapids
Front End 000-009
Dual 16-Bit 310 Msps Receiver
Reference Manual
797 North Grove Rd, Suite 101
Richardson, TX 75081
Phone: [phone]
www.redrapids.com

Publication No. REF-000-009-R00
Red Rapids
Red Rapids reserves the right to alter product specifications or discontinue any product without
notice. All products are sold subject to the terms and conditions of sale supplied at the time of
order acknowledgment. This product is not designed, authorized, or warranted for use in a life-
support system or other critical application.
All trademark and registered trademarks are the property of their respective owners.
Copyright © 2016, Red Rapids, Inc. All rights reserved.

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Table of Contents
1.0 Introduction.......................................................................................................................1
1.1 Contents and Structure .................................................................................................1
1.2 Conventions..................................................................................................................1
1.3 Revision History............................................................................................................1
2.0 Description........................................................................................................................2
2.1 Filter Build Option..........................................................................................................3
2.2 Coupling........................................................................................................................3
2.3 DC Offset Adjustment (DC-Coupled units only).............................................................4
2.4 ADC Configuration ........................................................................................................5
2.4.1 ADC Hardware Interface........................................................................................5
2.4.1 ADC Control Interface............................................................................................6
2.4.1 ADC Clock Interface...............................................................................................6
2.4.2 ADC Data Interface................................................................................................6
3.0 Specifications ...................................................................................................................7
3.1 Input Levels...................................................................................................................7
3.2 Performance..................................................................................................................8
3.2.1 AC-Coupled Performance ......................................................................................8
3.2.2 DC-Coupled Performance......................................................................................9
3.3 Absolute Maximums......................................................................................................9
4.0 Typical Performance Characteristics...............................................................................10
4.1 AC-Coupled.................................................................................................................10
4.2 DC-Coupled ................................................................................................................13
4.3 Generating Characterization Plots...............................................................................15
5.0 Key Components............................................................................................................16
6.0 Technical Support...........................................................................................................17

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List of Figures
Figure 2-1 Receiver Block Diagram.............................................................................................2
Figure 2-2 Coupling Options (equivalent circuits) .......................................................................3
Figure 2-3 Trim DAC Operation in DC-Coupled Build Option......................................................4
Figure 2-4 Trim DAC Control......................................................................................................5
Figure 2-5 Selected RX ADC Physical Connections...................................................................5
Figure 2-6 ADC Control Interface ...............................................................................................6
Figure 2-7 ADC Clock Interface..................................................................................................6
Figure 2-8 ADC Data Interface...................................................................................................6
Figure 4-1 AC-Coupled Passband Profile 1 MHz to 750 MHz...................................................10
Figure 4-2 AC-Coupled Passband Profile 1 MHz to 300 MHz...................................................11
Figure 4-3 20.17 MHz, -1.0dBFS,.............................................................................................11
Figure 4-4 70.17 MHz, -4.8 dBFS,............................................................................................11
Figure 4-5 125.17 MHz, -2.0dBFS............................................................................................12
Figure 4-6 Terminated Input.....................................................................................................12
Figure 4-7 Two-tones 19.5 and 20.5 MHz at -7dBFS..............................................................12
Figure 4-8 Two-tones 124.5 and 125.5 MHz at -8dBFS............................................................12
Figure 4-9 DC-Coupled Passband Profile DC to 600 MHz........................................................13
Figure 4-10 DC-Coupled Passband Profile DC to 260 MHz......................................................13
Figure 4-11 20.17 MHz, -1 dBFS,.............................................................................................14
Figure 4-12 70.17 MHz, -1 dBFS,.............................................................................................14
Figure 4-13 125.17 MHz, -1dBFS.............................................................................................14
Figure 4-14 Terminated Input...................................................................................................14
Figure 4-15 Two-tones 19.5 and 20.5 MHz at -7dBFS............................................................14
Figure 4-16 Two-tones 69.5 and 70.5 MHz at -7dBFS..............................................................14
Figure 4-17 Characterization Setup..........................................................................................15
List of Tables
Table 2-1 Lowpass Filter Build Option Parameters.....................................................................3
Table 3-1 Test Environment ........................................................................................................7
Table 3-2 Absolute Maximum Specifications..............................................................................9
Table 4-1 Characterization Test Equipment..............................................................................15
Table 5-1 Key Hardware Components......................................................................................16

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1.0 Introduction
1.1 Contents and Structure
This manual describes the Front End 000-009 receiver hardware. The focus of this
manual is the electrical function of the hardware including control structure, signal flow and
key components.
The latest product documentation and software is available for download from the Red
Rapids web site (www.redrapids.com) by following the Technical Support link.
1.2Conventions
This manual uses the following conventions:
Hexadecimal numbers are prefixed by “0x” (e.g. 0x00058C).

Text in this format highlights useful or important information.
!
Text shown in this format is a warning. It describes a situation
that could potentially damage your equipment. Please read
each warning carefully.
The following are acronyms used in this manual.
AC Alternating Current (Greater than 0 Hertz)
ADC Analog to Digital Converter
DAC Digital to Analog Converter
dB Decibels
dBFS Decibels Relative to Full Scale
dBm Decibels Relative to One milliwatt
DC Direct Current (0 Hertz)
FFT Fast Fourier Transform
LVDS Low Voltage Differential Signaling
MHz Megahertz
mV millivolts
MSPS Mega Samples per Second
PGA Programmable Gain Amplifier
RF Radio Frequency
SFDR Spur Free Dynamic Range
SINAD Signal-to-Noise and Distortion Ratio
SNR Signal-to-Noise Ratio
Vpp Voltage, peak-to-peak
1.3 Revision History
Version
Date
Description
R00
1/21/2016
Initial release.
Placeholder
Table 1-1 Placeholder

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2.0 Description
The Front End 000-009 receiver is a high performance dual-channel structure built around
the Analog Devices AD9652 16 bit 310 Msps dual ADC.
Features1:
Dual Channel
16-bit Architecture
SNR 75 dB
SFDR 94 dB
Sample Rate up to 310 Msps
PGA Front End (2.0 Vpp or 2.5 Vpp Input)
3-Pole Chebyshev or Butterworth lowpass input filter (optional)
400 MHz Full Power Bandwidth
AC or DC Coupled (Build option)
Precision DC offset adjustment (DC-Coupled option)
Note 1: Features listed are mode and build dependent. See specifications and
performance sections for more information.
A block diagram of the receiver is shown in Figure 2-1. The receiver consists of two
independent analog input channels labeled 1 and 2. A receiver channel consists of a front
panel SMA connector, an optional signal conditioning filter and a coupling mechanism (AC
or DC) that bridges the analog input to the ADC. Analog inputs are digitized by a dual
ADC that creates discrete data samples and streams them to the data Interface using a
high-speed precision clock distributed from a low noise network.
The following paragraphs provide details about each element of the receiver section.
Receiver
Data
Interface
Clock
Interface
DC Offset
Adjust
Control Interface Control Interface
ADCB
RX 2
SMA SMA
RX 1 ADCA
RX 1, RX 2
CouplingFilter
CouplingFilter
Dual ADC Interleaved
Figure 2-1 Receiver Block Diagram

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2.1 Filter Build Option
The Front End Receiver has two filter build options. The standard build bypasses the
filter section to provide maximum frequency response. As an option each receiver is
designed to accommodate a 3-pole lumped element single ended Butterworth or
Chebyshev lowpass filter. Table 2-1 provides a summary of the filter build option
parameters. The filter is located at the receiver input prior to coupling and is useful for
limiting broadband noise and harmonic distortion entering the ADC. The default build
bypasses the input filter section.
Table 2-1 Lowpass Filter Build Option Parameters
Parameter
Value
Filter Type
Chebyshev or Butterworth
Number of Poles
3
3 dB Bandwidth (Cutoff)
10 to 325 MHz
Passband Ripple (Chebyshev)
0.1 dB standard
2.2 Coupling
The receiver is available AC or DC coupled as a build option as shown in Figure 2-2.
AC coupled units typically offer better high frequency performance and SNR at the
expense of low frequency operation. DC-coupled units provide for good mid/low
frequency operation down to DC with the expense of added noise and distortion from
the coupling amplifier.
AC units block DC signal content with a 0.1 uF series capacitor and are transformer
coupled to the ADC. DC-coupled units use a differential amplifier to couple the input
signal to the ADC. The differential amplifier also provides signal gain allowing unit
operation with a lower input signal amplitude range. DC-coupled units require a dc-
coupled system source impedance of 50 Ohms to ensure proper coupling amplifier
bias. Other source impedances are supported as a build option.

DC-coupled units require a dc-coupled source impedance of
50 Ohms as part of double balanced system.
Input
SMA
50 Ohms
GND
0.1uF
GND
Input
SMA
+
-
ADC
ADC
50 Ohms
GND
GND
AC-Coupled Build Option
DC-Coupled Build Option
Figure 2-2 Coupling Options (equivalent circuits)

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2.3 DC Offset Adjustment (DC-Coupled units only)
The DC-coupled receiver option contains a set of DACs to trim larger DC offset errors
that are induced by the coupling amplifier and system DC mismatch. A block diagram
of the trim DAC structure is shown in Figure 2-3. The DC offset trimming function is
implemented using a dual DAC in a push-pull configuration. The polarity control for
the offset is different between channel 1 and 2 due to layout constraints. In channel 1
trim DAC A controls positive offset while DAC B controls negative offset. Channel 2
has the opposite structure. DAC B offsets the ADC input voltage in a positive direction
while DAC A offsets the ADC input in a negative direction. Trim DAC register settings
can be found in the device data sheet listed in section 5.0. The receiver trim DACs are
accessed through the Control Interface via a SPI bus as shown in Figure 2-4.

Only one of the pair of offset trim DACs per input should be
active at a time. The unused trim DAC should be set to 0 V.
Analog
Input
DACA
DACB
+
-
Control Interface
ADC
GND
Trim DAC
pos
neg
Analog
Input
DACB
DACA
+
-
Control Interface
ADC
GND
Trim DAC
pos
neg
Channel 1 DC Offset Adjustment
Channel 2 DC Offset Adjustment
Figure 2-3 Trim DAC Operation in DC-Coupled Build Option

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Trim
DAC
Control
Interface
CS_LD
DIN
SCK
spi_csb(n)
spi_sdi
spi_clk
Device Configuration
(SPI Bus)
Figure 2-4 Trim DAC Control
2.4 ADC Configuration
The receiver ADC has a number of configuration options available to support different
modes of operation. The following sections describe the physical connection of the
device in terms of hardwired board connections, clock inputs and control/data
interfaces accessible to the user. Operational modes are described in the ADC device
data sheet listed in section 5.0. .
2.4.1 ADC Hardware Interface
Selected ADC component physical pin connections are shown in Figure 2-5. The
figure shows logical connection of the RX channel interface and individual discrete
control pins described in the device data sheet listed in section 5.0.
Receiver
ADC
TEST
SENSE
0
SYNC
PDWN
49.9
10.0k
10.0k RBIAS
VREF
0.1 uF 1.0 uF
10.0k
Receiver
ADC
ADCA
ADCB
Analog RX CH 2
Analog RX CH 1
Figure 2-5 Selected RX ADC Physical Connections

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2.4.1 ADC Control Interface
A diagram of the ADC control interface is shown in Figure 2-6. The user has access to
the ADC command and status registers through the control interface SPI port. A list
and description of ADC command and status registers can be found in the device data
sheet listed in section 5.0.
Receiver
ADC
Control
Interface
SPI_CSB
SPI_SDIO
SPI_SCLK
spi_csb(n)
spi_sdi
spi_sdo
spi_clk
Device Configuration
(SPI Bus)
Figure 2-6 ADC Control Interface
2.4.1 ADC Clock Interface
The receiver ADC clock input is sourced by the sample clock distribution network as
shown in Figure 2-7.
Sample Clock
Distribution Network Receiver
ADC
CLKINP
CLKINM
Figure 2-7 ADC Clock Interface
2.4.2 ADC Data Interface
A diagram of the ADC data interface is shown in Figure 2-8. The interface consists of
a forwarded LVDS data clock, a 16-bit LVDS interleaved data bus and a single over
range LVDS pair. A description of the data transfer protocol can be found in the RX
ADC device data sheet listed in section 5.0.
ADC Data
Interface
DCOP
DCOM
D(15:0)P
D(15:0)M
rx_clkp
rx_clkn
rx_datap(15:0)
rx_datan(15:0)
rx_ovrp
rx_ovrn
OVRP
OVRM
ADC
Interface
Figure 2-8 ADC Data Interface