Reflex PLDA XpressGX5LP-QE User manual

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Version 2.0.0 November 2015
Copyright © ReFLEX CES 2015
XpressGX5LP-QE
Reference Manual
Custom Embedded Systems
by

XpressGX5LP-QE Reference Manual
2
XpressGX5LP-QE
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ReFLEX CES. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by ReFLEX CES in good faith. This document is
provided “as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness
for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. ReFLEX CES shall not be liable for
any loss or damage arising from the use of any information in this document, or any error or omission in such
information, or any incorrect use of the product. Nor shall ReFLEX CES be liable for infringement of proprietary
rights relating to use of information in this document. No license, express or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein.
Date Doc Version Board Version Change
November 2015 2.0.0 P133_v1.0.0 •ReFLEX CES Update
October 2014 1.0.0 P133_v1.0.0 •First release

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XpressGX5LP-QE Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 XpressGX5LP-QE Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 XpressGX5LP-QE Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3 XpressGX5LP-QE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1 Stratix V GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Board Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Transceiver Clock Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7 DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Dual QSFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Time Stamping on Micro BNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 Extension Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14 EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.15 PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.16 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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XpressGX5LP-QE Reference Manual
List of Tables
Table 1: Board features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Stratix V GX FPGA Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: FlashPROM pin assignments on the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4: FlashPROM pin assignments + FPGA configuration signals on the CPLD . . . . . . . . . . . . . . . 15
Table 5: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6: Management signals pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7: XpressGX5LP-QE clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8: Transceiver clock tree pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10: DDR3L SDRAM pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11: QSFP+ 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12: QSFP+ 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13: Time stamping signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14: Extension interface pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15: Extension interface clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18: Pin assignments for the mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19: Pin assignments for the EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20: Pin assignments for the PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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XpressGX5LP-QE Reference Manual
List of Figures
Figure 1: XpressGX5LP-QE layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2: XpressGX5LP-QE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3: XpressGX5LP-QE mechanical architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4: Board Configuration component side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5: Board configuration solder side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6: Max II EPM 570 board configuration module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7: Max II board manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8: Reference Clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10: DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11: QSFP+ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12: Dual QSFP+ interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13: MicroBNC for time stamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14: Extension interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15: User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16: Reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18: Power Distribution for the XpressGX5LP-QE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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XpressGX5LP-QE Reference Manual
Preface
About this Document
This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who
are evaluating or using the ReFLEX CES XpressGX5LP-QE board. Prior knowledge of PCI Express is assumed.
Additional Reading
ReFLEX CES periodically updates its documentation. Please contact ReFLEX CES Technical Support or check
the Web site at http://www.reflexces.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 3.0
•PCI Express Card Electromechanical Specification, Revision 2.0
Feedback and Contact Information
Feedback about this document
ReFLEX CES welcomes comments and suggestions about this documentation. Please contact ReFLEX CES
Technical Support and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
ReFLEX CES
2, rue du Gévaudan - SILIC 1743
Lisses
91047 EVRY Cedex
FRANCE
Tel: [phone]
Fax: [phone]
http://www.reflexces.com
Sales
For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact ReFLEX CES Support at https://support.reflexces.com using the
Support Center if you have a ReFLEX CES online account.
If you don’t have a ReFLEX CES account, contact https://support.reflexces.com.

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XpressGX5LP-QE Reference Manual
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX5LP-QE board is designed to enable all engineers, even those with little PCI Express
experience, to design complex applications using PCIe and 10 Gigabit Ethernet as their main communication
interfaces.
The XpressGX5LP-QE is a low-profile, highly-integrated PCI Express FPGA board with quad-10 G or 40 G
Ethernet channels engineered for both prototyping and field deployment.
The board is based on the Altera Stratix V GX in the FBGA 1517 package and is available with either the
5SGXEA7K2F40C2N or the 5SGXEA4K2F40C2N FPGA.
1.2 Features List
•PCI Express x8 2.5/5.0/8.0 Gbps (Gen 1, 2 or 3)
•PCI Express edge connector
•Stratix V GX FPGA
•5SGXEA7K2F40C2N or 5SGXEA4K2F40C2N
•Two QSFP+ connectors
•Up to eight 1G/10G Ethernet or any high-speed link via QSFP+ to SPF+ splitter cable
•or up to two 40Gbs links
•Board configuration module
•Power monitoring
•Power-Up and reset controller
•IP protection (ReFLEX CES Protocore)
•FPGA configuration functionality supports
•Complete FPGA configuration from Flash Devices
•Flash image boot management
•FPGA re-load functionality
•PPS interface on MicroBNC connector for time stamping
•Clock circuitry
•FPGA configuration (Flash): 50 MHz
•PCIe: 100 MHz
•DDR3: 200 MHz
•QSF+/extension interface: 8 similar clocks (max skew=40ps) with 644.53125MHz or I2C PLL output
•Memories
•Two 4 GB DDR3L-1333 SDRAM with 72-bit data path (2x8GB capable)
•512 MB Flash
•Two 256Kbit I2C EEPROMs
•Extension Serial link
•Board capabilities extension or board-to-board connection over SAMTEC LSHM connector
•General I/Os
•Eight user LEDs
•Four FPGA configuration LEDs
•One reset button
•One FPGA configuration reload button
•One FPGA image boot selector
•Three user switches
•Board-to-board Interface (8 GXB Rx/Tx + 10 LVCMOS)

XpressGX5LP-QE Reference Manual
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•Power supply
•PCI Express edge connector power (12 V and 3.3 V)
•Power derived directly from PCI Express slot
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.
1.3 System Requirements
To use XpressGX5LP-QE board features, you must install the ReFLEX CES Software Tools. The ReFLEX CES
Software Tools can be downloaded from ReFLEX CES’s extranet site. You can log in to the extranet from
ReFLEX CES’s web site www.reflexces.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 13.0

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XpressGX5LP-QE Reference Manual
Chapter 2 XpressGX5LP-QE Architecture
The XpressGX5LP-QE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express
12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX5LP-QE by default. This daughter card is supplied with the XpressGX5LP-QE board. See Section 3.16
for more information.
The XpressGX5LP-QE is delivered with a fansink mounted on the FPGA.
2.1 XpressGX5LP-QE Layout
The following figure shows the component side of the XpressGX5LP-QE board without the mezzanine power
supply daughter card:
Figure 1: XpressGX5LP-QE layout

XpressGX5LP-QE Reference Manual
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2.2 Block Diagram of the Board
The XpressGX5LP-QE board is based on an Altera Stratix V GX FPGA, as shown below:
Figure 2: XpressGX5LP-QE block diagram