Reflex PLDA XpressGX5LP-QE User manual

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Version 2.0.0 November 2015
Copyright © ReFLEX CES 2015
XpressGX5LP-QE
Reference Manual
Custom Embedded Systems
by

XpressGX5LP-QE Reference Manual
2
XpressGX5LP-QE
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ReFLEX CES. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by ReFLEX CES in good faith. This document is
provided “as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness
for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. ReFLEX CES shall not be liable for
any loss or damage arising from the use of any information in this document, or any error or omission in such
information, or any incorrect use of the product. Nor shall ReFLEX CES be liable for infringement of proprietary
rights relating to use of information in this document. No license, express or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein.
Date Doc Version Board Version Change
November 2015 2.0.0 P133_v1.0.0 •ReFLEX CES Update
October 2014 1.0.0 P133_v1.0.0 •First release

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XpressGX5LP-QE Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 XpressGX5LP-QE Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 XpressGX5LP-QE Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3 XpressGX5LP-QE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1 Stratix V GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Board Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Transceiver Clock Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7 DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Dual QSFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Time Stamping on Micro BNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 Extension Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14 EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.15 PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.16 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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XpressGX5LP-QE Reference Manual
List of Tables
Table 1: Board features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Stratix V GX FPGA Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: FlashPROM pin assignments on the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4: FlashPROM pin assignments + FPGA configuration signals on the CPLD . . . . . . . . . . . . . . . 15
Table 5: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6: Management signals pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7: XpressGX5LP-QE clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8: Transceiver clock tree pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10: DDR3L SDRAM pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11: QSFP+ 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12: QSFP+ 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13: Time stamping signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14: Extension interface pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15: Extension interface clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18: Pin assignments for the mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19: Pin assignments for the EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20: Pin assignments for the PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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XpressGX5LP-QE Reference Manual
List of Figures
Figure 1: XpressGX5LP-QE layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2: XpressGX5LP-QE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3: XpressGX5LP-QE mechanical architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4: Board Configuration component side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5: Board configuration solder side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6: Max II EPM 570 board configuration module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7: Max II board manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8: Reference Clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10: DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11: QSFP+ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12: Dual QSFP+ interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13: MicroBNC for time stamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14: Extension interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15: User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16: Reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18: Power Distribution for the XpressGX5LP-QE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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XpressGX5LP-QE Reference Manual
Preface
About this Document
This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who
are evaluating or using the ReFLEX CES XpressGX5LP-QE board. Prior knowledge of PCI Express is assumed.
Additional Reading
ReFLEX CES periodically updates its documentation. Please contact ReFLEX CES Technical Support or check
the Web site at http://www.reflexces.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 3.0
•PCI Express Card Electromechanical Specification, Revision 2.0
Feedback and Contact Information
Feedback about this document
ReFLEX CES welcomes comments and suggestions about this documentation. Please contact ReFLEX CES
Technical Support and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
ReFLEX CES
2, rue du Gévaudan - SILIC 1743
Lisses
91047 EVRY Cedex
FRANCE
Tel: [phone]
Fax: [phone]
http://www.reflexces.com
Sales
For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact ReFLEX CES Support at https://support.reflexces.com using the
Support Center if you have a ReFLEX CES online account.
If you don’t have a ReFLEX CES account, contact https://support.reflexces.com.

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XpressGX5LP-QE Reference Manual
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX5LP-QE board is designed to enable all engineers, even those with little PCI Express
experience, to design complex applications using PCIe and 10 Gigabit Ethernet as their main communication
interfaces.
The XpressGX5LP-QE is a low-profile, highly-integrated PCI Express FPGA board with quad-10 G or 40 G
Ethernet channels engineered for both prototyping and field deployment.
The board is based on the Altera Stratix V GX in the FBGA 1517 package and is available with either the
5SGXEA7K2F40C2N or the 5SGXEA4K2F40C2N FPGA.
1.2 Features List
•PCI Express x8 2.5/5.0/8.0 Gbps (Gen 1, 2 or 3)
•PCI Express edge connector
•Stratix V GX FPGA
•5SGXEA7K2F40C2N or 5SGXEA4K2F40C2N
•Two QSFP+ connectors
•Up to eight 1G/10G Ethernet or any high-speed link via QSFP+ to SPF+ splitter cable
•or up to two 40Gbs links
•Board configuration module
•Power monitoring
•Power-Up and reset controller
•IP protection (ReFLEX CES Protocore)
•FPGA configuration functionality supports
•Complete FPGA configuration from Flash Devices
•Flash image boot management
•FPGA re-load functionality
•PPS interface on MicroBNC connector for time stamping
•Clock circuitry
•FPGA configuration (Flash): 50 MHz
•PCIe: 100 MHz
•DDR3: 200 MHz
•QSF+/extension interface: 8 similar clocks (max skew=40ps) with 644.53125MHz or I2C PLL output
•Memories
•Two 4 GB DDR3L-1333 SDRAM with 72-bit data path (2x8GB capable)
•512 MB Flash
•Two 256Kbit I2C EEPROMs
•Extension Serial link
•Board capabilities extension or board-to-board connection over SAMTEC LSHM connector
•General I/Os
•Eight user LEDs
•Four FPGA configuration LEDs
•One reset button
•One FPGA configuration reload button
•One FPGA image boot selector
•Three user switches
•Board-to-board Interface (8 GXB Rx/Tx + 10 LVCMOS)

XpressGX5LP-QE Reference Manual
8
•Power supply
•PCI Express edge connector power (12 V and 3.3 V)
•Power derived directly from PCI Express slot
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.
1.3 System Requirements
To use XpressGX5LP-QE board features, you must install the ReFLEX CES Software Tools. The ReFLEX CES
Software Tools can be downloaded from ReFLEX CES’s extranet site. You can log in to the extranet from
ReFLEX CES’s web site www.reflexces.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 13.0

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XpressGX5LP-QE Reference Manual
Chapter 2 XpressGX5LP-QE Architecture
The XpressGX5LP-QE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express
12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX5LP-QE by default. This daughter card is supplied with the XpressGX5LP-QE board. See Section 3.16
for more information.
The XpressGX5LP-QE is delivered with a fansink mounted on the FPGA.
2.1 XpressGX5LP-QE Layout
The following figure shows the component side of the XpressGX5LP-QE board without the mezzanine power
supply daughter card:
Figure 1: XpressGX5LP-QE layout

XpressGX5LP-QE Reference Manual
10
2.2 Block Diagram of the Board
The XpressGX5LP-QE board is based on an Altera Stratix V GX FPGA, as shown below:
Figure 2: XpressGX5LP-QE block diagram

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XpressGX5LP-QE Reference Manual
2.3 Board Features
The following table describes XpressGX5LP-QE board features:
Table 1: Board features description
Feature
name Description
For more
information,
see ...
FPGA configuration
module
A 32-bit configuration module (50 MHz) is available to configure the FPGA at
each board power-up.
This module consists of two 2 Gbit Numonyx Flash devices and an Altera CPLD.
The Flash devices can be programmed using ReFLEX CES's FlashPCI software.
Each device is directly connected to FPGA pins.
Section 3.2
JTAG connector The JTAG connector enables FPGA configuration via an Altera USB-Blaster and
Quartus.
Max II Board Manager This MAX II Board Manager CPLD is dedicated to IP protection, CvP
, partial
reconfiguration, and power and temperature management.
Section 3.3
x8 PCI Express 3.0 male
connector
This connector supports PCI Express at 2.5, 5.0, and 8.0 Gbps for x8, x4, and x1
link width. PCI Express is provided via FPGA transceivers.
Section 3.6
DDR3L SDRAM Two independent banks of DDR3L-SDRAM are available. Each bank consists of
9 x 4 Gb (8-bit wide) chips, which feature:
Section 3.7
QSFP+ interfaces Two QSPF+ interfaces connected to eight FPGA transceivers to enable 2 x
40Gbs links or up to 8 x 10Gbs links. All links have the same reference clock.
Section 3.8
Time stamping (PPS) on
Micro BNC
The board provides a Time Stamping feature via a MicroBNC connector. Time
Stamping can be effected using one of three electrical formats:
Section 3.9
Extension interface The extension interface provides access to eight Rx/Tx GxB transceivers to
enable board-to-board data transfers up to 80 Gbps. This interface also provides
10 other LVCMOS25 signals data transfer of up to 40 Gbps.
--
LEDs 8 user LEDs are available on the component side of the board. Section 3.11
Reset button 1 local power-on reset button on the component side of the board. Section 3.12
Switches 3 micro switches on the component side. Section 3.13
EEPROMs Two 256k-bit Serial FlashPROMs are available for data storage via two I²C links Section 3.14
Power supply Power is provided via a daughter card supplied by the PCIe slot (12/3.3 V). Section 3.16
•Up to 4 Gbytes density (4 Gbytes are mounted by default)
•72-bit data path
•Up to 800 MHz clock frequency
•Maximum throughput of 12.8 Gbytes per bank
•Schmitt trigger
•ADC converter (serial bus)
•Basic comparator

XpressGX5LP-QE Reference Manual
12
2.4 Mechanical Description
The following diagram illustrates the mechanical architecture of the XpressGX5LP-QE board without the fansink
mounted.
Note: The overall height of the board, that is, the height of the highest component, is 14mm.
Figure 3: XpressGX5LP-QE mechanical architecture

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XpressGX5LP-QE Reference Manual
Chapter 3 XpressGX5LP-QE Features
3.1 Stratix V GX FPGA Device
The XpressGX5LP-QE board can be mounted with either the Altera 5SGXEA7K2F40C2N or the
5SGXEA4K2F40C2N FPGA. The following table shows the resources of each available Stratix V GX FPGA:
Table 2: Stratix V GX FPGA Resources
FPGA LEs Registers M20K RAM
Blocks
M20K
Memory
18x18
Multipliers
27x27
Multipliers PLL
5SGXA4 420 K 634 K 1900 37 Mbits 512 512 24
5SGXA7 622 K 939 K 2560 50 Mbits 256 256 28
3.2 Board Configuration Module
The XpressGX5LP uses an EPM570F100 Max II CPLD as a 32-bit FPP Configuration Module.
The FPP module consists of 2 x 256MB PC28F00BP30 Micron 16-bit FlashPROMs that are directly connected to
the FPGA on the FPP 32-bit interface.
At FPGA power-up, the CPLD acts as an address counter to configure the FPGA.
Both FlashPROMs are directly accessible via the FGPA, and the address bus and control signals are shared
between the FPGA and the CPLD.
MSEL signals available on the CPLD enable the FPGA configuration type to be modified.
The SW1-4 switch enables you to select a boot sector (0 or 1), while the push button BPCONF on the solder side
enables you to reconfigure the FPGA with one of the two Flash boot sectors (depending on the position of SW1-4).
Figure 4: Board Configuration component side

XpressGX5LP-QE Reference Manual
14
The BPCONF button and SW1-4 switch on the solder side of the board are shown below:
Figure 5: Board configuration solder side
The following diagram shows the board configuration module:
Figure 6: Max II EPM 570 board configuration module
The following table shows pin assignments for the FlashPROMs on the FPGA:
Flash Data Flash Address Flash Control
flash_data00 AP33 flash_ad00 AM28 flash_oe0# AT24
flash_data01 AT33 flash_ad01 AL27 flash_rst0# AV23
flash_data02 AR33 flash_ad02 AM29 flash_ce0# AT23
flash_data03 AU34 flash_ad03 AW26 flash_wp0# AU23
flash_data04 AU33 flash_ad04 AN27 flash_adv0# AU24
flash_data05 AN31 flash_ad05 AN25 flash_we0# AP25
flash_data06 AM31 flash_ad06 AL26 flash_wait0 AW23
Table 3: FlashPROM pin assignments on the FPGA

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XpressGX5LP-QE Reference Manual
The following table shows the pin assignments of the FlashPROMs and FPGA configuration signals on the CPLD.
flash_data07 AU32 flash_ad07 AK29 -- --
flash_data08 AT32 flash_ad08 AM25 flash_oe1# AV25
flash_data09 AR31 flash_ad09 AM26 flash_rst1# AN28
flash_data10 AP31 flash_ad10 AL29 flash_ce1# AK30
flash_data11 AW34 flash_ad11 AL30 flash_wp1# AP27
flash_data12 AV34 flash_ad12 AR27 flash_adv1# AR28
flash_data13 AW31 flash_ad13 AT27 flash_we1# AU25
flash_data14 AV31 flash_ad14 AN24 flash_wait1 AU26
flash_data15 AW32 flash_ad15 AK27 -- --
flash_data16 AV32 flash_ad16 AJ27 flash_clk AU27
flash_data17 AJ33 flash_ad17 AN26 -- --
flash_data18 AH33 flash_ad18 AP28 -- --
flash_data19 AL33 flash_ad19 AT26 -- --
flash_data20 AK33 flash_ad20 AJ29 -- --
flash_data21 AK32 flash_ad21 AL28 -- --
flash_data22 AJ32 flash_ad22 AW25 -- --
flash_data23 AH31 flash_ad23 AR25 -- --
flash_data24 AG31 flash_ad24 AK26 -- --
flash_data25 AF31 flash_ad25 AV26 -- --
flash_data26 AE31 flash_ad26 AL25 -- --
flash_data27 AJ30 -- -- -- --
flash_data28 AH30 -- -- -- --
flash_data29 AR30 -- -- -- --
flash_data30 AP30 -- -- -- --
flash_data31 AU30 -- -- -- --
Flash Address Flash Control FPGA Configuration CPLD Status/Control + FPGA
flash_ad00 J3 flash_clk E3 msel0 J9 osc_config_cpld E2
flash_ad01 J4 -- -- msel1 J8 -- --
flash_ad02 K3 flash_adv0# B6 msel2 K10 max_sw0 A10
flash_ad03 K5 flash_wp0# B8 msel3 J10 -- --
flash_ad04 K4 flash_ce0# C8 msel4 H9 max_confdone B9
Table 4: FlashPROM pin assignments + FPGA configuration signals on the CPLD
Flash Data Flash Address Flash Control
Table 3: FlashPROM pin assignments on the FPGA

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Note: In the table above, RFU signifies signals that are reserved for future use.
Configuration MAX is the first device available on the JTAG chain. This device must never be deleted.
The following table shows the memory mapping for the Flash Access Module:
Table 5: Flash Memory Mapping
Name Size Address
FPGA Sector 1 or User Sector
(SW1-4 = 1)
64MB 7FF FFFF
400 0000
Sector 0
(SW1-4 = 0)
64MB 3FF FFFF
000 0000
flash_ad05 J6 flash_rst0# C7 -- -- max_leduser0 C9
flash_ad06 J5 flash_wait0 B7 nconfig K1 max_leduser1 B10
flash_ad07 G2 flash_oe0# A7 init_done K2 max_leduser2 C10
flash_ad08 H7 flash_we0# A6 dclk_cpld A8 -- --
flash_ad09 H4 -- -- clrconfig# A9 conf_rfu0 G9 AV22
flash_ad10 G3 flash_adv1# C2 nstatus G10 conf_rfu1 D9 AR24
flash_ad11 F2 flash_wp1# D1 conf_done H10 conf_rfu2 F9 AR22
flash_ad12 D2 flash_ce1# F1 -- -- conf_rfu3 F10 AV21
flash_ad13 D3 flash_rst1# F3 -- -- conf_rfu4 H8 AM23
flash_ad14 E8 flash_wait1 A3 -- -- conf_rfu5 D8 AW22
flash_ad15 B1 flash_oe1# A4 -- -- conf_rfu6 G8 AL24
flash_ad16 A2 flash_we1# B5 -- -- conf_rfu7 D10 AP24
flash_ad17 C4 -- -- -- -- conf_rfu8 K8 AN23
flash_ad18 C1 -- -- -- -- conf_rfu9 E9 AT21
flash_ad19 B3 -- -- -- -- -- --
flash_ad20 A1 -- -- -- -- -- --
flash_ad21 B2 -- -- -- -- -- --
flash_ad22 K6 -- -- -- -- -- --
flash_ad23 A5 -- -- -- -- -- --
flash_ad24 C3 -- -- -- -- -- --
flash_ad25 B4 -- -- -- -- -- --
flash_ad26 K7 -- -- -- -- -- --
Flash Address Flash Control FPGA Configuration CPLD Status/Control + FPGA
Table 4: FlashPROM pin assignments + FPGA configuration signals on the CPLD

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3.3 Board Manager
A second Max II CPLD is dedicated to IP protection, Configuration via Protocol (CvP), Partial Reconfiguration, and
power and temperature management.
The following figure shows the Max II board manager:
Figure 7: Max II board manager
The following table shows the pin assignments of the management signals on the CPLD and other components:
Signal CPLD Pin FPGA or Component Pin Comment
Protocore
osc_config_proto E10 Na MAX Main clock input (50MHz)
-- -- -- --
proto_led0 B1 DSMAX3 (Red LED) MAX LEDs: NDY
proto_led1 C2 DSMAX4 (Green LED)
proto_led2 C1 DSMAX5 (Orange LED)
proto_led3 D1 MAX2OK (Green LED)
-- -- -- --
prot0_out D9 FGPA: AC24 Protocore reset
-- -- -- --
prot1_in0 B8 FPGA: AE21 IP protection # 1
prot1_in1 G9 FPGA: AD22
prot1_out D8 FPGA: AE20
-- -- -- --
prot2_in0 C8 FPGA: AD21 IP protection #2
prot2_in1 G10 FPGA: AD23
prot2_out H9 FPGA: AG22
-- -- -- --
Table 6: Management signals pin assignments

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fpga_proto_misc0 G8 FPGA: AG21 IP protection misc signals
fpga_proto_misc1 E8 FPGA: AD20
fpga_proto_misc2 B7 FPGA: AH21
fpga_proto_misc3 E9 FPGA: AF22
fpga_proto_misc4 C7 FPGA: AJ21
fpga_proto_misc5 F10 FPGA: AB24
POR
por_VCCR_GXB B6 -- Power good from GXB DC/DC
converters
por_VCCA_GXB J6 --
ddr3_pgood J10 -- Power good from DDR3L
termination managers
-- -- -- --
ddr3_slp_s3 H10 -- Sleep mode input of DDR3L
termination managers
-- -- -- --
fpga_power_good F9 FPGA: AE22 Global power good
Temp MGT/PCIe SMBU
smb_temp_d K3 LM83: 12 Temperature Data information
inputs
smb_temp_clk K4 LM83: 14
-- -- -- --
temp_int# J3 LM83 : 11 Heat sink command output
Temperature critical warning
temp_crit# J4 LM83 : 16
-- -- -- --
pcie_sm_dat H8 PCIe connector: JB6 NDY
pcie_sm_clk J8 PCIe connector: JB5 NDY
Partial Reconfig/CVP
pr_error C9 FPGA: AU29 Partial reconfiguration control pins:
RFU
pr_ready D10 FPGA: AN29
pr_request B9 FPGA: AN30
pr_done B10 FPGA: AT30
-- -- --
cvp_confdone C10 FPGA: AT29
max2_link0 A10 CONF_CPLD: G1 Link between the two MAX II
CPLDs for POR signals.
max2_link1 B2 CONF_CPLD: H1
clrconfig E3 CONF_CPLD: A9 Reset push button
Signal CPLD Pin FPGA or Component Pin Comment
Table 6: Management signals pin assignments

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Note: This device is the last device on the JTAG chain.
3.4 Dedicated Clocks
The following table describes clock assignments for the board.
Table 7: XpressGX5LP-QE clock assignments
Global Clock Inputs
osc_config_FPGA AV29 LVCMOS25 Single-ended 50MHz clock used for the Max II CPLDs.
Osc3 p/n AK23/AL23 LVDS 125 MHz CLK used for PCIe Hard IP.
Osc5 p/n E34/D34 LVDS 200 MHz CLK dedicated to DDR3L Bank1.
Osc7 p/n AR8/AT8 LVDS 200 MHz CLK dedicated to DDR3L Bank0.
Osc8 p/n G7/G6 LVDS 200 MHz CLK dedicated to QDR2 banks.
Qsfp1_refclk0_p/n AF6/AF5 LVDS 644.53125MHz or I²C PLL clock for QSFP+ and extension
interface connectors.
Max skew between the 8 clocks is 40ps. See Section 3.5 for
more information.
Qsfp1_refclk1_p/n AD7/AD6 LVDS
Qsfp2_refclk2_p/n AB6/AB5 LVDS
Qsfp2_refclk3_p/n Y7/Y6 LVDS
Herma1_refclk4_p/n V6/V5 LVDS
Herma1_refclk5_p/n T7/T6 LVDS
Herma2_refclk6_p/n V34/V35 LVDS
Herma2_refclk7_p/n T33/T34 LVDS
Pcie_clk_100MHz p/n AF34/AF35 HCSL 100 MHz Transceiver RefCLK for PCIe Gen2.
Signal FPGA Pin Type Comment
GXB Transceiver Clock Inputs

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3.5 Transceiver Clock Tree
The QSFP+ and Extension interface links are connected to four different GxB transceivers, each featuring two
reference clock inputs.
These eight clock inputs are fed by the same clock frequency with a maximum skew of 40ps.
The clock frequency can either be a fixed 644.53125MHz/50ppm frequency or a user-defined clock from an I²C
PLL (Si570FBB0042DG). The clock type can be selected via a signal coming from the FPGA.
Table 8: Transceiver clock tree pin assignment
Clk_sel_644 B11 LVCMOS25 Select the ‘’2 to 8’’ multiplexer input. Logical ‘0’ will set I²C
PLL, and Logical ‘1’ will set a fixed 644.53125MHz frequency
(default) as the clock input.
SDA A11 LVCMOS25 I²C data line
SCL A10 LVCMOS25 I²C clock line
Figure 8: Reference Clock inputs
Signal FPGA Pin Type Comment