Renesas ISL81802EVAL1Z User manual
ISL81802EVAL1Z
Evaluation Board
R16UH0002EU0100 Rev.1.00 Page 1 of 23
Aug.24.20
User Manual
The ISL81802EVAL1Z dual-phase evaluation board (shown in Figure 4) features the ISL81802, an 80V high
voltage dual synchronous buck controller that offers external soft-start, independent enable functions, and
integrates UV/OV/OC/OT protection. A programmable switching frequency ranging from 100kHz to 1MHz helps to
optimize inductor size while the strong gate driver delivers up to 20A for the buck output.
Key Features
• Wide input range: 18V to 80V
• High light-load efficiency in pulse skipping DEM operation
• Programmable soft-start
• Optional DEM/PWM operation
• Optional CC/HICCUP OCP protection
• Supports pre-bias output with soft-start
• PGOOD indicator
• OVP, OTP, and UVP protection
• Back biased from output to improve efficiency
Specifications
The ISL81802EVAL1Z dual-phase evaluation board is designed for high current applications. The current rating of
the ISL81802EVAL1Z is limited by the FETs and inductor selected. The ISL81802EVAL1Z electrical ratings are
shown in Ta ble 1.
Ordering Information
Related Literature
For a full list of related documents, visit our website:
•ISL81802 device page
Table 1. ISL81802EVAL1Z Electrical Ratings
Parameter Rating
Input Voltage 18V to 80V
Switching Frequency 200kHz
Output Voltage 12V
Output Current 20A
OCP Set Point Minimum 22A at ambient room temperature
Part Number Description
ISL81802EVAL1Z High Voltage Dual Buck Controller Evaluation Board
ISL81802EVAL1Z
R16UH0002EU0100 Rev.1.00 Page 2 of 23
Aug.24.20
Figure 1. ISL81802EVAL1Z Block Diagram
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ISL81802EVAL1Z 1. Functional Description
R16UH0002EU0100 Rev.1.00 Page 3 of 23
Aug.24.20
1. Functional Description
The ISL81802EVAL1Z is the same test board used by Renesas application engineers and IC designers to
evaluate the performance of the ISL81802 TQFN IC. The board provides an easy and complete evaluation of all
the IC and board functions.
As shown in Figure 3, 18V to 80V VIN is supplied to J1 (+) and J2 (-). The regulated 12V output on J4 (+) and
J5 (-) can supply up to 20A to the load. Due to the high power efficiency, the evaluation board can run at 20A
continuously without airflow at ambient room temperature conditions.
Test points TP1 through TP23 provide easy access to the IC pin and external signal injection terminals.
As shown in Tabl e 2 , connector J6 provides a selection of either Forced PWM mode (shorting Pin 1 and Pin 2) or
DEM mode (shorting Pin 2 and Pin 3). Connector J7 provides a selection of either constant current limit (shorting
Pin 1 and Pin 2) or HICCUP OCP (shorting Pin 2 and Pin 3). Connector J3 provides an option to disable the
converter by shorting its Pin 1 and Pin 2.
1.1 Recommended Testing Equipment
The following materials are recommended for testing:
• 0V to 80V power supply with at least 30A source current capability
• Electronic loads capable of sinking current up to 30A
• Digital Multimeters (DMMs)
• 100MHz quad-trace oscilloscope
1.2 Operating Range
The input voltage range is from 18V to 80V for an output voltage of 12V. If the output voltage is set to a lower
value, the minimum VIN can be reset to a lower value by changing the ratio of R1and R5. The minimum EN
threshold that VIN can be set to is 4.5V.
The rated load current is 20A with the OCP point set at a minimum 22A at ambient room temperature conditions.
The operating temperature range of this board is -40°C to +85°C.
Note: Airflow is needed for higher temperature ambient conditions.
ISL81802EVAL1Z 1. Functional Description
R16UH0002EU0100 Rev.1.00 Page 4 of 23
Aug.24.20
1.3 Quick Test Guide
1. Jumper J6 provides the option to select PWM or DEM. Jumper J7 provides the option to select a constant
current limit or HICCUP. See Table 2 for the operating options. Ensure that the circuit is correctly connected to
the supply and electronic loads before applying any power. See Figure 3 for the proper setup.
2. Turn on the power supply.
3. Adjust the input voltage (VIN) within the specified range and observe the output voltage. The output voltage
variation should be within 3%.
4. Adjust the load current within the specified range and observe the output voltage. The output voltage variation
should be within 3%.
5. Use an oscilloscope to observe output voltage ripple and phase node ringing. For accurate measurement, see
Figure 2 for the proper test setup.
Table 2. Operating Options
Jumper Position Function
3 EN-GND Disable output
EN Floating Enable output
6Pin1-2 PWM
Pin 2-3 DEM
7 Pin 1-2 Constant current limit
Pin 2-3 HICCUP
Figure 2. Proper Probe Setup to Measure Output Ripple and Phase Node Ringing
Figure 3. Proper Test Setup
Output Capacitor
or MOSFET
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ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 5 of 23
Aug.24.20
2. PCB Layout Guidelines
Careful attention to Printed Circuit Board (PCB) layout requirements is necessary for the successful
implementation of an ISL81802 based DC/DC converter. The ISL81802 switches at a high frequency; therefore,
the switching times are short. At these switching frequencies, even the shortest trace has significant impedance
and the peak gate drive current rises significantly in an extremely short time. The transition speed of the current
from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and
ringing. Careful component selection and proper PCB layout minimize the magnitude of these voltage spikes.
Three sets of components are critical when using the ISL81802 DC/DC converter:
• Controller
• Switching power components
• Small-signal components
The switching power components are the most critical to the layout because they switch a large amount of energy,
which tends to generate a large amount of noise. The critical small-signal components are those connected to
sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.
Complete the following steps to optimize the PCB layout.
1. Place the input capacitors, FETs, inductor, and output capacitor first. Isolate these power components on
dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output
high frequency decoupling ceramic capacitors very close to the MOSFETs.
2. If signal components and the IC are placed separately from the power train, Renesas recommends using full
ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise,
use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND
together close to the IC. Note: DO NOT connect them together anywhere else.
3. Keep the loop formed by the input capacitor, the top FET, and the bottom FET as small as possible.
4. Ensure the current paths from the input capacitor to the FETs, the power inductor, and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the lower FETs. The low-side FETs gate drive connections should be
short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.
6. Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND
pin. Connect the PGND pin to the ground plane by a via.
Note: DO NOT connect the PGND pin directly to the SGND EPAD.
7. Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.
8. Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output
capacitors to load to avoid inductance and resistances.
9. Use copper filled polygons or wide, short traces to connect the junction of the upper FET, lower FET, and output
inductor. Keep the PHASE nodes connection to the IC short. Note: DO NOT unnecessarily oversize the copper
islands for the PHASE nodes. Because the phase nodes are subjected to very high dv/dt voltages, the stray
capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.
10. Route all high speed switching nodes away from the control circuitry.
11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. Connect all
small signal grounding paths including feedback resistors, current monitoring resistors and capacitors,
soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors to this SGND
plane.
12. Use a pair of traces with minimum loop for the input or output current sensing connection.
13. Ensure the feedback connection to the output capacitor is short and direct.
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 6 of 23
Aug.24.20
2.1 ISL81802EVAL1Z Evaluation Board
Figure 4. ISL81802EVAL1Z Evaluation Board, Top View
Figure 5. ISL81802EVAL1Z Evaluation Board, Bottom View
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 7 of 23
Aug.24.20
2.2 ISL81802EVAL1Z Circuit Schematic
Figure 6. Schematic
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ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 8 of 23
Aug.24.20
2.3 Bill of Materials
Qty Reference Designator Description Manufacturer Manufacturer Part
1 PWB-PCB, ISL81802EVAL1Z,
REVB, ROHS
Multilayer PCB Technology ISL81802EVAL1ZREVBPCB
2 C1, C2 CAP, RADIAL, 12.5x26.5, 220μF,
100V, 20%, ALUM.ELEC., 5mm,
ROHS
United Chemi-Con EKZN101ELL221MK25S
8 C3, C4, C5, C6, C42, C43,
C44, C45
CAP-AEC-Q200, SMD, 1210,
4.7μF, 100V, 10%, X7S, ROHS
TDK CGA6M3X7S2A475K200AB
1 C7 CAP, SMD, 0603, 1000pF, 50V,
10%, X7R, ROHS
TDK C1608X7R1H102K080AE
2 C8, C41 CAP, SMD, 0603, 0.1µF, 100V,
10%, X7R, ROHS
Vishay GRJ188R72A104KE11D
6 C9, C27, C47, C48, C49, C50 CAP, SMD, 0603, 0.01µF, 100V,
5%, X7R, ROHS
Kemet C0603C103J1RACTU
1 C11 CAP, SMD, 0603, 10µF, 16V, X5R,
10%, ROHS
Murata GRM188R61C106KAALJ
1 C12 CAP, SMD, 0603, 100PF, 50V,
X7R, 10%, ROHS
Kemet C0603C101K5RACTU
1 C46 CAP, SMD, 0603, 10PF, 50V, X7R,
10%, ROHS
Kemet C0603C100K5RACTU
1 C15 CAP, SMD, 0603, 220pF, 50V,
10%, X7R, ROHS
Murata GRM188R71H221KA01D
2 C16, C39 CAP, SMD, 0603, 0.47µF, 25V,
10%, X7R, ROHS
Murata GRM188R71E474KA12D
1 C17 CAP, SMD, 0603, 4700PF, 50V,
X7R, ROHS
Murata GCJ188R71H472KA01D
8 C18, C19, C20, C23, C34,
C35, C36, C37
CAP, SMD, 1210, 22µF, 25V, X7R,
ROHS
Murata GRM32ER71E226KE15L
2 C21, C38 CAP-OSCON, SMD, 10mm,
1000μF, 16V, 20%, 12mΩ, ROHS
Panasonic 16SVPF1000M
1 C22 CAP, SMD, 0603, 0.047µF 25V
X7R, ROHS
Kemet C0603C473K3RACTU
2 C24, C26 CAP, SMD, 0805, 10µF, 16V, 10%,
X7S, ROHS
Murata GRM21BC71C106KE11L
1 C28 CAP, SMD, 0603, 820pF, 50V,
10%, X7R, ROHS
Kemet C0603C821K5RACTU
0 C13, C14, C25, C51, C52,
C33
CAP, SMD, 0603, DNP-PLACE
HOLDER, ROHS
3 D1, D3, D4 DIODE-RECTIFIER, SMD, 2P,
S0D-123FL, 100V, 1A, ROHS
ON Semiconductor MBR1H100SFT3G
4 J1, J2, J4, J5 HDWARE, TERMINAL, M4
METRIC SCREW, TH, 4P,
SNAP-FIT, ROHS
Keystone 7795
1 J3 CONN-HEADER, 1x2, BRKAWY
1x36, 2.54mm, ROHS
BERG/FCI 68000-236HLF
2 J6, J7 CONN-HEADER, 1x3,
BREAKAWY 1x36, 2.54mm,
ROHS
BERG/FCI 68000-236HLF
0 J10, J11, J12, J13, J14, J15 2.54mm Headers, DNP-PLACE
HOLDER, ROHS
2 L1, L2 COIL-PWR INDUCTOR, SMD,
6.8μH, 20%, 15A, 4.1mΩ, ROHS
Wurth 74439370068
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 9 of 23
Aug.24.20
1 U1 80V DUAL-BUCK PWM
CONTROLLER, 32P, TQFN, 5x5,
ROHS
Renesas Electronics America ISL81802FRTZ
4 Q1, Q4, Q6, Q8 TRANSISTOR-MOS,
N-CHANNEL, SMD, 8P, PPK
SO-8, 100V, 80A, ROHS
Infineon BSC070N10NS5ATMA1
0 Q2, Q3, Q5, Q7 DO NOT POPULATE OR
PURCHASE
1 R1 RES SMD 430kΩ1% 1/4W 1206 Panasonic ERJ-8ENF4303V
1 R2 RES SMD 487kΩ1% 1/10W 0603 Yageo RC0603FR-07487KL
4 R5, R38, R39, R40 RES SMD 48.7kΩ1% 1/10W 0603 Yageo RC0603FR-0748K7L
1R3 RESSMD20Ω1% 1/10W 0603 Yageo RC0603FR-0720RL
4 R6, R10, R25, R29 RES SMD 1Ω1% 1/10W 0603 Panasonic ERJ-3RQF1R0V
1R7 RESSMD5.1Ω1% 1/10W 0603 Yageo RC0603FR-075R1L
4 R8, R18, R30, R32 RES SMD 21kΩ1% 1/10W 0603 Yageo RC0603FR-0721KL
1 R11 RES SMD 1kΩ1% 1/10W 0603 Yageo RC0603FR-071KL
1 R12 RES SMD 34.8kΩ1% 1/10W 0603 Yageo RC0603FR-0734K8L
2 R14, R22 RES SMD 0.004Ω3W 2512 WIDE Susumu KRL6432E-M-R004-F-T1
2 R16, R21 RES SMD 5.1Ω1% 1/10W 0603 Yageo RC0603FR-075R1L
1 R19 RES SMD 169kΩ1% 1/10W 0603 Venkel CR0603-10W-1693FT
1 R20 RES SMD 2.7kΩ1% 1/10W 0603 Yageo RC0603FR-072K7L
2 R23, R26 RES SMD 100kΩ1% 1/10W 0603 Yageo RC0603FR-07100KL
2 R31, R33 RES SMD 39kΩ1% 1/10W 0603 Yageo RC0603FR-0739KL
2 R41, R52 RES SMD 0Ω1% 1/10W 0603 Yageo RC0603FR-070RL
0 R34, R35, R42, R43, R44,
R45, R46, R47, R48, R49,
R50, R51, R53, R54, R55,
R17, R15, R27, RT2, RT3,
RES, SMD, 0603, DNP-PLACE
HOLDER, ROHS
13 TP1, TP2, TP3, TP5, TP7,
TP9, TP10, TP13, TP14,
TP15, TP18, TP22, TP23
CONN-COMPACT TEST PT,
VERTICAL, WHT, ROHS
Keystone 5007
3 J3, J6, J7 CONN-
JUMPER,SHORTING,2PIN,BLAC
K,GOLD,ROHS
Sullins SPC02SYAN
4 Four corners SCREW, 4-40x1/4in, PHILLIPS,
PANHEAD, STAINLESS, ROHS
Keystone 2204
4 Four corners STANDOFF, 4-40x3/4in, F/F, HEX,
ALUMINUM, 0.25 OD, ROHS
Keystone 7795
Qty Reference Designator Description Manufacturer Manufacturer Part
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 10 of 23
Aug.24.20
2.4 Board Layout
Figure 7. Silkscreen Top
Figure 8. Top Layer
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 11 of 23
Aug.24.20
Figure 9. Second Layer (Solid Ground)
Figure 10. Third Layer
ISL81802EVAL1Z 2. PCB Layout Guidelines
R16UH0002EU0100 Rev.1.00 Page 12 of 23
Aug.24.20
Figure 11. Bottom Layer
Figure 12. Silkscreen Bottom
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 13 of 23
Aug.24.20
3. Design Example
3.1 Design Requirements
3.2 Frequency Setting
The default switching frequency of the PWM controller is determined by the resistor RT (R19). It adjusts the default
switching frequency from 100kHz to 1MHz. The RT value for fSW = 200kHz is calculated using Equation 1.
where fSW is the switching frequency in MHz. Select a standard value resistor RT = 169kΩ.
3.3 Output Voltage Setting
The output voltage can be set from 0.8V up to a level determined by the feedback voltage divider. A resistive
divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT
pin. With VOUT = 12V and RFBO1 (R2) = 487k, the RFBO2 (R12) value is calculated using Equation 2.
where RFBO1 (R2) is the top resistor of the feedback divider network and RFBO2 (R12) is the bottom resistor
connected from FB_OUT to ground. To avoid an unstable state during hiccup, the value of RFBO1 and RFBO2 in
parallel should be no less than 30k. Select a standard value resistor RFBO2 = 34.8kΩ.
3.4 UVLO Setting
The ISL81802 has input UVLO protection. When the voltage on the EN/UVLO pin reaches 1.8V, the PWM
modulator is enabled. Accurate UVLO feature can be implemented by feeding the VIN into the EN/UVLO pin using
a voltage divider, RUV1 (R1) and RUV2 (R5). The VIN UVP rising threshold is calculated using Equation 3.
The VIN UVP falling threshold is calculated using Equation 4.
where VUVLO_THR is the 1.8V UVLO rising threshold and IUVLO_HYST is the 6.8µA UVLO hysteresis current.
Parameter Rating
Input Voltage 18V to 80V
Switching Frequency 200kHz
Output Voltage 12V
Output Current 20A
OCP Set Point 22A
Output Mode Dual phase
PWM Mode Forced PWM
OCP Mode Constant current
RT
34.7
fSW
----------- 4.78–
34.7
0.2
----------- 4.78–168.72k===
(EQ. 1)
RFBO2
0.8V RFBO1
VOUT 0.8V–
-------------------------------------- 0.8V 487k
12V 0.8V–
------------------------------------- 34.78k===
(EQ. 2)
(EQ. 3) VUVRISE
VUVLO_THR RUV1 RUV2
+ILEAK
–RUV1RUV2
RUV2
----------------------------------------------------------------------------------------------------------------------------------1.8V 430k48.7k+2.8A–430k48.7k
48.7k
-------------------------------------------------------------------------------------------------------------------------------------16.49V== =
(EQ. 4)
VUVFALL
VUVLO_THR RUV1 RUV2
+IUVLO_HYST–RUV1RUV2
RUV2
--------------------------------------------------------------------------------------------------------------------------------------------------------1.8V 430k48.7k+6.8A–430k48.7k
48.7k
-------------------------------------------------------------------------------------------------------------------------------------14.77V===
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 14 of 23
Aug.24.20
3.5 Soft-Start Capacitor
The soft-start time for dual-phase is set by the value of the soft-start capacitor CSS (C22) connected from SS/TRK1
to GND. The soft-start time with CSS = 47nF is calculated using Equation 5.
When the soft-start time set by external CSS or tracking is less than 1.7ms, an internal soft-start circuit of 1.7ms
takes over the soft-start.
3.6 MOSFET Considerations
The MOSFETs are selected based on rDS(ON), gate supply requirements, and thermal management
considerations. The maximum operation voltage of the MOSFETs in Buck mode is decided by the maximum VIN
voltage.
The power loss of the upper and lower MOSFETs for each phase is calculated using Equation 6 and Equation 7.
The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery
for the body diode of the lower MOSFET.
Ensure that all MOSFETs are within their maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal resistance specifications.
3.7 Inductor Selection
The inductor value determines the ripple current of the converter. The ripple voltage is a function of the ripple
current and the output capacitor(s) ESR. Assume the ripple current ratio is 80% of the inductor average current at
the maximum input voltage and the full output load condition. The inductor value for each phase is calculated
using Equation 8.
The recommended inductor value is 6.8µH. Then the ripple current and peak current are calculated using
Equation 9, Equation 10, and Equation 11.
tSS 0.8V
CSS
4A
-----------
0.8V 47nF
4A
--------------
9.4ms== =
(EQ. 5)
PUPPERMAX
IOUT
2
rDS ON
VOUT
VINMAX
-----------------------------------------------------------------------IOUT
VINMAX
tSW
fSW
2
------------------------------------------------------------------------------
+
10A2
6m12V
80V
------------------------------------------------------
10A80V 6nC
8V 4.9V–
3.3
--------------------------
--------------------------------6nC
4.9V
3.3
-------------
-------------------
+
200kHz
2
---------------------------------------------------------------------------------------------------------------------------
+0.09W 0.834W+0.843W
=
===
(EQ. 6)
PLOWERMAX
IOUT
2
rDS ON
VINMAX VOUT
–
VINMAX
---------------------------------------------------------------------------------------------------
10A
26m80V 12V–
80V
------------------------------------------------------------------------0.51W
=
==
(EQ. 7)
LINMIN
VINMAX VOUT
–VOUT
fSW
0.8 IOUTMAX
VINMAX
------------------------------------------------------------------------------------------80V 12V–12V
200kHz0.8 10A80V
--------------------------------------------------------------------------6.375H===
(EQ. 8)
ILMAX
VINMAX VOUT
–VOUT
fSW
LVINMAX
---------------------------------------------------------------------- 80V 12V–12V
200kHz6.8H80V
-----------------------------------------------------------------7.5A===
(EQ. 9)
ILRMS IOUTMAX
2ILMAX
2
12
-----------------------------
+10A
27.5A
2
12
--------------------
+10.23A===
(EQ. 10)
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 15 of 23
Aug.24.20
The saturation current of the inductor should be larger than 14.75A. The heat rating current of the inductor should
be larger than 10.23A.
The maximum DC power dissipation in the inductor is calculated using Equation 12.
3.8 Output Capacitor Selection
The minimum capacitor value required to provide the full, rising step, transient load current during the response
time of the inductor is shown in Equation 13.
where COUTMIN is the minimum output capacitor(s) required, ITRAN is the transient load current step, and ΔVOUT
is the drop in output voltage allowed during the load transient. Choose a capacitor no less than 314.8µF for each
phase. 1000µF electrolytic capacitor and 88µF MLCC in total are used for each phase on this board.
The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by
Equation 14.
3.9 Input Capacitor Selection
The important parameters for the input capacitors are the voltage rating and the RMS current rating. The
capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a
conservative guideline. The AC RMS input current varies with the load given in Equation 15.
where floor(2xD) equals 0 when D < 0.5 and equals 1 when D ≥0.5.
The maximum RMS current for two phases in total supplied by the input capacitance occurs at D = 0.25 and
D = 0.75, and only D = 0.25 is within the range of this application. Therefore, the maximum AC RMS current is
shown in Equation 16.
Renesas recommends using a mix of input bypass capacitors to control the voltage ripple across the MOSFETs.
Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Two
220µF electrolytic capacitors with 2.2A rating current and eight 4.7µF ceramic capacitors are used to share the
2.5A RMS input current on this board.
ILPEAKMAX
IOUTOCP
2
--------------------------ILMAX
2
---------------------
+22A
2
-----------7.5A
2
------------
+14.75A===
(EQ. 11)
PLMAX IOUT
2DCR10A
24.1m0.41W== =
(EQ. 12)
COUTMIN
LI
TRAN
2
2V
INMIN VOUT
–VOUT
-----------------------------------------------------------------------------6.8F10A0A–
2
218V 12V–12V 1.5
100
----------
---------------------------------------------------------------------- 314.8F===
(EQ. 13)
VRIPPLE ILMAX ESR7.5A 5m 37.5mV===
(EQ. 14)
IRMS Dfloor 2 D
2
--------------------------------
–
1 floor 2 D+
2
------------------------------------------ D–
IOUT
=
(EQ. 15)
IRMSMAX D1
2
---D–
IOUTMAX
0.25 1
2
---0.25–
10A2.5A===
(EQ. 16)
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 16 of 23
Aug.24.20
3.10 First Level Peak Current Limit and Sense Resistor Selection
The inductor peak current is sensed by the sense resistor RS (R14). When the voltage drop on RSreaches the set
point VOCSET-CS typical 85mV, it triggers the pulse-by-pulse peak current limit. With the current limit set point
IOCPP1 =2xI
OUTMAX = 20A for each phase, the value of the sense resistor is calculated using Equation 17.
Select a standard value resistor RS=4mΩ. Then the actual peak current limit is calculated using Equation 18.
The maximum power dissipation in RSis calculated by Equation 19.
Therefore, a sense resistor with 1W power rating is sufficient for this application.
3.11 Second Level Hiccup Peak Current Protection
In the output dead short condition especially at high VIN, the inductor current runs away with the minimum on
PWM duty. The ISL81802 integrates a second level hiccup type of peak current protection. The second level peak
current protection set point IOCPP2 is calculated using Equation 20.
3.12 Output Average Overcurrent Protection and RIM Selection
The ISL81802 provides either constant current or hiccup type of overcurrent protection for output average current.
The OCP mode is set by a resistor connected between the LG2/OC_MODE pin and ground. With output constant
current/hiccup set point IOUTOCP = 22A for two phases in total, the current monitoring resistor RIM (R8) is
calculated using Equation 21.
where ICSOFFSET is the output current sense op amp internal offset current, typical 20μA. Select a standard value
resistor RIM = 21kΩ.
3.13 Output Mode Selection
When the IMON2 pin voltage is higher than 3V, the IC is set for one output dual-phase application, and the
original IMON2 current monitor function pin is disconnected from the IMON2 pin and internally connected to the
IMON1 pin. The IMON2 pin is connected to VCC5 using R26 for dual-phase setting on this board.
3.14 PWM Mode Selection
You can set the ISL81802 to either forced PWM mode or DE mode. The mode is set by a resistor RPWMMODE (R30
or R31) connected between the LG1/PWM_MODE pin and GND. The boundary resistor value for RPWMMODE is
calculated using Equation 22.
RS
VOCSET CS–
IOCPP1
---------------------------------- 85mV
20A
---------------- 4.25m===
(EQ. 17)
IOCPP1
VOCSET CS–
RS
---------------------------------- 85mV
4m
---------------- 21.25A===
(EQ. 18)
PRSMAX IOUT
2RS10A
24m0.4W== =
(EQ. 19)
IOCPP2
VOCSET-CS-HIC
RS
--------------------------------------------115mV
4m
------------------- 28.75A===
(EQ. 20)
RIM
1.2
IOUTOCP RSGmCS
2I
CSOFFSET
+
----------------------------------------------------------------------------------------------------------------- 1.2V
22Ax4mx195S220A+
----------------------------------------------------------------------------------20.99k===
(EQ. 21)
(EQ. 22) RPWMMODE
0.3V
10A
---------------30k==
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 17 of 23
Aug.24.20
A resistor less than 30kΩsets the converter to forced PWM mode, while a resistor higher than 30kΩsets the
converter to DE mode. Considering the tolerance in all temperature ranges, Renesas recommends using 21kΩto
set Forced PWM mode and 39kΩto set DE mode.
3.15 Overcurrent Protection Mode Selection
The ISL81802 is set to either a constant current or hiccup type of overcurrent protection for output average
current by selecting a different value of the resistor ROCMODE (R32 or R33) connected between LG2/OC_MODE
and GND. The boundary resistor value for ROCMODE is calculated using Equation 23.
A resistor less than 30kΩsets the converter to constant current mode, while a resistor higher than 30kΩsets the
converter to Hiccup mode. Considering the tolerance in all temperature ranges, Renesas recommends using
21kΩto set constant current and 39kΩto set the Hiccup mode.
3.16 Phase Lock Loop (PLL)
The PLL of the ISL81802 ensures the wide range of accurate clock frequency and phase setting. It also makes
the internal clock easily synchronized to an external clock with the frequency either lower or higher than the
internal setting. The external compensation network of RPLL (R20), CPLL1 (C27), and CPLL2 (C28) is needed to
connect to the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩfor RPLL,
10nF for CPLL1, and 820pF for CPLL2.
3.17 Feedback Loop Compensation
Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency
determined by the load using Equation 24.
where ROis load resistance and COis total load capacitance for each phase. For this type of modulator, a Type 2
compensation circuit is usually sufficient.
Figure 13 shows a Type 2 amplifier and its response, along with the responses of the current mode modulator and
the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole. The RCOMP, CCOMP1, and CCOMP2 network connected on
the Gm regulator output COMP pin is needed to compensate the loop for stable operation. The loop stability can
be affected by many different factors such as VIN, VOUT, load current, switching frequency, inductor value, output
capacitance, and the compensation network on the COMP pin.
Figure 13. Feedback Loop Compensation
(EQ. 23) ROCMODE
0.3V
10A
---------------30k==
FPO
1
2ROCO
---------------------------------1
212V
10A
-----------1088F
------------------------------------------------ 122Hz== =
(EQ. 24)
Compensation
Converter
F
Z
F
P
F
P0
Vo
COMP
Vref
(0.8V)
Gm C
COMP1
R
FBO1
Type 2 Compensation
F
C
R
FBO2
Modulator
C3
C
COMP2
R
COMP
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 18 of 23
Aug.24.20
High amplifier zero frequency gain and modulator gain are chosen to satisfy most typical applications. The
crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency
gain. The crossover frequency FCis usually about 1/10 to 1/30 of switching frequency. To fulfill the various
applications, large value capacitors are used on the output side. Therefore, a reasonable target crossover
frequency FCin this application is 4kHz.
The compensation zero FZ is usually placed between FPO and FC. Setting FZto 1.6kHz, with
CCOMP1 (C17) = 4.7nF, the RCOMP (R18) is calculated using Equation 25.
Select a standard value resistor RCOMP =21kΩ. A larger CCOMP1 makes the loop more stable by giving a larger
phase margin, but the loop bandwidth is lower. Lower RCOMP improves stability but slows the loop response.
A high-frequency pole FP is placed by a capacitor CCOMP2 (C15) in parallel with RCOMP and CCOMP1. Set the
frequency of this pole at about 7 to 10 times of crossover frequency FCto provide attenuation of switching ripple
and noise on COMP, while avoiding excessive phase loss at the crossover frequency. For a target FP=35kHz,
the CCOMP2 is calculated using Equation 26.
Select a standard value capacitor CCOMP2 = 220pF.
Some phase boost can be achieved by connecting capacitor C3in parallel with the upper resistor RFBO1 of the
divider. These values provide a good starting point for the compensation design, and the final compensation
network should be optimized with bench test.
3.18 Parallel Connection
The ISL81802EVAL1Z evaluation board can operate in parallel, in a daisy chain setup. Figure 14 shows the wiring
of two units in parallel and Figure 15 shows three units in parallel.
Figure 14. Setup for Two Units in Parallel Figure 15. Setup for Three Units in Parallel
RCOMP
1
2FZCCOMP1
------------------------------------------------1
21.6kHz 4.7nF
----------------------------------------------------21.17k== =
(EQ. 25)
CCOMP2
1
2RCOMP1 FP
------------------------------------------------1
221k35kHz
------------------------------------------------- 216.6pF== =
(EQ. 26)
ISL81802EVAL1Z #2
J1
J2 J5
J4
J10
J11
VIN
GND
VOUT
GND
ISL81802EVAL1Z #1
J1
J2 J5
J4
J10
J11
VIN
GND
VOUT
GND
Load
-
+
DC
Source
+
-
ISL81802EVAL1Z #3
J1
J2 J5
J4
J10
J11
VIN
GND
VOUT
GND
ISL81802EVAL1Z #2
J1
J2 J5
J4
J10
J11
VIN
GND
VOUT
GND
ISL81802EVAL1Z #1
J1
J2 J5
J4
J10
J11
VIN
GND
VOUT
GND
Load
-
+
DC
Source
+
-
ISL81802EVAL1Z 3. Design Example
R16UH0002EU0100 Rev.1.00 Page 19 of 23
Aug.24.20
Tab le 3 shows the CLKOUT/DITHER phase settings with different EN/UVLO2 pin connection and IMON2 pin
voltage.
On the ISL81802EVAL1Z board, the IMON2 pin is tied to 5V and EN/UVLO2 is tied to EN/UVLO1, which leads to
a default 60° CLKOUT Phase Shift.
Table 3. CLKOUT and Channel 2 Phase Shift vs EN/UVLO2 and IMON2 Voltage
CLKOUT Phase Shift (°) Channel 2 Phase Shift (°) IMON2 Voltage (V) EN/UVLO2
90 180 0 to 4.3 Tie to EN/UVLO1
60 180 4.7 to 5 Tie to EN/UVLO1
240 120 3 to 5 Tie to SGND
Notes:
1. CLKOUT Phase Shift: CLKOUT rising edge delay after UG1 rising edge.
2. Channel 2 Phase Shift: UG2 rising edge delay after UG1 rising edge.
ISL81802EVAL1Z 4. Typical Performance Curves
R16UH0002EU0100 Rev.1.00 Page 20 of 23
Aug.24.20
4. Typical Performance Curves
VIN = 48V, TA= 25°C, unless otherwise noted.
Figure 16. Efficiency, CCM Figure 17. Load Regulation, CCM
Figure 18. Phase 1, Phase 2, IL1, IL2, VIN = 18V, IOUT = 20A Figure 19. Phase 1, Phase 2, IL1, IL2, VIN = 48V, IOUT = 20A
Figure 20. Phase 1, Phase 2, IL1, IL2, VIN = 80V, IOUT = 20A Figure 21. Load Transient, VIN = 18V, IOUT = 0A to 20A,
2.5A/µs, CCM
50
55
60
65
70
75
80
85
90
95
100
024681012141618
20
Efficiency (%)
I
OUT
(A)
Vin = 18V Vin = 24V
Vin = 36V Vin = 48V
Vin = 60V Vin = 80V
11.85
11.87
11.89
11.91
11.93
11.95
11.97
11.99
12.01
12.03
12.05
024681012141618
20
VOUT (V)
IOUT (A)
Vin = 18V Vin = 24V
Vin = 36V Vin = 48V
Vin = 60V Vin = 80V
2µs/Div
IL1 5A/Div
Phase 2 20V/Div
Phase 1 20V/Div
IL2 5A/Div
2µs/Div
IL1 5A/Div
Phase 2 20V/Div
Phase 1 20V/Div
IL2 5A/Div
2µs/Div
Phase 1 50V/Div
Phase 2 50V/Div
IL1 5A/Div IL2 5A/Div
2ms/Div
VOUT 100mV/Div
IOUT2 10A/Div
IOUT1 10A/Div
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