Renesas Tsi301 HyperTransport User manual

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©2009 Integrated Device Technology, Inc.
Tsi301™
HyperTransport to PCI
User Manual
80D3000_MA001_02
September 2009

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Tsi301 HyperTransport to PCI User Manual 6
Notes
About This Manual
This reference manual contains technical specifications for the Tsi301 HyperTransport PCI bridge chip.
The manual is intended for use by system designers and developers who are using the chipset in their
designs.
HyperTransportTM and LDT
In this manual, HyperTransportTM technology and LDT (Lightning Data Transport) are sometimes used
interchangeably. HyperTransportTM technology and LDT both refer to identical technology based on the same
specification.
Throughout the remainder of this manual HyperTransportTM technology is referred to as HyperTransport.
Silicon Revisions: Pass1 and Pass2
Silicon revisions are referred to as Pass1 and Pass 2 throughout this document. Pass1 refers to silicon
revisions 1.0 and 1.1. Pass2 refers to silicon revisions 2.0 and higher. Any information not flagged as specific
to Pass1 or Pass 2 is applicable to all Tsi301 bridges. Pass1 and Pass2 are italicized throughout this docu-
ment’s text to help identify the relevant information.
The following sections describe the intended audience, scope, and the organization of this reference
manual.
Audience
This reference manual is intended for system designers and others who design using the HyperTransport
PCI bridge, or who evaluate computer systems based on this chip.
Scope
This manual describes the features, requirements, and configurations for the HyperTransport PCI bridge,
including functional and physical details.
Specific details on industry standards (for example, PCI or ISA bus specifications) are not included. Addi-
tional information is available in the appropriate vendor and IEEE specifications.
Conventions and Definitions
This section describes stylistic conventions used in this manual, and defines product-specific terminology,
acronyms, and other technical language used throughout this manual.
Information Flags
Note: Notes highlight information that provides additional clarification or will ease tasks related to
the assembly and operation of the system.
Typographic Conventions
This manual uses the following type conventions:
•Italic type is used for document citations and information that provides supplemental clarification.
Pass1 and Pass2 are italicized throughout this document’s text to help identify the relevant
information.
•Courier font is used for type that appears on a screen, such as an example of computer
output.

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About This Manual
Notes
Tsi301 HyperTransport to PCI User Manual 6
Signals and Bits
•Active-Low Signals—Signal names ending in _N, such as SFILL_N, indicate active-low signals.
Active-low signals are asserted in their low-voltage state and negated in their high-voltage state.
•Active-High Signals are asserted in their high-voltage state and negated in their low-voltage state.
•Differential Signals—Differential signals are indicated by the _H and _L suffixes. Signals ending in _H
are the active-high half of a differential pair whereas signals ending in _L are the active-low half of a
differential pair.
•Signal Ranges—The highest and lowest signal numbers in a range of signals are contained in
brackets and separated by a colon; for example D[63:0].
•Reserved Bits and Signals—Signals or bus bits marked reserved must be driven inactive or left
unconnected, as indicated in the signal descriptions. These bits and signals are reserved by API
NetWorks, Inc. for future implementations. When software reads registers with reserved bits, the
reserved bits must be masked. When software writes such registers, it must first read the register and
change only the non-reserved bits before writing back to the register.
Data
The following list defines data terminology:
•Quantities
–A word (W) is two bytes (16 bits).
–A doubleword (DW) is four bytes (32 bits).
–A quadword (QW) is eight bytes (64 bits).
•Abbreviations—The following notation is used for bits and bytes:
–Kilo—K, as in 4-Kbyte page (210).
–Mega—M, as in 4 Mbits/sec (220).
–Giga—G, as in 4 Gbytes of memory space (230).
•Little-Endian Convention—The byte with the address xx...xx00 is in the least-significant byte position
(little end). In byte diagrams, bit positions are numbered from right to left: The little end is on the right,
and the big end is on the left.
•Bit Ranges—In text, bit ranges are shown with a colon (for example, 3:0). When accompanied by a
signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a
colon (for example, AD[31:0]).
•Bit Values—Bits can either be set to 1 or cleared/reset to 0.
•Hexadecimal and Binary Numbers—Unless the context makes interpretation clear, hexadecimal
numbers are followed by an h, binary numbers are followed by a b, and decimal numbers are followed
by a d.
Acronyms
The following is a list of acronyms used in this document.
Acronym Definition
APIC Advanced Programmable Interrupt Controller
BIOS Basic Input/Output System
CSR Control/Status Register
DAC Dual Address Cycle
DDR Double Data Rate
DMA Direct Memory Access
DRAM Direct Random Access Memory
ESBGA Enhanced Super Ball Grid Array
FIFO First In, First Out
HSTL High-Speed Transistor Logic
I/O Input/Output

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Notes
Tsi301 HyperTransport to PCI User Manual 6
ISA Industry Standard Architecture
LSB Least Significant Bit
LVD Low Voltage Differential
LVTTL Low Voltage Transistor-Transistor Logic
MRL Memory Read Line
MRM Memory Read Multiple
MSB Most Significant Bit
MWI Memory Write Invalid
NDA Non-disclosure Agreement
NMI Non-maskable Interrupt
ORC Outbound Request Controller
OS Operating System
PBGA Plastic Ball Grid Array
PCB Printed Circuit Board
PIO Programmed Input/Output
PCI Peripheral Component Interconnect
PLL Phase Locked Loop
SBGA Super Ball Grid Array
SDRAM Synchronous Direct Random Access Memory
SE Single-ended
SIP Serial Initialization Packet
SPD Serial Presence Detect
SRI Serial ROM Interface
SROM Serial Read Only Memory
SRAM Static Random Access Memory
SRM System Reference Manual
Acronym Definition

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About This Manual
Notes
Tsi301 HyperTransport to PCI User Manual 6

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1-10
Notes
Chapter 1 Bridge Features
This chapter describes the features and operation of the API NetWorks HyperTransport PCI bridge.
1.1 HyperTransport PCI Bridge Features
The HyperTransport PCI bridge is an I/O bridge from HyperTransport to PCI with the following features:
•An 8-bit HyperTransport primary interface capable of running at data rates up to 800 Mb/s and
compliant with Lightning Data Transport I/O Link Protocol Specification, Revision 1.0.
•A 64-bit, 66 MHz PCI secondary interface compliant with the PCI Local Bus Specification, Revision
2.2.
•A PCI arbiter supporting six external bus masters (not counting the Tsi301) and compliant with the PCI
Local Bus Specification, Revision 2.2.
•A HyperTransport interrupt controller with configurable support for up to 20 interrupt sources in Pass1,
and 16 interrupt sources in Pass2.
•A configuration register set and programming model consistent with the PCI-to-PCI Bridge
Architecture Specification, Revision 1.1.
•Power-up configuration through Serial Initialization Packet (SIP) or pin sampling.
1.2 HyperTransport Interface
The HyperTransport PCI bridge primary interface is a HyperTransport tunnel. The primary interface is
compliant with Lightning Data Transport I/O Link Protocol Specification, Revision 1.0 with the exception that
the Tsi301 does not support 2 and 4 bit HyperTransport interfaces and does not support Dynamic Frequency
Programming. The interface contains two HyperTransport links which allow the connection of multiple bridge
chips in a daisy-chain configuration.
Each HyperTransport link has an 8-bit DDR transmit and an 8-bit DDR receive port running at clock speeds
up to 400 MHz, allowing for raw bandwidth of 800 MB/s simultaneously in each direction. With protocol over-
head, the maximum sustainable bandwidth in one direction is approximately 705 MB/s.
•For testing, or connection to slower devices, the HyperTransport PCI bridge may be programmed to
operate at slower link clock rates.
•The HyperTransport PCI bridge supports both the synchronous and asynchronous modes of link
initialization.
1.3 PCI Interface
The HyperTransport PCI bridge secondary interface is a 64-bit, 66 MHz capable PCI bus. The HyperTrans-
port PCI bridge supports running the bus in 32-bit mode at either 33 MHz or 66 MHz. A lower performance
mode is also supported in which the PCI bus runs at 25 or 50 MHz. The bus can be configured for compati-
bility with 3.3 V or 5.0 V operation, although 50 and 66 MHz are only supported at 3.3 V.
The HyperTransport PCI bridge supports the full 40-bit memory-mapped space and 25-bit I/O space
described in the Lightning Data Transport I/O Link Protocol Specification, Revision 1.0. In Pass1, PCI
addresses outside these spaces alias into them. In Pass2, PCI addresses outside these spaces are left on the
PCI bus. PCI dual address cycle (DAC) support is provided both inbound and outbound to support the
memory-mapped space.
•The HyperTransport PCI bridge supports configuration accesses to devices 0–15, using Address/Data
(AD) bits 16–31 for IDSEL#.
•The HyperTransport PCI bridge implements all parity and error-checking features described in the PCI
Local Bus Specification, Revision 2.2.

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1.3.1 PCI Master
As a PCI master, the HyperTransport PCI bridge chip can generate MemRd/Wr, IORd/Wr, and ConfigRd/
Wr cycles.
•The HyperTransport PCI bridge does not implement a cacheline size register and does not prefetch to
PCI, so it never generates MemRdLine, MemRdMult, or MemWrInv cycles.
•The HyperTransport PCI bridge does not support a Southbridge connection to its PCI bus, so it never
generates INTA cycles.
•The HyperTransport PCI bridge does not generate Special cycles.
PCI master cycles that are retried or disconnected on the PCI bus are reissued locally by the HyperTrans-
port PCI bridge until they complete. The HyperTransport PCI bridge can track up to four outstanding requests
in the Outbound Request Controller, of which a maximum of three may be nonposted requests. The Hyper-
Transport PCI bridge rotates among these requests to maximize bandwidth in the presence of retries or
disconnects.
1.3.2 PCI Slave
As a PCI slave, the HyperTransport PCI bridge can respond to all types of memory and I/O cycles.
However, the HyperTransport PCI bridge never responds to PCI configuration cycles.
•The HyperTransport PCI bridge employs medium DEVSEL# timing.
•All PCI slave writes, including I/O writes, are posted.
•A total of 48 doublewords (DW) of write data buffering are provided on the chip.
•All PCI slave reads are implemented as delayed requests, with up to four delayed requests
outstanding at once.
Prefetching is supported for all flavors of memory read cycle, with separate prefetch controls for each cycle
type and a maximum prefetch per read of 128 DW. Prefetching may be done once at the beginning of each
read, or it may be enabled to continuously issue requests as data is drained to PCI. All prefetch data is
discarded when the read disconnects on the PCI bus. The bridge chip provides buffer space for a total of
256 DW of read prefetch data.
1.3.3 PCI Arbiter
The HyperTransport PCI bridge implements an on-chip two-level PCI Arbiter with request/grant pairs: 7
pairs in Pass1, 6 pairs in Pass2. The request/grant pairs in Pass1 include two high-priority sets for the on-chip
PCI master, one high priority set for an external requester, and five symmetrical sets for external device use.
In Pass2, there is one high-priority set for the on-chip PCI master.
All connections to the arbiter are through external pins, so its use is optional. The HyperTransport PCI
bridge chip may also be configured to use an external PCI arbiter.
1.4 Interrupt Controller
The HyperTransport PCI bridge implements a HyperTransport interrupt controller. In Pass1, there are
20 external interrupt sources. In Pass2, there are 16 external interrupt sources.
The interrupts pins may be programmed in groups of four to be level or edge-triggered and active high or
low. In Pass1, one group can also be used to generate the special PC compatibility interrupts: SMI, NMI, INIT,
and INTR. In Pass2, SMI, NMI, INIT, and INTR are not available.
1.5 Configuration
Most HyperTransport PCI bridge configuration is done under host software control through accesses
across HyperTransport to the bridge chip’s control/status register (CSR) set. However, some hardware initial-
ization is required to bring up the HyperTransport links before software configuration can occur. To support
hardware initialization, the HyperTransport PCI bridge provides a Serial Initialization Packet (SIP) interface to
read an external SROM during a cold reset sequence.

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Tsi301 HyperTransport to PCI User Manual 1-10
To reduce external part count, a small number of configurations are pre-programmed into the HyperTrans-
port PCI bridge. These pre-programmed configurations may be selected using PCI bus pins during cold reset
in the absence of an SROM.
1.6 Interface Levels
A complete pinout of the HyperTransport PCI bridge is given in the Signals Chapter. The rough grouping of
signal types is shown in Table 1.
1.7 Clocking
In normal operation, the HyperTransport PCI bridge’s reference clock (REFCLK_H/L) comes from a PCI
bus clock. This clock is received from the same source that drives clocks to devices on the bridge’s PCI bus
and is nominally in phase with it; although it may be delayed relative to the other PCI bus clocks. Reference
clock frequency is indicated by the P_M66EN pin. From this input, an internal phase locked loop (PLL) gener-
ates the HyperTransport PCI bridge internal core clock and the HyperTransport transmit clocks.
Note: In Pass1, the reference clock frequency and P_M66EN can be set at either 33 or 66 MHz at
L_PWROK and must remain static. In Pass2, clocks and P_M66EN can be used in the same way;
or the PCI bus frequency can be changed without resetting the HyperTransport PCI bridge. To
support changing the PCI bus frequency without resetting the HyperTransport PCI bridge,
REFCLK_H/L must always run at 33 MHz and P_M66EN must indicate 33 MHz at the rising edge of
L_PWROK. The clock frequency to the PCI devices and P_M66EN can then be switched between
33 and 66 MHz whenever AP_RST is asserted. The clocks must still be nominally in phase and
rising edges of the reference clock must be aligned with rising edges of the PCI bus clock.
If the HyperTransport PCI bridge is to perform synchronous link initialization with the HyperTransport
devices on either side of it, the reference clock must be derived from the same base frequency source. If not,
asynchronous link initialization must be used. No phase relationship is required in either mode.
For debug and test purposes, the HyperTransport PCI bridge allows bypassing of the PLL. It provides
separate bypass clock inputs for the core and HyperTransport transmit clocks. The bypass clocks run directly
at the frequency provided. Both bypass clocks must be derived from the same base frequency source.
Interface Group Voltages
PCI PCI 3.3V, 5.0V tolerant
HyperTransport HyperTransport Differential, 600 mV swing, centered on 600 mV
Interrupts INT In Pass1, 2.5 V
In Pass2, 3.3 V
Table 1 HyperTransport PCI Bridge Interface Voltages

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