RESEARCH MACHINES LINK 480Z User manual
480Z·
SERVICE
MANUAL
October 1984
380Z
AND
480Z
SYSTEMS
SERVICE
MANUAL
PN
13821
Copyright
c 1984
by
Research
Machines
Limited
All
rights
reserved.
Copies
of
this
publication
may
be
made
by
customers
exclusively
for
their
own
use,
but
otherwise
no
part
of
it
may
be
reproduced,
transmitted,
transcribed,
stored
in
a
retrieval
system,
or
translated
into
any
language
or
computer
language
without
the
prior
written
permission
of
Research
Machines
Limited,
Mill
St.,
Oxford,
England.
OX2
OBW.
Tel:
Oxford
(0865)
249866.
Research
Machines
has
a
policy
of
continuous
development
and
improvement
of
its
products
and
services,
and
the
right
is
reserved
to
revise
this
manual
or
to
make
changes
in
the
computer
software
it
describes
without
notice.
Research
Machines
endeavour
to
ensure
the
accuracy
of
this
manual
and
that
the
products
described
perform
correctly
according
to
their
descriptions.
However,
Research
Machines
Limited
do
not
accept
liability
for
the
consequences
of
any
error
or
omission.
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of
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may
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Machines
Limited
at
the
address
above.
Please
ask
for
the
title
as
given
above.
( . I
(
SECTION
1
SECTION
2
SECTION
3
(
SECTION
4
FIGURES
1.
1
2.1
2.2
2.3
2.4
(
2.s
2.6
2.1
3.1
3.2
3.3
3.4
3.5
3.6
4
.1
KEYBOARD
MAIN
PCB
BO-Character
Mode
40-Character
Mode
System
Read
Ports
System
Write
Ports
OPTION
PCB
CONTENTS
High
Resolution
Graphics
POWER
SUPPLY
General
Mains
Filter
and
Rectifier
Flyback
Converter
Snubbers
Secondary
Operation
Switching
PSU
Load
Box
Keyboard
Timing
Basic
M1
Cycle
and
Clocks
Port
Mapping
RAM
Mapping
RAM
Access
Cycle
Line
Wave£orm
Video
RAM
Video
Timing
Writing
to
HRG
Memory
Memory
Re-mapping
(HRG)
HRG
Modes
Extra
High
Resolution
High
Resolution
Medium
Resolution
Power
Supply
(i)
480Z
Service
Manual
1• 1
2.
1
2.8
2
.13
2
.14
2
.14
3.1
3.1
4.1
4.1
4.1
4.1
4.2
4.2
4.4
'
('
. (
480Z
Keyboard
SECTION
1
THE
KEYBOARD
(Circuit
ref.
:
Alphameric
Drawing
no.
146-1710)
There
are
64
keys,
each
generating
a
distinct
8-bit
code
(not
ASCII)
whenever
it
is
pressed
or
released,
accompanied
by
a
strobe
pulse.
In
fact,
only
6
bits
are
used,
with
bit
8
indicating
key
position
(0
= down,
1
=up).
The
keyboard
consists,
electrically,
of
an
8 x 8
matrix
which
is
scanned
to
check
key
status
(up
or
down).
This
scanning
is
accomplished
by
3
IC's:
1• IC 8
is
a
12-stage
binary
counter
clocked
by
oscillator
IC5b/IC6a
at
about
500
kHz.
The
clock
is
divided
by
8
(QO,
Q1,
and
Q2
are
not
used)
and
then
again
by
8 (Q3,
Q4
and
Q5
are
used
for
strobe
functions)
to
give
a
6-bit
key
address
count
which
is
placed
on
the
data
bus.
This
forms
part
of
the
data
byte
sent
to
the
processor
and
is
accompanied
(if
a
key
has
changed
state)
by
a
strobe
pulse
and
DEPRESSION
signal.
2.
IC 7
is
a
decoder
which
takes
the
three
most
significant
bits
of
the
key_
address
and
enables
the
appropriate
row
of
the
matrix,
provided
that
the
'D'
input
is
low.
As
'D'
is
connected
to
the
500
kHz
clock,
each
row
in
turn
outputs
a 500 kHz
signal.
3.
IC
1
is
an
analogue-type
multiplexer;
each
of
the
inputs
0
to
7
is
at
high
impedance,
except
for
the
one
selected
(by
pins
9,
10,
11)
which
is
connected
via
a few
hundred
ohms
resistance
to
the
Z
output.
Input
selection
comes
from
the
three
least
significant
bits
of
the
key
address,
and
so
this
forms
the
rest
of
the
scanning
operation.
Each
key
provides
a
capacitance
coupling
between
its
row
and
column,
and,
when
pressed,
couples
the
500 kHz
clock
to
the
Z
output
of
IC 1
at
the
appropriate
point
in
the
scanning
cycle.
The
function
of
the
circuitry
around
IC
2
is
to
detect
whether
or
not
the
selected
key
is
pressed.
It
operates
as
follows:
(N.B.
IC 2
transistors
will
be
referred
to
as
TR1
to
TR5
from
left
to
right).
•
Selected
key
not
pressed
R9
and
D1/D2
provide
a
1.5v
reference
for
the
base
of
TR2
and
for
each
of
the
matrix
columns
via
4k7
resistors.
The
output
of
IC 1
is
at
high
impedance
and
so
a
small
DC
current
flows
into
TR1
(via
L1)
and
TR2
bases.
As
TR2
collector
is
stable,
no
current
flows
through
CJ,
TR3
has
no
base
current
and
is
turned
off,
and
any
small
residual
charge
on
C4
is
insufficient
to
drive
TR5
base.
Consequently,
TRS
collector
is
high.
1• 1
480Z
Keyboard
•
Selected
key
pressed
There
is
now a 500 kHz
signal
from
IC 1
(referenced
to
02+)
which
is
amplified
by
the
resonant
circuit
L1/C2,
causing
the
current
through
TR1
to
oscillate.
The
current
through
TR2
oscillates
in
anti-phase
and
an
amplified
500 kHz
signal
appears
at
the
collector.
C1
prevents
the
oscillation
from
affecting
the
base
of
TR2.
During
negative
half-cycles,
C3
pulls
the
emitter
of
TR3
lower
than
its
base
(held
by
C4)
and
it
then
starts
to
conduct,
charging
C3.
During
positive
half-
cycles
the
charge
on
C3
flows
through
03
(TR3 now
turned
off)
to
carge
C4
and
provide
a
base
current
for
TRS.
Thus
TRS
collector
is
low.
Once a
key
address
has
been
set
in
IC
8,
some
time
elapses
to
allow
a
charge
to
build
up
on
C4,
if
the
key
is
pressed
(see
timing
diagram,
figure
1);
the
state
of
TRS
collector
is
then
clocked
into
IC
3a.
The
output
of
this
represents
the
state
of
the
key
and
forms
part
of
the
data
byte
sent
to
the
processor
(as
DEPRESSION).
At
the
start
of
each
key
address
cycle,
the
Q
output
of
IC 3b
turns
on
TR4
for
a
short
period
to
ensure
that
no
residual
(
_'
charge
remains
on
C4
from
the
previous
cycle.
As
the
keyboard
must
only
generate
strobe
pulses
when a
key
changes
state,
some
sort
of
memory
is
required;
this
is
IC
4,
a
64-bit
shift
register.
At
the
start
of
each
address
cycle
the
state
of
the
previous
key
(latched
in
IC
3a)
is
clocked
into
IC
4,
an
action
which
continues
as
the
keyboard
is
scanned.
As IC 4
is
clocked,
the
state
of
the
~urrently
addressed
key
during
the
last
scan
appears
at
the
output
and
is
compared
with
its
present
state
by
IC
Sa.
If
a
change
has
taken
place,
a
strobe
is
generated
near
the
end
of
the
cycle
by
IC
6b
and
IC Gd.
Holding
RESET
'low'
has
the
effect
of
clearing
the
shift
register
to
all
1's,
and
not
allowing
any
key
depressions
to
enter
IC
3a.
Keyboard
scanning
is
inhibited
(as
are
strobe
pulses)
by
taking
the
READY
line
low
(stopping
500 kHz
oscillator);
this
happens
automatically
when
the
480Z
receives
a
strobe,
and
is
returned
to
normal
when
the
CPU
reads
the
keyboard
data.
1.2
(
_..
•
w
IC.I-
Q5
Q4,Q~
IC!b -
C.
Icsb-i
lC3a,-D
IC.5&-Q
IC4-Q
STlt.08&
~
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----'
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--~,
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'n
,,n
n n
in
...
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11
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1:
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,...,
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_
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,,,
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I,,
I
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Down
1<'!1
Up
I I I
k.,
Up
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Down 1 I
K.,
Down I I
I I I I I I
---1
I I
._
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____
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I I I
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IC"
+wn
IA.at
biona
: !
I<.,
Mf
fa.st time
K!'I
down
last
bit.~
IC.,
wp
lo.st
t"im, :
I I I I
' n '
n~-----
' I I I I
I I I I I
I I I I I
Figure
1.1
Keyboard
Timing
~
co
0
N
~
~
0
Pl
t1
Qt
480Z Main
PCB
SECTION
2
MAIN
PCB
(Circuit
ref.
:
D10829,
Sheets
1
to
6)
SHEET
1
The
ZSOA
microprocessor
is
the
heart
of
the
system.
It
is
clocked
at
4MHz
from
the
oscillator
(sheet
4),
and
all
signals
directly
connected
to
this
are
prefixed
by
Z
(e.g.
ZWAIT).
To
save
using
high-speed
memories,
one
'wait'
state
is
inserted
in
each
memory
cycle
by
GT. One
'wait'
state
is
also
inserted
into
each
video
access
(to
be
described
later)
to
make
this
transparent
to
the
user.
Figure
2.1
shows
the
relationship
between
the
various
derivations
of
the
4MHz
clock,
and
the
timing
of
GT.
All
address
lines
go
through
buffers
which
are
permanently
enabled,
as
do
some
control
signals.
During
I/O
cycles,
lines
AO
to
A6
contain
the
port
address,
and
the
most
significant
lines
A2
to
A6
are
decoded
by
JS
(the
port
mapping
PROM)
when
enabled
by
IORQ.
In
this
system,
the
ZBO
operates
in
interrupt
mode
2,
and
no
port
is
enabled
during
interrupt
acknowledge
cycles
as
the
interrupting
device
is
automatically
enabled
by
the
combination
of
ZMI
and
ZIORQ
being
active.
Figure
2.2
shows
the
operation
of
JS.
If
the
group
of
system
ports
is
selected
(PORTEN
low)
the
address
is
further
decoded
(AO
-A2)
by
CU
and
DR
giving
5
read
and
5
write
ports,
which
are
used
for
control
and
status
information,
etc.
(as
shown
on
sheet
5).
The
'Z'
data
bus
is
used
directly
by
ROM
and
RAM,
and
is
buffered
to
give
a
'T'
data
bus
when
TDBUSEN
is
active.
This
is
used
mainly
by
I/O
ports
and
is
further
buffered
by
DQ
(write)
and
CQ
(read)
for
use
by
VDU
circuitry.
When
NMIEN
goes
active
(by
writing
to
system
port
0)
an
NMI
will
be
(
generated
during
the
ei9hth
successive
instruction.
This
is
used
by
the
ROS
monitor
for
single-stepping
through
programs.
The
power
up
circuitry
(C23,
GW
etc)
holds
the
CL
line
of
GU
low,
and
so
holds
RESET
low,
until
the
power
rails
have
stabilised.
Memory
contents
can
be
corrupted
during
reset
in
two
ways:
1.
While
RESET
is
active
no
refreshing
takes
place.
2.
If
RESET
goes
active
during
T3
of
an
M1
cycle,
a
short
MREQ
pulse
can
be
generated
which
may
destroy
data.
Thus,
in
order
to
preserve
memory
contents,
the
RESET
button
signal
is
gated
with
R3
(part
of
the
row
counter
in
video
circuit
which
happens
to
be
a
convenient
frequency)
and
synchronized
with
M1.
This
results
in
RESET
being
active
for
128us,
and
inactive
for
512us,
while
the·
button
is
pressed,
allowing
sufficient
time
to
2.1
~
a>
0
N
t1
~
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.....
t-h
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~
Tl
m
::r
Q
T2.
TW
TJ
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16MHZ
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0
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MCLC.K
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C.LCK
VDUAce/tPUACC
0
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11
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Z.WAIT
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~
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Fiqure
2.1
Basic
M1
Cycle
and
Clocks
-
.-----
_,
' ( .
480Z
Main
PCB
SECTION
2
MAIN
PCB
(Circuit
ref.
:
010829,
Sheets
1
to
6)
SHEET
1
The
ZSOA
microprocessor
is
the
heart
of
the
system.
It
is
clocked
at
4MHz
from
the
oscillator
(sheet
4),
and
all
siqnals
directly
connected
to
this
are
prefixed
by
Z
(e.g.
ZWAIT).
To
save
using
high-speed
memories,
one
'wait'
state
is
inserted
in
each
memory
cycle
by
GT. One
'wait'
state
is
also
inserted
into
each
video
access
(to
be
described
later)
to
make
this
transparent
to
the
user.
Figure
2.1
shows
the
relationship
between
the
various
derivations
of
the
4MHz
clock,
and
the
timing
of
GT.
All
address
lines
go
through
buffers
which
are
permanently
enabled,
as
do
some
control
signals.
During
I/O
cycles,
lines
AO
to
A6
contain
the
port
address,
and
the
most
significant
lines
A2
to
A6
are
decoded
by
JS
(the
port
mapping
PROM)
when
enabled
by
IORQ.
In
this
system,
the
zao
operates
in
interrupt
mode
2,
and
no
port
is
enabled
during
interrupt
acknowledge
cycles
as
the
interrupting
device
is
automatically
enabled
by
the
combination
of
ZMI
and
ZIORQ
being
active.
Figure
2.2
shows
the
operation
of
JS.
If
the
group
of
system
ports
is
selected
(PORTEN
low)
the
address
is
further
decoded
(AO
-A2)
by
CU
and
DR
giving
S
read
and
5
write
ports,
which
are
used
for
control
and
status
information,
etc.
(as
shown
on
sheet
5).
The
'Z'
data
bus
is
used
directly
by
ROM
and
RAM,
and
is
buffered
to
give
a
'T'
data
bus
when
TDBUSEN
is
active.
This
is
used
mainly
by
I/O
ports
and
is
further
buffered
by
DQ
(write)
and
CQ
(read)
for
use
by
VDU
circuitry.
When
NMIEN
goes
active
(by
writing
to
system
port
0)
an
NMI
will
be
(
generated
during
the
eighth
successive
instruction.
This
is
used
by
the
ROS
monitor
for
single-stepping
through
programs.
The
power
up
circuitry
(C23,
GW
etc)
holds
the
CL
line
of
GU
low,
and
so
holds
RESET
low,
until
the
power
rails
have
stabilised.
Memory
contents
can
be
corrupted
during
reset
in
two
ways:
1.
While
RESET
is
active
no
refreshing
takes
place.
2.
If
RESET
goes
active
during
T3
of
an
M1
cycle,
a
short
MREQ
pulse
can
be
generated
which
may
destroy
data.
Thus,
in
order
to
preserve
memory
contents,
the
RESET
button
signal
is
gated
with
R3
(part
of
the
row
counter
in
video
circuit
which
happens
to
be
a
convenient
frequency)
and
synchronized
with
M1.
This
results
in
RESET
being
active
for
128us,
and
inactive
for
512us,
while
the·
button
is
pressed,
allowing
sufficient
time
to
2.1
•
CD
0
N
t1
~
"
....
Ht
::s
t1
"
~
Tl
en
:r
n
td
T2.
TW
TJ
~
"
16MHZ
~
0
16
MHZ
I
....
<t
MCLC.K
1 ZCLC.K
tJ
•
tJ
C.LC.K
VDUAce/CPUAtC
0
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t1
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•
I I I I I
I I I J I
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t..-
l : I
-,H_n
I I I I I I I
JMA...-~
-
Ml
6T·Q
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I I I
----,--
.....
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11
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r--
1 I I
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GT·
I,
Z.WAIT
: '
~
I-
I I I I
I I I I
Figure
2.1
Basic
M1
Cycle
and
Clocks
-
,-
_,
:v
..
w
Con.ten.Cs
showr.
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Figure
.2.2
Port
Mapping
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480Z Main
PCB
SHEET 2
JV
is
the
memory map
PROM
that
decodes
the
top
address
lines
to
enable
RAM
or
ROM
during
MREQ
cycles.
It
functions
in
the
same way
as
the
port
mapping
PROM.
This
map
can
be
modified
by
signals
PAGE
O,
PAGE
1,
and
ZRD
so
that
the
monitor
program
appears
at
address
0000
after
a
reset
during
memory
read;
this
is
necessary
as
the
zeo
always
looks
at
0000
for
its
first
instruction
after
reset.
During
initialization,
PAGE
0
and
PAGE
1
are
changed
by
writing
to
port
1,
so
that
in
normal
operation
RAM
appears
at
address
0000,
as
required
by
CP/M.
ER
is
a 4 x
4-bit
register
used
for
RAM
mapping
in
a
similar
way
to
JV
except
that
it
can
be
altered
under
software
control
by
writing
to
port
o.
Fiqure
2.3
shows
the
operation
of
ER. The
contents
of
this
register
will
vary
depending
upon
which
type
of
RAM
ICs
are
used
(4116
or
4164).
Lines
MA16
and
MA17
define
the
physical
bank
of
memory,
and
are
decoded
by
JT
to
generate
the
appropriate
RAS
during
MREQ
cycles.
RASO
and
RAS1
go
to
RAM
on
the
main
board,
and
RAS2
and
RAS3
go
to
the
option
PCB.
Lines
MA14
and
MA15
are
used
when
4164
(64K)
RAM
ICs
are
installed,
and
they
select
the
required
16K
block
within
a 64K
bank.
The
ZSO
can
only
directly
address
64K
of
memory
(16
address
lines)
and
so
it
is
the
responsibility
of
the
program
to
change
the
contents
of
ER
to
make
full
use
of
256K memory
(if
this
is
installed).
MR,
KR,
and
HT
are
used
to
multiplex
14
address
lines
into
7
pins
on
the
dynamic
RAM
ICs
(16
lines
into
8+
for
4164's),
and
HT
also
generates
CAS.
Fiqure
2.4
shows
an
MREQ
cycle
involving
RAM;
this
is
started
when
the
ZSO
puts
a
valid
RAM
address
onto
the
bus,
which
is
decoded
by
JV
to
give
RAMEN.
Address
lines
AO
to
A6
and
MA14
are
connected
through
the
multiplexers
to
RAM
(i.e.
the
row
address).
When
MREQ
goes
active,
JT
decodes
the
top
two
address
lines
and
generates
a
RAS
on
the
appropriate
bank.
At
the
start
of
the
next
clock
cycle
the
multiplexers
are
switched
to
connect
A7
to
A13
and
MA15
to
the
RAM
(column
address)
and
RAMEN
is
connected
to
CAS
delay
circuit
(R44/C20).
After
about
40us
(to
allow
address
lines
to
settle)
a
CASO
and
CAS1
go
active;
both
signals
are
identical
and
CAS
1
goes
to
the
option
PCB.
The
cycle
ends
when
MREQ
goes
inactive.
During
refresh,
JV
is
disabled
and
RAMEN
is
not
generated;
this
inhibits
CAS.
ER
is
also
disabled
allowing
JT
to
generate
RAS
on
all
banks
of
RAM
simultaneously.
As
the
zao
only
supplies
7
address
lines
during
refresh,
one
extra
line
is
needed
to
allow
4164
ICs
to
be
used.
This
is
derived
from
the
VDU
line
count
using
L1
which
changes
approximately
every
1.s
ms.
L1
is
synchronized
with
ZRFSH
to
give
SRFSHB
which
is
gated
through
HT
during
refresh
cycles;
this
allows
each
half
of
the
4164's
to
be
refreshed
within
the
2ms
limit.
The
two
latches
GT
and
GV
are
included
to
overcome
a
timing
restriction
of
dynamic
RAM
known
as
RAS
precharge~
this
is
the
minimum
time
that
RAS.
must
be
inactive
between
memory
accesses.
This
is
at
its
limit
between
M1
and
refresh
cycles
where
ZMREQ
goes
inactive
slightly
after
the
rising
edge
of
2.4
(
(
( .
I (
480Z Main
PCB
T3
clock,
and
active
again
on
falling
edge.
GV
terminates
RAS
(by
MRINH
to
JT)
and
CAS
(by
disabling
MREQ1)
on
the
rising
edge
of
T3
clock,
so
overcoming
any
delay
in
ZMREQ
going
high.
2.5
IV
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Figure
2.3
RAM
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I I I I I
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Fiqure
2.4
RAM
Access
Cycle
,.
(J)
0
N
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::s
~
0
m
480Z
Main
PCB
SHEET
3
This
describes
the
regulated
DC
power
entry
to
the
board:
+9V
is
developed
onboard
from
+12V,
as
is
-sv
from
-12V,
both
being
low
current
requirements.
There
are
two
banks
of
RAM
on
the
main
PCB
and
a
further
two
on
the
option
PCB.
Each
bank
can
contain
either
4116
res
(16K)
or
4164
ICs
(64K),
and
link
pads
are
provided
to
cater
for
the
different
pin
requirements.
A 64K
system
may
consist
of
4
banks
of
4116
or
1
bank
of
4164,
and
memory may
be
expanded
up
to
256K.
Different
firmware
and
mapping
PROMs
are
available
to
suit
the
different
options.
Four
ROM
sockets
are
provided,
enabled
by
ROMOEN
through
ROM3EN
from
the
mapping
PROM,
and
most
types
of
ROM
or
EPROM
can
be
accommodated
by
altering
the
link
pad.
BASIC
in
ROM
is
available
as
an
option
with
its
associated
firmware
and
mapping
PROM.
A
similar
range
of
ROM/EPROMs
can
be
accommodated
in
the
character
generator
position
making
a
variety
of
character
fonts
available
to
the
video
circuitry.
SHEET
4
The
video
circuitry
is
dual
mode,
i.e.
40
or
SO
characters
wide
by
24
lines.
It
is
selectable
by
software
(using
write
port
2).
For
clarity,
SO-character
mode
will
be
dealt
with
first.
SO-Character
Mode
The
16MHz
oscillator
is
used
as
the
dot
clock
for
video
output
and
is
divided
into
character
cells
by
JP,
which
also
outputs
the
4MHz
system
clock.
This
counter
is
preset
to
8
and
then
incremented
to
15,
whereupon
EOC
(end
of
character)
goes
active,
and
8
is
reloaded
on
the
next
clock
pulse.
EOC
occurs
every
SOOns
and
clocks
IP
to
produce
a
character
count
of
O
to
127,
although
only
0
to
79
represent
valid
addresses.
This
count
takes
64ns,
i.e.
one
line
scan
time
for
a
VDU
and
is
fed
to
PROM
GR
which
'maps
out'
the
line
waveform
(as
.shown
in
Figure
2.5).
To
restrict
the
number
of
lines
of
this
PROM,
CO
is
not
used,
and
C6
is
routed
via
HP
i.e.
the
PROM
receives
even
addresses
0
to
126.
This
PROM
outputs
LBLNK
to
give
a
blank
area
on
both
sides
of
the
screen,
and
line
sync
pulses
•.
The
LCLK1
output
clocks
the
row
counter
HR,
giving
line
slice
counts
0
to
9.
These
are
fed
to
the
character
generator
IC
to
select
the
appropriate
character
slice.
R3
is
a
convenient
waveform
(active
128
us,
inactive
512
us)
for
use
in
the
reset
circuitry
(sheet
1).
The
falling
edge
of
R3
clocks
IQ
giving
line
counts
Oto
31,
of
which
0
to
23
represent
valid
data
addesses.
The
field
waveform
is
'mapped
out
'
by
PROM
HQ
in
the
same
way
as
the
line
waveform.
Output
FBLNK1
blanks
scan
lines
between
text
lines
by
2.8
(. . )
'
f
\ {
480Z Main
PCB
inhibiting
LOAD
to
the
shift
register,
and
FSYNC1
is
the
separate
field
sync
output.
FS
is
fed
back
to
GR
which,
in
combination
with
LSYNC1,
generates
mixed
sync
(MSYNC)
and
is
used
to
produce
the
composite
video
output.
Field
RESET
(FR)
is
used
to
'trim'
the
field
time
to
the
required
20ms (SOHz)
by
resetting
and
row
counters
during
line
count
31.
If
these
were
not
reset,
the
field
time
would
be:
32 (max
line
count)
x
10
(max
row
count)
x
64us
Cline
time)
-
20.48ms
which
might
cause
instability.
During
normal
screen
refreshing,
the
7
character-count
bits
(CO-C6)
and
5
line-count
bits
(LO
-
L4)
define
the
character
position
in
RAM
with
some
redundant
addresses.
The
2K
RAM
used,
although
being
of
adequate
capacity
for
the
display,
only
uses
11
address
lines
(with
no
redundancy)
and
is
not
compatible
with
the
80 x 24
screen
format
-
in
other
words
the
RAM
is
'too
square'
-
and
so
some
juggling
of
address
space
is
needed.
In
40-character
mode no
problem
arises,
but
in
BO-character
mode
addresses
greater
than
63
are
mapped down
to
the
redundant
lines
(24
to
31)
in
three
groups
because
CC6E
is
active
(column
count
C6
via
GP
and
HP)
and
switches
the
multiplexer,
MP.
This
is
illustrated
in
fiqure
2.6.
Access
to
the
video
RAM
is
divided
into
two
equal
time
slots
by
the
2
MHz
signal
VDUACC/CPUACC
so
that
the
CPU
can
write
to
the
screen
without
any
timing
restrictions
and
without
disrupting
screen
refresh.
During
screen
refresh
(VDUACC
high)
the
character
and
line
counts
are
selected
by
the
multiplexers
KP,
GQ,
and
GP,
and
are
latched
into
LP,
MP,
and
KP
on
the
falling
edge
of
4
MHz
(i.e.
half-way
through
VDUACC).
When
EOC
is
active,
the
data
addressed
is
latched
into
MQ
on
the
rising
edge
of
16
MHz
(i.e.
half-way
through
EOC)
and
is
presented
to
the
character
generator.
At
the
same
time,
the
outputs
SRO
to
SR7
from
the
previous
character
are
loaded
into
the
shift
register
JQ,
provided
that
valid
data
exists
(i.e.
LBLNK
and
FBLNK
are
inactive).
This
data
represents
the
dot
format
of
the
selected
character
slice,
and
is
shifted
out
at
16MHz
as
VIDEO.
Figure
2.7
shows
the
timing.
2.9
4BOZ
Main
PCB
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2.12
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