Rohm LAPIS Semiconductor ML22620 User manual

FEDL22620-01
Issue date: Apr 24, 2020
ML22620
4-Channel Mixing Speech Synthesis LSI
■Overview
ML22620 is a 4-channel mixing speech synthesis LSI with a serial flash memory interface for sound data. It is equipped
with a clock synchronous serial interface.
It adopts a HQ-ADPCM*1, 16-bit D/A converter, and low-pass filter for high sound quality, and incorporates a 1.0W mono
speaker amplifier for driving speakers directly. It is also equipped with a function to detect failure.
The functions necessary for sound output are integrated into a single chip, so that sound functions can be realized simply by
adding this LSI.
● Memory capacity and maximum sound production time (HQ-ADPCM*1 algorithm, registered phrase 1024)
Product Name
Flash memory capacity
Maximum sound production time (sec)
fs=8.0kHz
fs=16.0kHz
fs=32.0kHz
ML22620
128Mbits
(Serial Flash Memory)
5240 2620 1310
Application Circuit
Host
MCU 16bit
DAC
Filter
Volume
MIX
SPI
Analog Signal
MIX
Decode
FLASH
MEMORY
Speaker
AMP
*1 HQ-ADPCM is "Ky's" high-quality audio compression technique.
"Ky's" is a registered trademark of Kyushu Institute of Technology, a
national university corporation.

FEDL22620-01
ML22620
■Feature
● Sound data
Speech synthesis algorithm: The algorithm can be specified for each phrase.
HQ-ADPCM/4bit ADPCM2/8bit non-linear PCM /
8bit Straight PCM/16bit Straight PCM
Sampling frequency: The sampling frequency can be specified for each phrase.
10.7/21.3kHz,
6.4/12.8/25.6kHz,
8.0/16.0/32.0kHz,
11.025/22.05/44.1kHz,
12.0/24.0/48.0kHz
Maximum number of phrases: 4096 Phrases
● Edit ROM function
● Playback function
Repeat function: LOOP command
Mixing-function: Up to 4-channel
Volume adjustment function: CVOL command 128 levels (including off-state)
AVOL command 16 levels (including off-state)
● Low-pass filter
● 16-bit D/A converter
● Speaker amplifier: Class AB/D 1. 0W 8Ω (SPVDD =5V, Ta=25 OC)
● Line amplifier output: 10kΩ driving (Exclusive operation from speaker amplifier output)
● External analog sound input (at the time Class AB speaker amplifier choice, with analog mixing function)
● MCU command interface: Clock Synchronous Serial Interface
● Failure detection function
Speaker short detection: Speaker pin ground fault detection, speaker pin short detection
Speaker disconnection detection
Thermal detection
Clock error detection
Flash memory error detection
● Clock backup function
● Master clock frequency: 4.096MHz, 4.000MHz
● Power-supply voltage 2.7V to 5.5V
●Operating temperature range: -40 OCto +85 OC*1
● Package: 32-pin TQFP (7mm x 7mm, 0.8mm pitch)
● Ordered Part Name: ML22620TB (32-pin TQFP)
*1 The operating time of the speaker amplifier may be limited depending on the average ambient temperature (Ta) used.
2/115

FEDL22620-01
ML22620
■Pin Configuration (TOP VIEW)
●ML22620TB
1
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
16
15
14
13
12
11
10
25
26
27
28
29
30
31
(N.C.)
SPP
SPM
RESETB
TEST0
STATUS1
STA
TUS2
CBUSYB
SPGND
SP
VDD
AIN
SG
V
DDL
D
VDD
DGND
XT
(TOP VIEW)
TQFP32
9
XTB
(N.C.)
IO
VDD
EROFF
ERSO
ERSI
ERSCK
ERCSB
32
(N.C.) Unused pin
DGND
(N.C.)
TEST1
CSB SCK
SI
SO
(N.C.)
3/115

FEDL22620-01
ML22620
■Pin Description
Pin Symbol I/O Attribute Description
Initial
value
*1
1,18
DGND
G
-
Digital ground pin.
—
3 TEST1 O -
Output pin for testing.
Leave open.
Hi-Z
4 CSB I Negative
Synchronous serial interface chip select pin.
The SCK and SI inputs are accepted only when this pin is at the "L"
level.
H
5
SCK
I
-
Synchronous serial interface clock input pin.
L
6 SI I -
Synchronous serial interface data input pin.
Data is fetched in synchronization with SCK.
L
7 SO O -
Synchronous serial interface data output pin.
When the CSB pin is at an "L" level, data is output in synchronization
with SCK.
When the CSB pin is at an "H" level, this pin enters a high-impedance
state.
Hi-Z
9 ERCSB O Negative
Serial flash memory interface chip select output pin.
Output the "H" level during non-access and the "L" level during
access.
Setting the EROFF pin to "L" enables output.
H
10 ERSCK O -
Serial flash memory interface serial clock output pin.
Setting the EROFF pin to "L" enables output.
L
11 ERSI I -
Serial flash memory interface serial data input pin.
Setting the EROFF pin to "L" enables input.
A pull-down resistor is internally connected.
L
12 ERSO O -
Serial flash memory interface serial data output pin.
Setting the EROFF pin to "L" enables output.
L
13 EROFF I Positive
Pin to disable the serial flash memory interface.
When this bit is set to "L", the serial flash memory interface pin is
enabled. A pull-down resistor is internally connected.
Set this pin to "L" during playback operation using serial flash
memory.
When this pin set to "H", the serial flash memory interface is in a
condition of high-impedance.
Set this bit to "H" for onboard rewriting.
L
*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.
4/115

FEDL22620-01
ML22620
Pin Symbol I/O Attribute Description
Initial
value
*1
14 IOVDD P -
Serial flash memory interface power supply pin.
Connect a bypass capacitor between this pin and the DGND pin.
—
16 XTB O Negative
Crystal or ceramic resonator connection pin.
When an external clock is used, leave it open and capacitor is not
required when a crystal or ceramic resonator is connected.
When using a resonator, connect it as close as possible.
Leave it open when not in use.
H
17 XT I Positive
Crystal or ceramic resonator connection pin.
A feedback resistor of about 1MΩ is built in between the XT pin and
the XTB pin.
To use an external clock, input from this pin. Delete the capacitor
when a crystal or ceramic resonator is connected.
When using a resonator, connect it as close as possible.
Leave it open when not in use.
L
19 DVDD P -
Digital power supply pin.
Connect a bypass capacitor between this pin and the DGND pin.
—
20 VDDLO -
2.5V regulator output pin.
Used as internal power supply.
Connect a capacitor between this pin and DGND pin as close as
possible.
L
21 SG O -
Reference voltage output pin for the built-in speaker amplifier.
Connect a capacitor between this pin and SPGND pin.
L
22 AIN I -
Speaker amplifier analog signal input pin.
Initially, input is disabled.
L
23 SPVDD P -
Power supply pin for speaker amplifier.
Connect a bypass capacitor between this pin and the SPGND pin.
—
24
SPGND
G
-
Speaker amplifier ground pin.
—
26 SPP O -
Positive output pin of the speaker amplifier.
Line amplifier outputs are also available with AMODE command.
L
27
SPM
O
-
Negative output pin of the speaker amplifier.
Hi-Z
*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.
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FEDL22620-01
ML22620
Pin Symbol I/O Attribute Description
Initial
value
*1
28 RESETB I Negative
Reset input pin.
The LSI is initialized by the "L" level input. After a reset is input, all the
circuits stop operating and enter the power-down state.
At power-on, input an
"L" level to this pin. After the power supply
voltage stabilizes, set this pin to an "H" level.
A pull-up resistor is internally connected.
(*2)
29 TEST0 I Positive
Input pin for testing.
A pull-down resistor is internally connected.
Fix to the DGND.
L
30 STATUS1 O -
Status/error output pin 1.
Execute OUTSTAT command to select BUSYB*3 and NCR*3 in each
channel, or errors.
The initial value is BUSYB
*3
of channel 0, and output data is "H" level.
H
31 STATUS2 O -
Status/error output pin 2.
Execute OUTSTAT command to select BUSYB*3 and NCR*3 in each
channel, or errors.
The initial value is BUSYB
*3
of channel 0, and output data is "H" level.
H
32 CBUSYB O Negative
Command processing status signal output pin.
An "L" level is output during command processing.
Be sure to input a command with this pin at an "H" level.
(*2)
2,8,
15,25
N.C. - -
Unused pin.
Leave open.
Hi-Z
*1 Initial value at reset input and power-down. The pin whose IO is "I" indicates a fixed level from outside.
*2 "L" at reset, "H" at power-down
*3 For NCR, BUSYB, refer to the description of "RDSTAT command".
■Termination of Unused Pins
This section explains how to terminate unused pins.
Symbol
Recommended pin termination
EROFF
Connect to the DGND.
XT
Leave open.
XTB
AIN
Connect to the SPGND.
TEST0
Connect to the DGND.
N.C.
Leave open.
SO
SPM
STATUS1
STATUS2
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FEDL22620-01
ML22620
■I/O Equivalent Circuit
Classifi
cation
Circuit Overview
A
Attribute: Input
Power: DVDD
Function: CMOS inputs with pull-down
Applicable pin: TEST0
B
Attribute: Input
Power: IOVDD
Function: CMOS inputs with pull-down
Applicable pin: EROFF
C
Attribute: Input
Power: DVDD
Function: CMOS inputs with pull-up
Applicable pin: RESETB
D
Attribute: Input
Power: DVDD
Function: CMOS inputs
Applicable pins: SI, SCK, CSB
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FEDL22620-01
ML22620
Classifi
cation
Circuit Overview
F
Attribute: Input/output
Power: DVDD
Function: CMOS inputs
Function: CMOS outputs
Applicable pins: STATUS1, STATUS2, CBUSYB,SO
G
Attribute: Input/output
Power: IOVDD
Function: CMOS inputs
Function: CMOS outputs
Applicable pin: ERCSB, ERSCK, ERSO
H
Attribute: Input/output
Power: IOVDD
Function: CMOS inputs with pull-down
Function: CMOS outputs
Applicable pin: ERSI
I
XT
XTB
Attribute: Oscillator circuit
Power: DVDD
Function: 4.096M, 4.000MHz oscillation
Applicable pins: XT, XTB
8/115

FEDL22620-01
ML22620
Classifi
cation
Circuit Overview
J
Attribute: Analog
Power: SPVDD
Function: Sound output
Applicable pins: SPP, SPM
L
Attribute: Analog
Power: SPVDD
Function: Sound input
Applicable pins: AIN
9/115

FEDL22620-01
ML22620
■Electrical characteristics
●Absolute maximum rating DGND=SPGND=0V, Ta=25°C
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
DV
DD
IOVDD
SPVDD
— -0.3 to +6.0 V
Input voltage 1
VIN1
—
-0.3 to DVDD+0.3
V
Input voltage 2
VIN2
—
-0.3 to IOVDD+0.3
V
Allowable loss PD
When the LSI is mounted on
JEDEC 4-layer board.
SPVDD = 5V
1000 mW
Output short-circuit current IOS Applies to pins other than
SPM, SPP and VDDL pins.
10 mA
Applies to SPM and SPP pins.
500
mA
Applies to the VDDL pin.
50
mA
Storage temperature
TSTG
—
-55 to +150
°C
●Recommended operating conditions DGND=SPGND=0V
Parameter
Symbol
Condition
Range
Unit
DVDD,
IOVDD,
SPVDD
*1
,Power-supply voltage
DVDD
IOVDD
SPVDD
— 2.7 to 3.6 / 3.3 to 5.5 V
Operating temperature
Top
—
-40 to +85
°C
Master clock frequency fOSC —
Min.
Typ.
Max.
MHz
Typ
-5%
4.096
Typ
+5%
4.000
*1 SPVDD≥DVDD
10/115

FEDL22620-01
ML22620
●DC characteristics SPVDD≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +85°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Applicable pin
Min.
Typ.*1
Max.
Unit
"H" input voltage 1 VIH1 — CSB/SCK/SI/
XT/RESETB/TEST0
0.8×DVDD — DVDD V
"H" input voltage 2
VIH2
—
ERSI/EROFF
0.8×IOVDD
—
IOVDD
V
"L" input voltage 1 VIL1 — CSB/SCK/SI/
XT/RESETB/TEST0
0 — 0.2×DVDD V
"L" input voltage 2
VIL2
—
EROFF/ERSI
0
—
0.2×IOVDD
V
"H" output voltage 1
VOH1
IOH = -50µA
XTB
DVDD-0.4
—
—
V
"H" output voltage 2 VOH2 IOH = -1mA SO/
CBUSYB/STATUS1/
STATUS2
DVDD-0.4 — — V
"H" output voltage 3
VOH3
IOH = -1mA
ERSO
IOVDD-0.4
—
—
V
"L" output voltage 1
VOL1
IOL = 50µA
XTB
—
—
0.4
V
"L" output voltage 2 VOL2 IOL = 2mA SO/
CBUSYB/STATUS1/
STATUS2
— — 0.4 V
"L" output voltage 3 VOL3 IOL = 2mA ERCSB/ERSCK/
ERSO
— — 0.4 V
Output leakage
current 1
IOOH1 VOH=DVDD
(in high-impedance state)
SO — — 10 µA
IOOL1
VOL=DGND
(in high-impedance state)
–10 — — µA
Output leakage
current 2
IOOH2 VOH=IOVDD
(in high-impedance state)
ERCSB/ERSCK/
ERSO
— — 10 µA
IOOL2 VOL=DGND
(in high-impedance state)
–10 — — µA
"H" input current 1
IIH1
VIH = DVDD
XT
0.8
5.0
20
µA
"H" input current 2 IIH2 VIH = DVDD RESETB/
CSB/SCK/SI
— — 10 µA
"H" input current 3
IIH3
VIH = DVDD
TEST0
20
500
1000
µA
"H" input current 4
IIH4
VIH = IOVDD
ERCSB/ERSCK
—
—
10
µA
"H" input current 5
IIH5
VIH = IOVDD
EROFF
20
500
1000
µA
"H" input current 6
IIH6
VIH = IOVDD
ERSI
2
100
400
µA
"L" input current 1
IIL1
VIL = DGND
XT
–20
–5.0
–0.8
µA
"L" input current 2 IIL2 VIL = DGND CSB/SCK/SI/
EROFF/
TEST0
–10 — — µA
"L" input current 3
IIL3
VIL = DGND
RESETB
–400
–100
–2
µA
During playback
Current
consumption IDDO
f
OSC
=4.096MHz
Fs=48kHz, f=1kHz,
During HQADPCM
playback
SPP/SPM No output
load
— — — 55*2 mA
Power-down
Current
consumption
IDDS
Ta=-40 to +55°C
—
—
1
10.0*2
µA
Ta=-40 to +85°C — — 1 30.0*2 µA
*1 Typ. : DVDD=SPVDD=IOVDD=5.0V,DGND=SPGND=0 V,Ta=25°C
*2 Total values of the DVDD pin, SPVDD pin, and IOVDD pin
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FEDL22620-01
ML22620
●Analog Part Characteristics
SPVDD≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +85°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
RC4MHz clock frequency Frc Ta=-40 to +70°C 3.89 4.096 4.31 MHz
AIN pin input resistance
RAIN
Input gain 0dB
10
20
30
kΩ
AIN pin input voltage range
VAIN
—
—
—
SPVDD×2/3
Vp-p
Line amplifier output
resistance1*1 RLA1
SPV
DD
= 3.3 to 5.5V
When 1/2SPVDD ± 1 mA is
applied
— — 100 Ω
Line amplifier output
resistance2*1 RLA2 SPVDD = 2.7 to 3.6V
When 1/2SPVDD ± 1 mA is
applied
— — 300 Ω
Line amplifier
output-load-resistance
*1
RLA For SPGND 10 — — kΩ
Line amplifier Out put Voltage
Range
*1
VAO No output load SPVDD /6 — SPVDD×5/6 V
SG pin output voltage VSG — 0.95x
SPVDD /2
SPVDD /2 1.05x
SPVDD /2
V
SG pin output resistance
RSG
—
57
96
135
kΩ
SPP/SPM pins Output-Load
Resistance
RLSP1 — 6 8 — Ω
To the SPP and SPM pins
Short circuit detection
ROCDAB Class AB speaker amplifier
4.5V≤SPVDD≤5.5V
0.1 — 6 Ω
ROCDD
Class D speaker amplifier
4.5V≤SPVDD≤5.5V
0.1 — 3 Ω
Speaker amplifier output power
1 PSPO1 SPVDD =5.0V,
f=1kHz RSPO=8Ω,
THD=10%
0.8 1 — W
Speaker amplifier output power
2 PSPO2
SPV
DD
=3.0V,
f=1kHz RSPO=8Ω,
THD=10%
0.1 0.3 — W
During no-signal SPM-SPP
Output offset voltage
VOF AVOL=0dB
8 Ω load
-50 — 50 mV
*1 Applies to the SPP when outputting LINE.
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FEDL22620-01
ML22620
●AC characteristic SPVDD≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +85°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Master clock duty cycle
fduty
—
40
50
60
%
RESETB input pulse width
tRST
—
10
—
—
μs
Reset noise rejection pulse width
tNRST
RESETB pin
—
—
0.1
μs
Command input interval time tINTC
f
OSC
= 4.096MHz
After input the first command at
two-times command input mode
0 — — μs
Command input enable time tcm fOSC = 4.096MHz
During continuous playback
at SLOOP input
— — 10 ms
At PUP command input
CBUSYB "L" level output time
tPUP 4.096MHz external clock input — — 8 ms
At AMODE command input
CBUSYB "L" level output time tPUPA1
4.096MHz external clock input
POP="L"
AEN0="L"→"H"
AEN1 = "L"
AVOL =
-4dB is selected
35 37 39 ms
At AMODE command input
CBUSYB "L" level output time tPUPA2 4.096MHz external clock input
DAMP="L",POP="H"
AEN1="L"→"H"
72 74 76 ms
At AMODE command input
CBUSYB "L" level output time tPUPA3 4.096MHz external clock input
DAMP="L",POP="L"
AEN1="L"→"H"
32 34 36 ms
At PDWN command input
CBUSYB "L" level output time
tPD fOSC = 4.096MHz — — 10 μs
At AMODE command input
CBUSYB "L" level output time tPDA1 4.096MHz external clock input
POP="L"
AEN1="L",AEN0="H"→"L"
106 108 110 ms
At AMODE command input
CBUSYB "L" level output time tPDA2
4.096MHz external clock input
DAMP="L",POP="H"
AEN1="H"→"L"
143 145 147 ms
At AMODE command input
CBUSYB "L" level output time tPDA3 4.096MHz external clock input
DAMP="L",POP= "L"
AEN1="H"→"L"
103 105 107 ms
CBUSYB "L" level output time 1*1
tCB1
fOSC= 4.096MHz
—
—
10
μs
CBUSYB "L" level output time 2*2
tCB2
fOSC = 4.096MHz
—
—
3
ms
CBUSYB "L" level output time 3*3 tCB3
FAD="L" at fOSC = 4.096MHz
—
—
200
μs
FAD="H" at fOSC = 4.096MHz
—
—
10
ms
*1 Applies when inputting commands except the timings after PUP, PDWN, PLAY, or START command is input.
*2 Applies when inputting PLAY, START, MUON command.
*3 Applies when inputting STOP command.
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FEDL22620-01
ML22620
●AC Characteristics (Clock Synchronous Serial Interface)
SPVDD ≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
CSB input enable time from EROFF falling edge
tEEROFF
—
1000
—
—
ns
CSB hold time from EROFF rising edge
tEROFFH
—
1000
—
—
ns
SCK setup time from CSB falling edge
tSCKS
—
100
—
—
ns
SCK input enable time from CSB falling edge
tESCK
—
100
—
—
ns
SCK hold time from CSB rising edge
tCSH
—
100
—
—
ns
Data floating time from CSB rising edge
tDOZ
RL=3KΩ
—
—
100
ns
Data setup time from SCK
tDIS
—
50
—
—
ns
Data hold time from SCK
tDIH
—
50
—
—
ns
Data output delay time from SCK
tDOD
—
—
—
90
ns
SCK "H" level pulse width
tSCKH
—
100
—
—
ns
SCK "L" level pulse width
tSCKL
—
100
—
—
ns
CBUSYB output delay time from SCK
tDBSY
—
—
—
90
ns
<When rewriting the flash memory using the clock synchronous serial interface>
SPVDD ≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
CSB input enable time from EROFF falling edge
tEEROFF
—
1000
—
—
ns
CSB hold time from EROFF rising edge
tEROFFH
—
1000
—
—
ns
SCK setup time from CSB falling edge
tSCKS
—
125
—
—
ns
SCK input enable time from CSB falling edge
tESCK
—
125
—
—
ns
SCK hold time from CSB rising edge
tCSH
—
125
—
—
ns
Data floating time from CSB rising edge
tDOZ
RL=3KΩ
—
—
125
ns
Data setup time from SCK
tDIS
—
50
—
—
ns
Data hold time from SCK
tDIH
—
50
—
—
ns
Data output delay time from SCK
tDOD
—
—
—
110
ns
SCK "H" level pulse width
tSCKH
—
125
—
—
ns
SCK "L" level pulse width
tSCKL
—
125
—
—
ns
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FEDL22620-01
ML22620
●AC Characteristics (Flash Memory Interface)
SPVDD ≥DVDD=IOVDD=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +85°C, Load capacitance of output pin =15pF(max.)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ERSCK enable time from ERCSB falling edge
tECSS
—
50
—
—
ns
ERSCK hold time from ERCSB rising edge tECSH — 50 — — ns
Data setup time from ERSCK rising edge
tEDIS
—
10
—
—
ns
Data hold time from ERSCK rising edge tEDIH — 10 — — ns
Data delay time from ERSCK falling edge
tEDOD
—
—
—
5
ns
ERSCK frequency tESCKF — 1.228 16.384 17.20 MHz
ERSCK "H" level pulse width
tESCKH
—
26
—
—
ns
ERSCK "L" level pulse width tESCKL — 26 — — ns
ERCSB/ERSC/ERSO delay time from EROFF rising
edge
tEFLH — — — 1 ms
ERCSB/ERSC/ERSO delay time from EROFF falling
edge
tEFHL — — — 1 ms
15/115

FEDL22620-01
ML22620
■Block diagram
The block diagram is shown below.
Address
Controller
Serial Flash Memory
Interface
Timing
Controller PLL
OSC4.096MHz
or 4.000MHz
PCM Synthesizer
XT
XTB
Digital Mixing
LPF
DV
DD
DGND
V
DDL
RESETB
TEST0
RC4.096MHz
Command
Analyzer
ERCSB
ERSCK
ERSI
ERSO
EROFF
IOVDD
CBUSYB
STATUS
1
STATUS2
MCU
Interface
CSB
SCK
SI
SO
16bit DAC
LINE Amplifier
Analog Mixing
AIN
SPVDD
SPGND
SPP
SPM
SG
ΔΣ
AB Class
Amplifier
PWM
D Class
Amplifier
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FEDL22620-01
ML22620
■Function description
●Clock Synchronous Serial Interface
The CSB, SCK, SI, and SO pins are used to input various command data and to read the status.
For command and data inputting, after "L" level is input to the CSB pin, data is input to the SI pin in MSB first in
synchronization with the input clock signal of the SCK pin. The SI pin data is loaded into the LSI in synchronization with the
SCK pin clock, and the command data is determined by the SCK pin clock of the eighth pulse.
When reading, after "L" level is input to the CSB pin, it is output from the SO pin in synchronization with the input clock
signal of the SCK pin.
The selection of the rising or falling edge of the SCK pin clock depends on the state of the SCK pin at the falling edge of the
CSB pin.
When the SCK pin is "H" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the rising edge of the
SCK pin clock, and the status signal is output from the SO pin on the falling edge of the SCK pin clock.
When the SCK pin is "L" at the falling edge of the CSB pin, the SI pin data is loaded into the LSI on the falling edge of the
SCK pin clock, and the status signal is output from the SO pin on the rising edge of the SCK pin clock.
When the CSB pin is fixed to "L" level, the SI pin data is loaded into the LSI on the rising edge of the SCK pin clock, and the
status signal is output from the SO pin at the falling edge of the SCK pin clock.
However, if unexpected pulses are input to the SCK pin due to noise, etc., the count of the number of SCK pin clocks may be
shifted, and normal command input may not be performed.
The serial interface can be returned to the initial state by setting the CSB pin to "H" level.
When the CSB pin is "H" level, the SO pin becomes a high impedance state.
CSB
SCK
SI
Command data input timing：SCK rising edge operation
(When the SCK is "H" at the falling edge of the CSB)
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
CSB
SCK
SI
Command data input timing：SCK falling edge operation
(When the SCK is "L" at the falling edge of the CSB)
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
CSB
SCK
Command data output timing：SCK falling edge operation
(When the SCK is "H" at the falling edge of the CSB)
(MSB)
(LSB)
CSB
SCK
Command data output timing：SCK rising edge operation
(When the SCK is "L" at the falling edge of the CSB)
(MSB)
(LSB)
SO
D7
D6
D5
D4
D3
D2
D1
D0
SO
D7
D6
D5
D4
D3
D2
D1
D0
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FEDL22620-01
ML22620
●Volume Settings (Differences Between AVOL and CVOL)
The volume can be set with 3 commands CVOL, AVOL and AMODE.
The CVOL can set the volume of each channel, the AVOL can set the volume after channel mixing, and the AMODE can set
the input gain to the amplifier. By using the fade function with FADE command, the volume can be adjusted stepwise when
the volume is changed with CVOL.
[3:0]
[0]
[1]
[2]
[3]
AIN
SPP
SPM
Channel 0 (CH0)
Channel 1 (CH1)
Channel 2 (CH2)
Channel 3 (CH3)
MIXING
CVOL command
FADE command
GAIN
AMP
Setting AIG of
AMODE command
Setting DAG of
AMODE command
GAIN
AMP
AVOL
command
LPF
DAC
LINE
AMP
Speaker
amplifier
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FEDL22620-01
ML22620
●Speech synthesis algorithm
This LSI contains five algorithm types to match the characteristic of playback sound: 4-bit ADPCM2 algorithm,
HQ-ADPCM algorithm, 8-bit non-linear PCM algorithm, 8-bit straight PCM algorithm, and 16-bit straight PCM algorithm.
Key feature of each algorithm is described in the table below.
Speech synthesis
algorithm
Compression
rate
Feature
4-bit ADPCM2 1/4
LAPIS original 4bit ADPCM algorithm is improved. Better
followability to the waveform improves the sound quality. Suitable for
human voices, animal crying, and natural sounds.
HQ- ADPCM 1/5
4bit ADPCM algorithm is improved. Adopting variable bit length
enables high sound quality and high data compression. Suitable for
sound effects with sharp changes in waveforms or for pulsed
waveforms.
8-bit non-linear PCM 1/2
This algorithm enables playing back a sound with 10-bit equivalent
quality in the center of the waveform. Suitable for low-amplitude
sounds that are easily distorted.
8-bit straight PCM 1/2
This algorithm has excellent followability to the waveform in all
sound areas. Suitable for sound effects with sharp changes in
waveforms or for pulsed waveforms.
16-bit straight PCM 1
This algorithm has excellent followability to the waveform in all
sound areas. Suitable for sound effects with sharp changes in
waveforms or for pulsed waveforms.
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FEDL22620-01
ML22620
●Memory Allocation and Creating Sound Data
The serial flash memory is partitioned into four data areas: sound (i.e., phrase) control area, test area, sound area, and edit
ROM area.
The sound control area manages the sound data in the ROM. It contains data for 4,096 phrases.
The sound area contains actual waveform data.
The edit ROM area contains data for effective use of sound data. For the details, refer to the section of "Edit ROM
Function".
The edit ROM area is not available if the edit ROM is not used.
The ROM data is created using a dedicated tool (Speech LSI Utility).
●Playback time and memory capacity
The playback time depends on the number of phrases, memory capacity, sampling frequency, and playback algorithm. The
relationship is shown below. However, this is the playback time when the edit ROM function is not used.
When the number of phrases is 1024, the sampling frequency is 16kHz, and the HQ-ADPCM algorithm is selected, the
playback time will be approximately 81 seconds.
Configuration
of Serial Flash Memory Data
(4Mbit)
Edit ROM area
Depends on creation of ROM
Test area
0x00000
0x0007F
0x7FFFF
0x00080
Sound area
Sound control area (*)
(The number of phrases can be set
with the dedicated tools.)
0x0207F
0x02080
(*) When the number of phrases is set to 1024
The number of phrases can be set from 1024 to 4096 in 1024 units
using the dedicated tools.
1.024 × (Memory Capacity (kbit)-(0.0625 × Number of Phrases)-0.625)
Sampling frequency (kHz) × bit length
Playback Time = (sec)
1.024 × (4096(kbit)- (0.0625×1024) - 0.625)
16 (kHz) × 3.2 (bit) (average)
Playback Time = ≒81 (sec)
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