Roland MicroComposer MC-4 Operating and maintenance manual

JAN.13,1982 MC-4
MC-4 [SERVICE NOTES
SPECIFICATIONS First Edition
Memory Capacity MC-4A [w/out OM-4]
apst 3900 notes |1 &Kbyte version]
MC-4E[withOM-*]
apx 12000 notes [4« Kbyte version]
"OM^s optforal memory board
with interface tOr MTR-IOO
Output 4channels each channel h^:
CVO [OV-ia.-^ZV. 125 steps,B3.3mV/step]
CV-2 [0 V-1 0.42 V,T 23 steps, 33.3 mW;Stepl
Cat« [off =0V,on^12V]
MPX [QH =0V.on =l2V]
Ut Input cv [OV~1043V]
Cat£ [thfeshoJd +2,5V]
Calibration Knob
Teir(p<i CV Inpyt CV [OV-10.42V3
EdtSrnc Input [thresiiold +2 5V]
Output I0-5V]
Total Tune Knob (+/- loo ctnts]
T«mpo Knob [-50% to +100%)
ShiHMip 7: CVl +GATE a: GATE REWRITE 9TUNE
4;CV2 5:MPX
TCVI 3' STEP TIME 3: GATE TIME
0: Available Mpfriory {%:
Dimensions 47^x343x1 24 mm
Weight 61kg[MC-4Al,6Jks(MC^B)
Power 30W
Hs^t$inkH2&{04BK025l
Sida panel HSSB [0S1 H03S'2) Psne!K74C i07aHO74Ci
Key switch KEH10903
(13129714)
Key iopKT3-1
blLie, ivory !12479705)
Key :op KT3 22479704)
lOKevassv KEH4A006 (13129716) ^
Switch SLE722-18P (131391321 "
TCS0 2EO'1-'3 {13429608)
HU-102-]-^ !1 34492201 FCM-7CI4Q034 AU/L {13439173)
COMTROL BOARD 0PH141 t149Hl4T)
JACK eOARD 0PH142 !149H142)
&idB panal H37B (0S1H037-2)
Covar HB2B {O65H0S2B1
Jack HSJ0779-01^1Cl (13449406MI
^NECTOR BOARD 0PH144 [149H144)
iWER SUPPLY PSHS6 (100V) (146H066}
RAM BOARD 0PH143 {149H143)
Pot EVHLWAD25B14 (13219312}
^Switch SUE 623-TSP I13T39135)
Pot VR1CIRS20A15 (13219601)
Knob K-34 Type (M) (2247540600)
CPU BOARD OPH 140 (149H140)
CHASSIS Hi 12 (061 HI 12)
PAMEL OPENABLE SCREWS
SELF TAPPING
3n6mrr>
BINDING ai Br
SwfTChSLE522'18P {13139136)
ISRoland Printed in Japan 1-2

MC-4 JAN,13,1982
MTR-100 Connector Board
POWER
Cassette Tape-
Transport
MT-2
MC-4
CPU
1G31
BUFFER
IC13
IC15
ADDRESS BUS
DATA BUS
ou
10K Byte ROM
IC32-IC36
nil
16K Byte RAM
IC1-IC3
CONTROL BUS -^' _jji
:t_
CLOCK
OSC
IL
TIMER
IC30
ITC
CPU BOARD
1
[
1^^,otg^? Pq":P?_.
ELCK
READ
SEL 4^av
r" BUFFER
IC12 A
32K Byte RAM
ICMC8
IC16-tC23
CONNECTO RBOARD
nBUFFER
fC27 BBUFFER
JC12 C
1iC12 CM
Digital Cassette Interface
UT
I/O PORT (8 bit X6)
IC29, ICBS
Audio
Cassette
Tape, Sync
Interface
D/A
S/H
LATCHES
A-CMT
SYNC
CV
GATE
MPX
1^
iI
i
IDISPLAY
LED
RAM BOARD {OM-41
"n
KEYSW
MATRIX
J1
I
I
SIGNALS THROUGH
RAM BOARD CONNECTORS
RS0^RS2 :ADDRESSES A0-A2
Select one of MT-2 internal 8
registers.
DO-D? :PARALLEL BUS
Transfers 8bit data from /to MT-2,
ELCK ;SYNC CLOCK derived from CPU
CLOCK
Controls MT-2 MT-2 operations.
READ :Signals MT-2 direction of data
flow on the data buss.
SE L:Indicates that CPU nam^s MT 2.
Gates Buffers A, Band C.
-I-5V :Informs Intarface that IVtT-2 power
is ON,
JACK BOARD CONTROL BOARD

MC-4
JAN .13,1982
{Top Vitfw)
^PD7S0 C/D-(
8BIT MICROPROCESSOR
1}
CPU AKD
5T^5TEH
CONTROL
SIGNALS
ADDRESS BUS
A14, A15 Used to select the follt>-wing memory blocks through
respeotive Address Decoders.
Address Decoder
IC60'
IClOj IC12
1024, 1025
Memory
TO'52-1036 ROKq on CPU Board
IC1-IC8, RJU^s on CKf Board
IC1-IC8, IG16-I023 SJffls on HAM Board
A0^A7 Used to select 1/0 DeYices through Port Addresa Decoder
1C57 on CPU Board. (See I/O MAP right)
1029\10] D/A, MODE LED Display, DIH OUT, A/D IN, Clock Out,
^-^ CYCLE 3W IN
IQ5o[40) Timing Signals generation, -Total Time measurement
IC58r77ri Key Scanning, Dot Display, iXIetronome, Mode sw IN,
i^ DIN IN
Tiie numbers |4ol ,[60| and [to] above, also shown in the^CHj
circuit diagWn, We abbreviated J/0 divice numbers ±n hex,
to be represented on address bus, that is xx4x, iC xbx
a:id XX7X. If bits 0111 (7) appear on A7-A4, IG57 selects
IC29. Then bits on Al-AO will cause one ot the following in
IC29 to be selected; 00-Port A, 01-Port B, 10-Port and 11^
Control Word Register.
Similarly, if 0100 (4) are on A7-A4, IG57 selects IG30, and
00 on Al-AO Counter 0.
^PD8255C
PROGRAMMABLE PERIPHERAL INTERFACE
2A Programmable WO Pins
BASIC OPERATION
APDS253C-5
PROGRAMMABLE IMTEflVAL TIMER
3Ind«p«nden1 16-Blt Counters
SND d
pc(**Qi
PCo-{i±
PCi**[i5
pci-*!
PCs*- EI
PBi**[i|
PB2'
*PAl
:l]«PB.s
1/0 mr
40 IC50
8253
'jO EXT
MTR-100
60 IC5S
8255
70 IC29
8255
DATA BUS Used to transfer Instructions and Data to/from l/O
Devices and HAJ4s,
4MHs, square Clock signal derived from devide-by-2
divider ICIS
^An HO WH SINPUT OPERATION [REAOl
t1DPOFIT A-DATABUS
r> \1POfiTB-OATA&US
111PORT C-CJATA BUS
OUTPUT OPEBAT! PN
WRITE]
n1atJATABUS-PORT A
f> ;1DATA BUS -PORT B
\1DATA BUS- PORT C
11aDATA PUS -fCONTROt
DISABLE FUMCnON
XX x X IDATA BUS- J-STATE
1t1ILLEGAL CONDITION
x: X11QDATA BUS- J-STATE
D, ^
D, »
D, *
Do*
CLKO »
OUTO*
GATE '
GNDo
<- 2*
2S
21
10
19
1& P
17
IS
ID
I] 14
13 13 ., *o
A;
A.
CLK2
OUT 2
GATE 2
«CLKl
CATEl
In the MCA B25&C operates in MODE
and 8253 in different MODEs.
ED
¥R
IHT
NMI
VIAIT
Ml
RESET
cs RD WH At Ad
1toadCouniBrNo.O
B\(.Mci CoumsF No. 1
1D1Load Counter No. 7
1»VJfilt Mode Word
1CI RmiJ Coumer No,
1Read Cojrbter Nd, 1
n}1Read Coumer No. 2
Q11Nrj OpwratlDn 3-StBt«
1XXXXDiwblE: 3-StaW
%1XXNo-Operation 3- Sut*
Indicates that the address bus holds avalid memory
address for amemory read or memory write cycle.
Indicates that lover 3bits (I/O Device tober) are
on the address bus for an l/O read or I/O write cycle.
Indicates that the GPU wants to read data from memory
or an I/O device.
Indicates that the CHJ data bus holds valid data to
be stored in the addressed memory or I/O device.
Used as Tempo GlocK in PLAY mode and is accepted by
the CHJ after it completes the current instruction
being executed provided that CPU internal INT enable
flip-flop Is set on.
Used to time the lightings of Dot Matrix Display and
•Shift lEDs, Key Switch Scanning, and the outputtmgs
of CV and GATE. Accepted by the CPU unconditi-onally
upon finishing of current instruction.
Used to keep the CPU wait for 1clock cycle to Provide
enough performance time for relatively low speed ROM
and RAM being accessed by the CPU",
Indicates Fetch cycle.
Used to reset and start the GPU from apower down
condition resulting from failure or initial start-
up of the processor.

CIRCUIT DESCRIPTION
JAN.13,1982
CPU BOARD
when CPU is initialized with power-on RESET signgi, it wants to read
operational program (software -instruction) stored at address (QOOOJi*
to starts controlling the MC-4.
With Os on the addreES bus [All A15) and MREQ, ROM Address
Decoder IC60 selects ROM [a] IC36 which in turn transfers data from
accessed memory cells to DO D7. CPU proceeds steps with fetch&d'
instruction.
The following Is one of steps wilt be done.
(1) To transfer d9ta to or fronn RAMs
(2) To transfer data to or from I/O ports or Programmable Tinner
ADDRESS MAP
ft _l
Ti l^ Tj
AO~/^lS^ 1IC 1fi.Zli
MJltfl "
WJ'
WA3T „.J U.
SiT -1J
r^ 1
vSi^
0000
27P?
ROM0 IC56
ROM AREA
IlOMjYj IQYd
BLAHE
4000 ICl-ICS
(CPU BOARD)
Rjm AREA
ICl-ICS
(RAM BOARD)
(RAM BOAED)
6000
cooo
{1> Accessing 1o HAMS ICl-IGS
The CPU places RAM address onto Address bus, then outputs necessary
signals as shown in Fig, 2.
Eight 16K Xtbit RAMs are connected in parallol to form a16K )c8 bit ^
RAM block. The 14 address bits required to decode 1of the 16,384 cell a9-xU
locations within M5K4T15 are multlptexed onto 7address inputs ICffifq
(A0-A6-) of RAMs, First, low&r order 7bits ara fad to RAM$ through f^
RAM Address Multiplexers (I C9 and ICl 1)and latched Into the RAMs'
on-chip ,gddres5 latches by HAS. Second, higlier order 7bits ara fed to "^
the RAMs when SEL pins of IC9 and IC11 go Sow by the delayed t]o~dt
MREQ coming th roughpjn 8of fC12. Thess 7bits are latched into wait
RAMs' chips with CAS fed via RAM Address Decoders (iCTOand IC12),
and an acGes to RAMs completes. Data are stored into selected cells by
acombination of WRITE and CAS, qr re^trieved from the memories
in aread cycle in which CAS is actJ'vt low.
OJk CONVERTER
The digital outputs from the PORT Aof INTE RFACE \\C29| are level-
shifted by the transistors {TR5-TR11), pa$s through the CMOS
INVERTERS (IC27, !C2a), and undergo addition by the weighing
resistors to become an analog voltage. Since the MC-4 has eight CVe,'
eighi data are sampled in the tine sharing system by the 4051 DMPX
!IC46^h?|[Jbythe 081 (IC47-fC54] and output to the output jacks.
The resolution of the D/A converter is 1/'12V, which corresponds to a
half-tone Etep voltage.
The resistance error at the most sfgniflcant t>it, which affects the output
error most significantly, is corrected by adjusting the VR3,
The VR2, equivalent to the width control of asynthesiser, should be
adjusted so that the output changes in 1/12V step. The VR4 is used for
offset adjustment of IC25.
For the GATEs (GT1-GT4) and MPXs {MPX1-MPX4), digital data are
sampled by IC43 in the tinie sharing system [see Fig. 4).
CMT BUOCK
Thi5 block is composed of the input/output circuits for CMT DATA
and TAPE SYNC CLOCK, Th& selection of CMT mode (CMT DATA}
and PLAY mode [TAPE SYJ^C) IS don& by tha hardware (IC41).
The output section delivers an approximately 2JKH!; signal wher> the
DIGITAL DATA is Hand an approximately I.SKH:: signal when the
data is L(see J^ig, 5}.
M
T. Tr T,
Mrr,*Qr,WrJtcCjTrlt ^
T, T. T. —
1'" ^MftijOU. .1nynnr w^in il|
\^ _r~ \ij
\_ ,. .;
rpi IU
DtmDtT >"
.J L.ij L
(2) Accessing to Timer IC30 or lyo Ports IC29 and IC58
The CPU places port address (lower order 8bits, A0-A7] onto the
address bus, then outputs lORQ, etc. as shown in Fig. 3.
As previously explained in CPU terminal functions "ADDRESS BUS",
Port Address Decoder ^IG571 selects the device which in turn reads or
writes data.
iirr:
_r
rMPxV \\\\ \
GT '^ GT \GT \QT \
4 3 \2\1\
MPX MPX MPX
C111IQ
B110 110
A1 1 1 I QFig. 4
S.6Vpp (appr&x.)
JiMJiiJijmriJiiuiMMJUii^
Fig. 5
Fig. 3
For frequency modulation. IC4:2 is wired as afunction generator whose
frequency shifts to the other as R121 is connected to distjonnected
from charging/discharging time constant by F£T SW (TRT5|.
The zen&r diodes (D11, Dl2) are used to prevent tiie output of the
comparator OP amp [operating on 413V arid -15V) from becoming
ur^balanced and to keep tfio duty ratio of the oscillation square wave-
form to 50%. At the input section, asignal from the CMT/SYNC IN
passes through apassive band pass filter and rs ampljfied by the OP amp
(1023). The signal funher pas&es through adiode limitler, is amplified
by !C22 and is separated into asignal for control and asignal for
denriodulation, The signal fordemodulation is democfulat&d bythePLL
(IC19) and the comparator {IC20) and is read via tha S255
INTERFACE {IC5S).
The signal for control passes through arectification circuit and Is
applied TO the tr&nsistor switches (TR^, TR3t to set TP3 in active state.
(While the CMT or SYNC signal is not inputted, TP3 is fixed at Llevel.)
ISee Fig, 6,|
i«5 -^ 7juirurLrumjUL
^JIII
Fig. 6

CONTROL BOARD
DOT display/ SHIFT LEDs. KEY SWITCHES
These circuits ^re configured in separate matrices in a conyenlional
fashion but one dimension of these share the same output pins of an
address decoder 1C1.
The address decoders (IC1 and IC2 in combination) places an Iat
output pins in sequence in symathy with NM1 cIogI< brought into th^
pin €f CPU as shown in Fig. 7. The following description will explicate
Dot Display only since Shift UEDs- and KEY- scanning are self
explanative,
^...p \PCS (23} Q
ADDRsi PC2<21) QQ
PCI [19) D11
PC^[17| 10 1Fig, 7
DOT DISPLAY
Character signal consistirig of &x 7 dots from the Dot Matrix Decoder
IC9 is applied to fluorescent lamp indicator 16'MD-02Z In which the
same dots in the Individual digits are connected in parallel and led out
as acommon terminal, and the digit electrodes have indtvldual leads
(G1-G15) for externa! connection.
Although the same dot signals are fed to all digits simaltenousiy, only
one digit whose grid is now His allowed to illuminate -called dynamic
lighting. But for human eyes those flickers are not perceptible.
Since filament laid across the tube serves as acommon cathode for all
digits, DC heating will cause brightness imbalance among digits due to
potential variations between el&ctrodes and the chathode.
METRONOME
Output from oscillator IC7 is shaped into metronome-lick sound with
percussive envelope developed In Tr35, C5 and R1 16 circuit.
TEMPO CLOCK GEMERATOR
When nothing is connected to the TEMPO CV jack, aconstant DC
voltage of approximately 4.17V is applied to pin 5of tC6 when the
TEMPO control is set at the center. The voltage is applied to the VCO
through 106 and IC5, and the VCO oscillates at approximately lOOKHz,
Since the VCO's oscillation frequency changes linearly to the input
voltage, when the input voltage is doubled, the oscillation frequency is
also doubled. When the linearity is improper {especially at the high
frequency range), the slew rate of IC3 is slow or TR31 is defective
in most cases.
When an external CV is applied to the TEMPO CV IN jack, the TEMPO
CLOCK is subjected to frequency modulation.

JAN,13,19a2
MCr4
C3 DZ Metal film CRB2&DZ(0,b%25PPM) Q2SC1815-GR
-3 aO Carbon R-25J
Ocr> Metal film CRB25FX(1%100PPM)
#HCrJ Metal film CRB25DY (0.5% SOPPM)
1"'^ *Crj Metal film CRB25BY (0.1% 5DPPM}
^'t; (C>) Trimmer SR-19R
01 2SA1015-GR
Q2SK30A-GR
3Rc$ijtar array
((^) Metal film trimmer F?J-@P
'"" f3Mvlar(10%J
(^Polypropylene (5%)
"' <r~~|> Ceramic
^Pinl
GMetal film trimmer RJ 6S
1S2473
-CjT)— Z&nner
f^'i *^0 *LEDTLR13'V
(orGL3AR1)
'^r^^ 2SAS82Y
I(^ Test point LC-2-3
,Jumper
K.
SUPPLY VOLTAGES
PiN CONNECTIONS
(Top view)
r
1C11,F& ILM,
nJ-™v-^ M
^
rr
J
CPU k)ARD 6PifiUd(149H1^
uzt
Jil 11^15

\
t^'^ 90" ^1 '^ ?
«

CH5-3S
CUT Ct4S-40
Etc -31.
tNi -34
tut -
1

Sm7 dot matrix decoder
iJ-2048{TopVtew)
iSiMface mounted at toil side)
"F^
2\<5 .^
?^7 *2; ^?v
-^-^ ,i 4r5v
r?\5 56C'Ci^^D ,
-?*.4 ^" +5V
=?fl3
FA2 'VI- ;2 +5V
r- ^i w^-^y/ 1
-FA* 16 DC^ND
.-- -^fl- ^CQN{?
,« PCI 20 t(irJD
S. ?;2 22 ^IZV
s'-3 aJ+ ~15V
:=->^ PS'? 2fc rEE>AL-5T/^RT
^pft5 -K—23 lPfi3ftL-ST0P
^COf^CK
r&4 32! DliJ CK JrJ
^fBS ^5+ 7SPE/EXT£fflC
=^ PB2 -a- 3i JNT-Cfc
«* PSl 5?J MODE
^?Ejr V40 c>^r
*w'C. +2 fl/^Y
*^ 'VCLE ++L&PIT
^- s^^VfT W6 T£M?0-Ct
*-" -i SWD WACiWD
-^ iG, NO 5^ T-EM?0 CV
--> f^AM BOARD
CWZ
A7 2A8 I
-A6 4A?
rA5 6/^/^
-.f(^ ea;/
iA^ 10 ArZ
,- A2 12 A3
=i AT f4 A7+
FAO fc /1/5 ..
r- IJ'arJD r? 0-6W0
j« j-GWO 20 £>-f5A/£i
-, -5/ 22 ".5V
&+;2V 24 f/2V
i^ ^72v £$ +/2V _.
;2^ -^.5V 2S -^5V
j= TSV 30, f5V
3^ L^NO ^32 D' ^WD
=^' -iT- INT .3+ RESET
=IZ 2-fMH^ ^A VSfort IB
-y- wR 33 lona
^??. no 40 Mfia
^»rM vp(s. r*^ RAM -DISABLE
<z 37 44 D0
«*S &6 'Ki Dl
-#^ i?5 ^d2
ii^ D^ i5 l>3
Pin No. Signal 1/0 Description Fin No.; Signal 1/0 Deacrlptlon
1HC '1 :
B,i Dot dJsplflj output
2HC 32 1
!
!,<, "
JNC 33 liss '^
dCts Bot display wtput 3A Iw Qot dlsplsy/prlnt
output
5Pfr^ "35 P.I c Dpt display output
6V,, "36 I^«
7Vdd 37 U^, "
BGND 38 CUD
9Dt2 °Dot display PTiCput 39 B.5 Dot display tiutpuL
30 D„ Eot diBplay/print 40 A, Opt selEct Inpdt
31 B55 Doc display cutpwt 41 Ai 3"
12 Dji. "Ji2 Ai "
13 Psi 43 Ai ^-
UD^3 44 A.
15 Oil P«tPUt 45 A5 "
16 HC 46 HC
1? HC 47 At Dot sfclECt input
IS ^n Dot dlaplay/ print
output 18 A, 1'
19 h. Dt?c display output 4S A^ M
20 ^13 °"5D A, '^
21 I^i. fi -51 C£, CMp enable Input
22 0l5 '52 CE5 Display/pj^lnt selfrct
lf!t)l3t
23- Dj, Dot dlspljiy/prlnt
output 53 Vn
24 Dr? Dot display output 54 »7S Bot display omput
25 D23 T>ot diffplay output 55 ^n DEot diEplay output
26 Hzu "56 ]=Jt
27 Ojs "57 Dt5 '
23 Bll Oat dispi^y/ptiat
output 53 D,, Dot display/print
tjutput
29 wc 59 uc
-Djz Doc display output 60 «c
WIRING DATA TABLE
CMJ_±
i| ?£ DAL -START
3! FEPAL STOF
4-1 cy^T/^TfJt: OCT
5iCAfrArtcff^J
\C^/3^^?wyL^^•
<^i^p
(^J^O
f5^
CFiV BOARD
CW6 —
i^ ^j^T^V^/fJ 2i rt '(iWD
5gyT.fiflT£ >/;i4l A^Wfi !
5^rwC-C< l!^ 6MPX4 .
7.-E-YNdOt a/T 3aT£ 4
1CAL .10 fiFX 3
!) TL'/V£= /^ <^A7^ 3
}^ +/2V ^^/VX2
f*> V-/2V MS/^T£2 _
f7 -15^ f? MPX J
2t ~b' (5V£>
?a Gr=!T£I_
iCV T-.2
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517 i? <S/VO .?i 2-2
27 <^Ni? J6 2-1
^D-C?^fD 30 3-2
?i\ |A^ ^ND 5^,, 3-1
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A^/Vt> bS f^-QNO
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VELCK 2€,Nb !
5
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?3 <P3 /4
/^ £>2 /6
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^'? D0 2t:
£f C5£i_" 2£
?=? ^S2 £4i
^-^ R57 'zd
^i?5;^ ^i
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3\ -32 -:
33 -^-
4-5 Vi,*,iB^ii,i4(
1TCii 17
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put 4^2
^
1?
1+;2v
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3A^WD
4/I <>/J0
5-2?V 1
6-22v ^
7
1
1f5v 1
f5v ^
P-^N-i?
Da/^D
CPU BOARD
1!CK 1
ZICOWT \mNOUJ
35T/lKTAroFj
4C^ )
^CO^T >0/A/ /A/
6^T-ARTAror
TEHpO CK 4t (V
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L^J '--'" 16MD-D2Z PIN CONNECTION (TOP VIEW) r^—
1
1
—n 4 Bfi 7&g!a 11 12 13 14 16 te 17 IB 19 g21 22 23 26
G10
27 !& ?9 3D 31 32 33 ', 34 M36 31 30 3& "41 42 43 44 45 46! 47 ^49 so ^1 52 63 &4 6g 56 57 sa &<» at) bl
FNl> Nf G15 1^ 2-5 3-5 G15 4-5 5'5 G14 1^ 2-€ 3-6 G13 4^ &« G12 rjp Nf NP G+1NP MP NP NF NP GS MP tI4P G8 NP NP G7 Nf NP^NP 05 NP NP G6 1-7 2-7 [3-7 e4 A-7 57 G3 NP NP V^-2 ^UK Igi HP MF> jFh

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4^ tP
Ipggg ktl*-t«^l^l^ kStpV?
iciz. 10

JAN.13,1982
'-«. CMS
I*K>-
m^
J40-
iZQ-
90-
6Q-
S^
CH-4
CVl
3^16
n"(-t i;f To ia
CVl CV2 GATf MPX
fhjt
CV2 GATE MPX
ft, fh. rt,
:^2 GATE
ft__jh.
fl
II
JGATE !
i!fl
JEXT I
IINPUT
n^i. rh
t,
INPUT
TEMPO
CV
hJ21
UTPUl
EXT
SYNC
+12V
A
%15/.33.
at0^?./?
<?'f
O2!. -J?
1S -fB ;!0 Si :-3 ?4: "i^£i ^6 ;?a 29 3.0
JACK BOARD
OPH142(149H142)
(pcb 052H285C)
Flat cal3le H132
MMr^n i
IiIi1iiiiizi
Io;
iI; } j;;!/////
iTrS
*®
OChaagig HII3
CONNECTOR BOARD
OPH144(149H144)
(pcb 052H331)
Connector PCTT-7O4Q034 AU/L
052H33I
lM!:;3:::::::::":::::fy7i
o
Zlat cable HI 34
O
O
'^
12

74LS74
Ousl D-FFs with preset and clear
FUNCTION TABlt
INPUTS ClUTFUrS
PREHr CtE*H CLOCK D. dQ
LHXX
»Iii ^
LLXX
HK1^
HH1L
KHLX
LK
HL
LH
74LS92
DUAJ. 4-INPUT NAPJD GATE
Fl pn ra mra mm
^dJ
^
74LS157
QUAD 2-lNPUT MULTIPLfXER
CONNECTION DIAGRAM
DIP (TOP VIEW}
;.OGtC SYMBOL
1^^
TRUTH TABLE
EWABLe SELECT
INPUT IhlPUTS auTfUT
¥5*5 ll z
L
L
u
1
X
rt
L
1-
X>;
Xt.
XK
LX
HX
L
L
H-HIGH VoJlsge Level
L-LOW Voitdflt Level
X'D&n tCite
74LS368
HEX 3STATE INVEPTER SUFFER
SEPARAtE 2-BIT AND ^&I7 SECT OfOS
,.R ^F^ Rmffl
.r?w^
74LS138
l-OF-8 DECODER/DEMULTIPLEXER
MK4116
16.384X 1-BIT DYNAMIC RAM
L0QIC5YMB0L CONWECTION DIAGRAM
DIP (TOP VIEW)
A, »i *i f
?c ^l t^ °> °^ =^ °f_^_
TTTTT
I* II r? II Id I
GND -Pin 3
74LS139
DUAL l-OF-4 DECODER
LOGIC SVMBOL COMNSCTIONDIAGRAW
DIP(TOPVIEW|
.i-LL
rrr
0( a, 0^ u
TTT
GNo -Pin a
74LS245
Oclal 3Stale Bus Transceivers
[TOP VIEW!
fUMCTIOH TaEI,E
DIRECTlCm
^'^*'='-^ CONTROL
*^ Dm OCEnATIDM
HI
edm mABM'
AdimaBlwt
lidttiwi
TRUTH TABLE
IMPUTS OUTPUT
^TD
L
L
H
L
H
X
H
L
(Zl
LJlljmUJL^liJL^W
PIN CONNECTIONS
vst 1[]
Din 2C 1
WRITE 3[ ]
rIs U]
Bp 5C :
ft? 6[ :
A| 71 :
Vqc e[:
15 CAS
14 DguT
13 A,
l£ A,
MA*
10 /kj
TC4099BP
9-Bit Addrassable Latch
PoL>T
rx5
STnOHE
DoTa in
SvHm nEADmniTE 1HPUT
Vbb POWEft :-5VS
Vjc POWEH M&V)
ROW ADDRESS StFlQ9E[
/iPC78L MC14528B
DUAL MONOSTASLE MULTIVISHATOFi
/1\
UUT t;ti:i> JN
MC14070B
QUAD EXCLUSIVE "OR 'GATE
V^p-flflK
4f«tn Owen]
MC14051B
a-CllPJiMl Analog
ML.IIipl«CP^D«|iiuH<pl*»«1
BLOtK DIftGHAM
^^ "X
rT1 TJ 06
lOD —,.
cn "x
^—.„ —am
;'::3D
V
gomwi. IHFXirS MJEBtaa lUFuTS !DUTTUTa
..1
RESET If. SIS BA"1 =qi di 53 <n 4i %r
-
J, vt »*LLLLLL^L
\> »~m-~---"--
aLI^ I, L L LI' .L_L
HL1. LT) 1 L Jjrj I. '^ 1.
HI. 1, LLniL1j LI
aLLLLL D Ll^ LI-
HHLLLLLL_!>_
^LHLLL1. LD:^
rt LH^1. L1. LLEI.
HLKLL L Lh_ 1. li p_
bt, li n-~-Z- -;_ """
I. t. 1. -E- - :!. __^ ^
LJ- L--D-"~~
..
"
LI. L-_-C----..
LLH-- - - _i> --^
LH
LI. .\H- - - - - --D~.
LJ. y!Hu- - - __~. -1-~L^1i>
EOM'T C132
MC145X8B
DUAL BCD UP COUNTER
HTAflLE
Ct-OCK £N/^aL6 BESET ACTiOh
-jT Tlr.tF<rT,..^lCO^"N^
—\_ l.iC.«ry.ni£oa/ilv
-\_ Kho cn»"9»
}« _y~ Mb tjhkftji
_f- Mo CH..1M
... ._, ~\_ ly^C".n|w
^>OO ihrij 03 -
BLOCK- OlftGFlAM
Wilt*
tlMbl^ Rn*1 L*1Eh L4Kh
^^ QUI
1Diti Riill*
TBDn" Or.'
1
"-" 11n.»i 1ntP^i
'Or, II Br»yiftU+|lll» [Jflncll.
^PD27 i60
16K (2K X8) UV ERASABLE PROM
{.Top View)
'liC^ lr.l1.ll.T
C»ntf»[j<
90— c
FV Cl„l
5<3
—OJ
SO
—
iCS
^C5— ^S
LJO— «>
SS"""'
s-T
ivss T*Uct ±1
13

ADJUSTMENT
CPU BOARD
1^15V
1-1 Connect digital voltmeter (DYM)
across TP5 and TP2 (aND)
.
1-2 Adjust VRl for -l^-OOO+^mV.
2D/A OFFSET
2-^1 Set controls;
TOTAL TTXNB -center
CYCLE -OFF
STtTC -INT
TFS
o
®
TP3
CU [13
2-2 POW^R ON.
2-3 Write CVl and CV2 data (OV)
for CHI to CE4j following the
flow chart shown right.
(simultaneously )"="
(4 times)-^
—
2-4 Shift the DVM lead to TP-1.
2-5 Flip MODE switch for PLAY mode.
CPU BOARD
Jtb nio jo ts[
2-6 Push ENTEE. Fe^tI
2-7 Adjust lffi4 for 0,000V. (0,000 to 0.099V)
Keep the CV data for the .next adjustment.
[I
[r
3
T^^l
1<^i
1m
3CV OFFSET
^his adjustment follows the preceding.
3-1 Insert plug with DVM
into aCV jack.
3-2 Adjust related VE for
O.OOOV (0 to +O.2111V),
3-2 Repeat the step for the
remainder.
GH^ 4321
GV2 11 12 13 14
CVl 78910 I^ VE
4D/A, WIDTH
[T6 no 3p TSJ
11-I
!11«
112-
1^ 1in
1! 13-
1 1 32^^
114-
11niw
11M--
111?
4-1 Turn power off then on.
4-2 Connect DV14 to CH-1 CVl jack.
4-3 Enter the CV data 0-120 in 12 increments.
4-4 Hereafter, pushing S'tfD button will change
data (and CE-1 CVl at the jack) and
display hy 12 at every step as shown
below. J}lote that the data displayed on
indicator lamp precede actual data by
one step-
Lata
displayed Ac tiial
data OVl (To he +lraV)
volt
12 0.000
24 12 1.000
56 24 2. 000
48 35 3.000
60 48 4.000
72 60 5.000
84 72 6.000
96 84 7.000
108 96 8.000
120 103 9.000
..
.
120 10.000
(120 10.000 )
-5 Adjust VE2 to the tahle above.
Use VR3 to compensate for higher CV only (data 72 and above).
14

5CMT FREQ
5-1 Flip MODS for PLAY.
5-2 Vith freq.uenc7 counter
connected to TP-4
adjust VR6 for 1.31^a+5?&.
5-5 Verfy that frequency changes
to 2.1kHz +5?£ when mode is
set to Om.
6PLL FREQ
prrl^l
CC^Y
mxio 30 JSj
111-1
1f1SI
112-
n)13o|
Isimultaneou
h11M
|l 11isl
ll 1151
ii ^ ^ _^
h11&1
|i 12-
6-1 Connect CMT/ SYNC I!T Emd OUT with
acord.
6-2 Connect scope to TP-5.
5-5 Input data by following the chart
shown at the left.
"Waveform will appear on the screen.
n1101 -1
1cycle
LTLJTJI
Li i1. 1
_p AiB =1:2
IKK 1B:G =1:1
6-4 Adjust VR5 for 50 duty ratio except
Aportion*
VJhen waveform disappears during adjust-
ment, push [T] and [i^J .In afew
seconds waveform will reappear.
Th11001 ^
M00ESW2 (flip MODE twice)
1CMTCVREF
CAUTION
If trijaimer wiper is frozen, try
adjusting at component side.
PAIHT LOOKED !
1-1 et controls: TOTAL TUNE
TBMPO center
center
[IB r2D 30 is]
e:
oVk4
VKl o
oV^2
(view from foil aide]
1-2 Connect GH-4 aV2 and TBMPO CV IH jacks
with acord.
1-3 Input data as shown right.
^^ ¥hile plugging
out and in the
cord at TEMPO CV
IN jackj adjust
VR4 so that
"time" being
displayed remains
unchanged.
CONTROL BOARD
2CMT FREQ, LINEAR, OFFSET
2-1 Observe steps 1-1 and 1-2 above
-
2-2 Enter data as illustrated at right.
2-5 Connect frequency counter to collector
of TR2S.
2-4 Adjust VHs respectively for the
frequency in the table below.
To change data push FWL ,
First, coarsely adjust TRJ> for lOOkHz,
then the remainder
.
2-5 Repeat adjustment until correct
frequencies are obtained.
ENT
^NT
ent
COPf [E
EnttI
14;oi 1
0V2 YR Preq,
10 7E2 20kHE
50 YR5 lOOkHz
100 imi 200kHs
flip MODE for PLAY
[4" IM 4.'?!
EVT
ENT
^MT
no 30 fsl
|4 11-
|4 T4H
K" 115*1
EH
15

PARTS LIST
CHASSIS
Oe^Hlia chassis Hn3
061 H1 12 CtiaSSisH112
0S3HQ37 Side panel H37 (right)
Cie3H03B Slds panel H3S {lehl
072H074 Pa^el H74
Q48H02& Heat sink H25
116H0CI5 Jqintscr&w H5
065H0B2 Cover H82 ifluorescent lube)
D66H091 Cover H31 (rear cover)
KNOB
2247540600 K34 TYPE METAL
KEY TOP
12479704
124797D5 ,
134492^0
1344940600
KT3-2 blue [tandem)
KT3-1 iyory, btue
HUl 02^01 010
HSJ-779-OI.O'EO (miniy
SLIDE SWITCH
13159113 SSB042-6LS
POWER SWITCH
13U9103 2WiXll
LEVER SWITCH
13T3913& SLE-622-18P ICYCLE)
13139135 SLE-623-1S? (5YHC)
13139132 SLE722-18PIMODE>
KEY SWITCH
13129714 KeH109O3wrskevtop
1312^716 KEH4A006f10KEYASS'Y}
PCB
149H140
I49hll4t
149H142
149H143
149H144
146H066
M6H067
CPU BOARD OPHl40(pcbO52H249C}
CONTROL BOARD 0PH141 [pab 052H250E)
JACK BOARD OPH142 (pqb052H285C)
RAM BOARD 0PHt43 (pcb052H333C)
CONNECTOR BOARD OPH144 Iptb 0b2H3311
POWER SUPPLY eOARD PSHeS (pctj052H251Al 100/n7V
POWER SUPPLY SOARD PSH77 ^pcb 052H2&1 A) 22C/240V
15169301 HO
15169303HO
1516Q346BO
1516930480
15169335HO
15169347BO
15169311HO
15169340BO
15169318H0
15169319HO
15169332HO
15169324CO
1616932SHO
1516^117
151891160A
15189117
15189118
151891 11 NO
15189105
1&219105
15159104TO
151591 12T0
15159113HO
1&1S9117TO
1515912C1TO
15159309TO
TRANSISTOR
15129816
15129606
15129&0O
15119402
1&119123
15119113
151196Q1
15129121
151 29703
1512913200
15129114
15139103
15139110
74LSO0 QUAD 2INPUT NAND
74LS02 0UAD2-INPUT NOR
74LSa3 HEX INVERTERS
74L504 HEX INVERTERS
74LS20 DUAL 4-U^PUT NAM D
74LS32 QUAD 2-lNPUTQR
74LS74 OI-IAL D-FFs WITH PRESET AND CLEAR
74L5132 QUAD 2.INPUT NAND SCHP^ITT TRIGGERS
74LS138 1-0F-8 DECODER/DEMULTIPLEXER
74LS139 DUAU1-0F-4 DECODER
74LS157 QUAD 2-INPUT MULTIPLEXER
74LS245 OCTAL 3-STATE BUS TRANSCEIVERS
74LS36a HEX 3-STATE INVERTER BUFFER
7407 HEX 0,C. BUFFERS
TLOflOCP OP AMP {factory selected)
TL0B1CP OP AMP
TL0B2CP OP AMP
^PC3nC OP AMP
;jPC4558C OP AMP
LM565 PHASE LOCKED LOOP
TC4011BP QUADRUPLE 2-fNPUT NAND GATE
TC4049BP HEX BUFFER/CONVERTER (IMVERTING)
TC4051BP G-CHANNEL ANALOG MULTIPLEXER/DEMALTlPLEXER
TC4070eP QUAD EXCLUSIVE ''OP" GATE
TC4099BP 3BIT ADDRESSABLE LATCH
TC452eBP DUAL MOWOSTABLE MU LTlVIBRATOR
SEMICONDUCTOR
1C
15199116 ;,PC14312H 3-PIN REGULATOR
ITA7S012P)
15179111 ;iPD7a0.1 B-BIT MICROPROCESSOR
(LH-QOSOA)
15179306 MBB11SN 16,384 X1-BIT DYNAMIC RAM
1B179605BO M&L27t6K 16K (2K x81 UV ERASABLE PROM
(i^Basisi
15179110BO M5LS253P-5 PROGRAMMABLE INTERVAL TIMER
[iiP 08253-51
15179120 LI204e 5«7DOT MATRIX DECODER
15199^09NO MPC7BL05 3-PlM REGULATOR
1S17S12S *JpDS2^^''^ PROGRAMMABLE PEFllPHERAL INTERFACE
(MSL8255AP}
DIODE
15019247
150 1920S
1501^123
15019103
1501&624
15019B31
15019532
15019612
1501962B
15029103
t50291 05
15029133
15019250
15019243
2SD380-Y or 0, GH
2SD844-Y
2SD571-L
2SA682'Y
2SA1 175 JF or HE, FF. EF, K^F, |2SA11 15-E or F), (^A937^
2SA1015-GR
2SB605^L
2SC202VRDrS
2SC1226 A
2SC1923-0
2SC1S15-GR
2SK30A G R
MF510or2N4392
GP-30G (Hi-Fi Special)
1SR35-200
1SI 585
1S2473
1SZ52
DSZ7.5Y
5Z36 X
0525.1 X
05Z5,6-U
TLR124 [redl
TLG124Atgrn)
TLY124 (yel)
D65BN'M
1B4B1
1BO29703 16MD 02Z fluorescar^t lamp ir^dicator
POTENTIOMETER
ROTARY
13219601 VM10R-S2aA1b [lOOKA] TEMPO
13219312 EVHLWAD25B14 (10KB)
TRIMMER
SR19R
13299111 2,2K&
13299114 10KB
13299115 22KB
RJ-6S
132993D6 50OnE
13299307 1KB
RJ-6P
13299131 20KB
RESISTOR
CRB25FX(1%+lDDppm/°Cl
137691S2DO 1.3K
1376918900 47 K
137691 97 DO 10OK
13769201 DO 150K
CRB25DZ [0.5% +25ppmrc}
13789601 DO 100K
13789602DO T30K
CRB25BY|0.1%+50ppmrC)
137S9501DO UK
137B95Q7DO 31K
137S9503DO 125K
1378950400 250K
CRB25DY (0.5?£ +50ppmr'CI
1378911300 600K
137S9114D0 1M
ARRAY
13919108 4R7Kx4(RC3SD4x472K)
13919109 4R7KxS^RGSD8x472K]
13919110 22K k8(RGSD8x223K)
M0'4S
138391 43 FO 0.33n 3W
13S39145F0 82t^ 3W
FLAT CABLE
D&3H131 FLAT CABLE K1 31
053H132
053H133
053 HI 34
IC SOCKET
13429S1
1
13429608
13439178
13429179
13439176
13439177
13439120
13439121
13439122
13439126
OTHERS
22 15050 100
2215050300
065H090
065H19G
064H055
D64H0B3
064Ha92
064H111
107H061
NOlSe FFLTER
12449219 ZGB1 201-11 (100/1 17V)
12449220 ZMB2201-13 (220y240V)
FUSE
125591 33
12559532
125 595 18
12559516
SPEAKER
12389806
MGP1.0A PRIM. 100/117V
CEETeaOrnA PRIM. 22Of240V
CEET500mA SEC. 220/240V
CEET3.15A SEC. 22O/240V
EAF-16R02C
FLAT CABLE HI 32
FLAT CABLE HI 33
FLAT CABLE H1 34
22P 50V J(palyatyrene)
IC-49-2406#2 {24P}
TCSO 25^1-1
FCN-7O4Q034'AU/L 34PIN
FCN-724P034-AU/L 34PIN
FCN'724P040-AU/L 40PIN
FCN-724P0&0-AUyL 50P1N
5045 04A
504&O5A
504506A
5045^ 10A
LONG NUT #1
LONG NUT^^3
Cover H90 (radiation cover)
Cover H190 [lever SW)
Holder H55 {pot.)
Holder H83 Ikev SW asay 41
Holder H92 (key SW assy 1, 2, 3)
Holder Hill [keySW^ssyB)
Cushion Hei
CAPACITOR
13563153 CQ09S-1 H^220O0-JO& 2200? 50V J(pDlYStyren&]
13569152 CO09S-lH'240RO 240P 50V J!polv^tvrer>e)
13569151 CQO9S.1H-022RO
CONVERTER TRANSFORMER
12449105 SI 67724
POWER TRANSFORMER
022H044J 1ODV
022H044C 117V
022H044D 220/240V
16

JAN.13,1982 MTR-100 JAN.13,1982
MTR-100 SERVICE NOTES
First Edition
SPECIFICATIONS
Memory Capacity -250 Kbytes (Each side of atape)
Dimensions 218 x348 x118 mm
Weight.... 3,4 Kg
Power 25 W(Dom), 30 W(Exp)
Accessaries .^..-tt ,, tConnection cable x1
Data cassette x1
Pan^J HS9 1072H0891
LED board
149H 160
Side panel H40 E0S3H04Q)
Powar supply board
(100/117V> 146H06S
(220/240V) l-lSHOeS
Conriectoi"
FNC'7MQ03'1AU/L
(13^139178)
PARTS LIST
CHASSIS
061H129 Chassis H129 (MAIN)
061H130 Chassis H130
PANEL
072H089 PANEL HS9
107H062 Cushion H62
04SH026 Heat sink H26
083H039 Side panel (right) H39
0a3H040 Side panel (left) H40
FLAT CABLE
053H135 Flat cable HI 35
053H136 Flat cable HI 36
POTENTIOMETER
TRiMJVIER
13299109 1KB{SR19R)
RESISTOR
M0-4S
13839146FQ 4.0n (3W}
13S39T47F0 ].bn (3W}
CONNECTOR
13439178 FCN-7D4Q034-AU/L 34 pin
13439123 5045-07 A
13439180 S273-07A
CASSETTE UNIT POWER TRANSFORMER
|hH^^^ 12439502 MT-2 022H046J PTH046J 1D0V
022Ka46C PTH-046C 117V3PCSA
tJi^lKir^^] POWER SWITCH 022H046D PTH-046D 220V, 240V
^SiM^M 13149103 2wixn FUSE
HHhIh ^^^ 12559133 MGP1.0A
146H068
146H069
Power supply board PSH6a 10D/117V
(pcb052H334)
Power supply board PSH69 220/240V
12559532
12559614
12559516
CEET630mA
CEET2.0A
CEET3.15A
149H160 {pcb052H334) LED bo^rd OPH160 (pcb 052H336} NOISE FILTER
149H145 Connector board (pcb 052H331) 12449219
12449220
ZGB1201-11 (100/117V)
ZMB220T 13 (220/240V)
SEM [CONDUCTOR
-"
IC
15199101F0
OTHERS
CossaltB jnit
MT-2 1T2<13&502) ;iA7230C 2215050300 Long nut #3 (18mm)
2215O5OT0O Long nut #1 (lOmml
Ctiessi5H130(06^Hi:^0) TRANSISTOR
15129114 2SC1815-GR
15129825 2SD844-0
DIODE
Flalt^ableHK
{053 K135) 5
Chassis H129 (061 H1291 15029103 TLR124[LED)
15019103 1S2473
15019250 DS5BfM-M
15019634 RD3.9Ee
ISRoland ?7

MTR-100 13 m
POWER SUPPLY BOARD
PSH66(146H068) 100/11 7V/PSH69(146H069) 220/240V
(pcb 052H334)
;-^2: ]\ F
-| V8 21
1/Vl2v
-! /apJ
?
'i^
^::L
!
;MT-2
FLAr;
^i^n ^*^
4^ Hl\
11 ;o It «
4b8^0
\l i^tt IS
tt zt 1+ :i
n?D ^i M
I
V
ADJUSTMENT
Measurements must be done without disconnecting
connector housing.
1. Adjust VRl for +5.00V.
2. Adjust VR2 for +12,00V,
3. Confirm RESET Signal at
Pin 14 upon power ON.
^V
p«vtflE^ OU
\,® (^
lOOV ELU
.1177 PiRN
230V BRIT RED
240y RED BRB
(MOTE; MT-2 is, 9S awhale, named maker-only-repairable component.
The Roland Company will promptly supply the replacement or repair the unit upon reception.
Please do not disassemble the unit In question as this will void the service polycy,
Return complete MT-2 with atag identifying the unit by using the mode! version and serial
number of the iVlTRlOO in which it is usad.
PT secondary winding ratings
[email protected],6300^F IN
[email protected], 22O0jiiF EN
'T. '%
T
18