Samsung KS8910 User manual

20-8910-0599
USER'S MANUAL
KS8910
100/10 Mbps Ethernet Transceriver(PHY)
Preliminary

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KS8910 100/10 Mbps Ethernet Transceiver User’s Manual
Publication Number: 20-8910-0599
Publication Date: May 1999
1999 Samsung Electronics
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PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER v
Preface
The KS8910 100/10 Mbps Ethernet Transceiver User’s Manual is intended for application designers and
programmers who are using the KS8910 100/10 Mbps ethernet microcontroller for product development.
The first six sections of this manual give you a general orientation to the KS8910 100/10 Mbps ethernet
transceriver:
•Section 1 “Product Overview” introduces a product and describes features, PCI system, controller application
configurations.
•Section 2 “External Signals” describes external signal, pin assignments, and signals.
•Section 3 “Functional Blocks” describes functional block, MII, PCI bus, DMA function block, and MAC
functional block.
•Section 4 “100 Base-TX Digital Blocks”
•Section 5 “10 Base-T Digital Blocks”
•Section 6 “Analog Blocks”
•Section 7 “Registers”
•Section 8 “Electrical Characteristics”
•Section 9 “Application Note”
•Section 10 “Mechanical Data”
•Section 11 “Appendix”

PRELIMINARY SPECIFICATION
vi KS8910 100/10 Mbps ETHERNET CONTROLLER

PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER vii
Table of Contents
Section 1 Product Overview
Introduction ............................................................................................................................................1-1
Features ................................................................................................................................................. 1-2
Ethernet 10Base-T and 100Base-TX Block Diagram .............................................................................1-3
ReferenceDocuments .............................................................................................................................1-4
Section 2 External Signals
Overview .................................................................................................................................................2-1
External Signals ......................................................................................................................................2-2
Pin Assignments .....................................................................................................................................2-3
Signal Descriptions .................................................................................................................................2-4
Section 3 Functional Blocks
MII data Interface ....................................................................................................................................3-1
Management Agent ................................................................................................................................3-2
Power Management ................................................................................................................................3-2
Control Registers / Status Registers .......................................................................................................3-2
Auto-Negotiation .....................................................................................................................................3-2
100 Base-TX Digital Block ......................................................................................................................3-3
10Base-T Digital Block ...........................................................................................................................3-5
100Base-TX and 10Base-T Analog Blocks ............................................................................................3-5
Section 4 100 Base-TX Digital Blocks
Overview .................................................................................................................................................4-1
Physical Coding Sublayer (PCS) ...................................................................................................4-1
physical Medium Attachment Sublayer (PMA) ...............................................................................4-2
Physical Medium Dependent Sublayer (PMD) ...............................................................................4-2
Description of operation .................................................................................................................4-2
Physical Coding Sublayer (PCS) ............................................................................................................4-4
4B/5B Encoder, Decoder ...............................................................................................................4-4
4B/5B Encoder (Transmit STM) .....................................................................................................4-6
4B/5B Decoder(Receive STM) .......................................................................................................4-6
Parallel and Serial Converters .......................................................................................................4-9
Carrier Sense .................................................................................................................................4-9
Physical Medium Attachment (PMA) ......................................................................................................4-10
Scrambling .....................................................................................................................................4-10
Link Monitor ....................................................................................................................................4-12
NRZ to NRZI AND NRZI to NRZ ConversiON ...............................................................................4-13
Physical Medium Dependent sublayer ...................................................................................................4-14

PRELIMINARY SPECIFICATION
viii KS8910 100/10 Mbps ETHERNET CONTROLLER
Table of Contents
Section 5 10 Base-T Digital Blocks
Overview .................................................................................................................................................5-1
Transmit Function ...................................................................................................................................5-1
Jabber Control Function ..........................................................................................................................5-1
SQE Function ..........................................................................................................................................5-3
Receive Function ....................................................................................................................................5-3
Polarity Reverse Function ..............................................................................................................5-3
Collision Detection Function ...........................................................................................................5-4
Loopback Function ..................................................................................................................................5-5
Link Integrity Test.....................................................................................................................................5-5
Section 6 Analog Blocks
Overview .................................................................................................................................................6-1
100Mbit/s Transmit Circuits .....................................................................................................................6-2
Frequency Synthesizer ...................................................................................................................6-3
Crystal Oscillator ............................................................................................................................6-3
Transmit Twisted-Pair Driver ..........................................................................................................6-4
100Mbit/s Receive Circuits ......................................................................................................................6-5
Receiver Buffer ...............................................................................................................................6-5
Adaptive Equalizer ..........................................................................................................................6-6
Base Line Restore ..........................................................................................................................6-6
Clock Recovery ..............................................................................................................................6-6
10Mbit/s transmit circuits .........................................................................................................................6-7
Transmit Wave Shaper ...........................................................................................................................6-7
10MBit/s Receive Circuits .......................................................................................................................6-7
Receiver .........................................................................................................................................6-7
Section 7 Registers
Overview .................................................................................................................................................7-1
Register Definitions .................................................................................................................................7-2
PHY registers ..........................................................................................................................................7-3
Base Mode Control : register 0 .......................................................................................................7-3
base mode status : register 1 .........................................................................................................7-5
PHY identifier 1 : register 2 .............................................................................................................7-6
PHY identifier 2 : register 3 .............................................................................................................7-6
Auto-negotiation Advertisement : Register 4 ..................................................................................7-7
Auto-negotiation Link Partner Ability : Register 5 ...........................................................................7-8
Auto-negotiation Expansion : Register 6 ........................................................................................7-9
Auto-negotiation Next Page Transmit Register : Register 7 ...........................................................7-10
10Base-T Control Register : Register 16 ........................................................................................7-11
100Base-TX Control Register : Register 17 ...................................................................................7-12
PHY Address Register : Register 18 ..............................................................................................7-12
Map Table Register 0 : Register 19 ................................................................................................7-13
Map Table Register 1 : Register 20 ................................................................................................7-13
Analog Control Register 0 : Register 21 .........................................................................................7-14

PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER ix
Table of Contents
Analog Control Register 1 : Register 22 .........................................................................................7-14
Analog Status Register : Register 23 .............................................................................................7-15
10base-t Status Register : Register 24 ..........................................................................................7-15
100base-t Status Register : Register 25 ........................................................................................7-16
Section 8 Electrical Characteristics
Absolute Maximum Ratings ....................................................................................................................8-2
Recommended Operating Ranges .........................................................................................................8-2
D.C Electrical Characteristics .................................................................................................................8-3
MII PADS Specification ..................................................................................................................8-3
100base-tx transceiver Specification .............................................................................................8-3
10base-t transceiver characteristics ...............................................................................................8-4
Timming ..................................................................................................................................................8-5
OSC clock frequency .....................................................................................................................8-5
MII-transmit clock Tolerance ..........................................................................................................8-5
MII-Receive clock Tolerance ..........................................................................................................8-6
MII/10base-T Transmit Timing .......................................................................................................8-7
MII/10base-T receive Timing ..........................................................................................................8-8
MII/100Base-TX Transmit Timing ..................................................................................................8-9
MII/100Base-TX receive Timing .....................................................................................................8-10
MII-Management Interface Timing .................................................................................................8-11
POWER on Reset Timming ...........................................................................................................8-12
10Base-T SQE(Heartbeat) Timing .................................................................................................8-13
10Base-T Jabber Timing ................................................................................................................8-14
10Base-T Normal Link Pulse Timing ..............................................................................................8-15
Auto- Negotiation And Fast Link Pulse Timing ...............................................................................8-16
Section 9 Application Notes
NIC Applications .....................................................................................................................................9-1
KS9820 MAC Ethernet Controller Application ...............................................................................9-1
Section 10 Mechanical Data
Package Dimension ................................................................................................................................10-1
Section 11 Appendix
Glossary ..................................................................................................................................................11-1
Ethernet and Networking Acronyms and Terms ............................................................................11-1

PRELIMINARY SPECIFICATION
xKS8910 100/10 Mbps ETHERNET CONTROLLER
List of Figures
Figure Number Title Page Number
1-1 KS8910 PHY Transceiver (64-QFP-1414 Package) .........................................................1-1
1-2 Ethernet System Overview Diagram with Emphasis on MDI .............................................1-3
1-3 100/10 Mbps Ethernet Transceiver Block Diagram ...........................................................1-3
2-1 External Signals .................................................................................................................2-2
2-2 KS8910 Pin Assignments ..................................................................................................2-3
3-1 Functional Block Diagram of KS8910 ................................................................................3-1
3-2 100Base-TX Digital Block of KS8910.................................................................................3-3
3-3 Analog Blocks of KS8910 ..................................................................................................3-5
4-1 100Base-TX Operational Block Diagram of KS8910 .........................................................4-3
4-2 PCS Functional Block Diagram of KS8910 .......................................................................4-4
4-3 4B/5B Encoder (Transmit) State Diagram of KS8910 .......................................................4-7
4-4 5B/4B Decoder (Receive) State Diagram of KS8910 ........................................................4-8
4-5 Linear Feedback Shift Register (LFSR) .............................................................................4-10
4-6 Scrambler Function of KS8910 ..........................................................................................4-10
4-7 Descramble Function of KS8910 .......................................................................................4-11
4-8 Link Monitor State Diagram of KS8910 .............................................................................4-12
4-9 NRZ to NRZI Conversion of KS8910 .................................................................................4-13
5-1 State Diagram of Jabber Control Function ........................................................................5-2
5-2 SQE Function ....................................................................................................................5-3
5-3 State Diagram of Collision Detection Function ..................................................................5-4
5-4 State Diagram of Link Integrity Test Function ...................................................................5-5
6-1 100Mbit/s Data Path Block Diagram of KS8910 ................................................................6-1
6-2 Analog Blocks of KS8910 ..................................................................................................6-2
6-3 Crystal Oscillator Connection ............................................................................................6-3
6-4 Transmit Twister-Pair Driver and Transmit Transformer ...................................................6-5
6-5 Receive Buffer Circuit Configuration .................................................................................6-6
8-1 Clock Frequency Timing Diagram .....................................................................................8-5
8-2 MII-Transmit Clock Tolerance Timing Diagram .................................................................8-5
8-3 MII-Receive Clock Tolerance Timing Diagram ..................................................................8-6
8-4 MII/10Base-T Transmit Timing Diagram ............................................................................8-7
8-5 MII/10Base-T Receive Timing Diagram .............................................................................8-8
8-6 MII/100Base-TX Transmit Timing Diagram .......................................................................8-9
8-7 MII/100Base-TX Receive Timing Diagram ........................................................................8-10
8-8 MII-Management Interface Timing Diagram ......................................................................8-11
8-9 Power On Reset Timming Diagram ...................................................................................8-12
8-10 10Base-T (SQE)Heartbeat Timing Diagram ......................................................................8-13
8-11 10Base-T Jabber Timing Diagram .....................................................................................8-14
8-12 10Base-T Normal Link Pulse Timing Diagram ..................................................................8-15
8-13 Auto-Negotiation and Fast Link Pulse Timing Diagram .....................................................8-16
9-1 KS8910 (64-QFP-1414) Schematic Diagram with KS8920 ...............................................9-1
10-1 KS8910 Package Dimension (64-QFP-1414) Type ...........................................................10-1

PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER xi
List of Tables
Table Number Title Page Number
2-1 KS8910 Signal Descriptions ..............................................................................................2-4
4-1 4B/5B Coding of KS8910 ..................................................................................................4-5
4-2 5B/4B Outputs....................................................................................................................4-6
6-1 Transmit Clocks Generated by the Frequency Synthesizer ..............................................6-4
7-1 Address Mapping ..............................................................................................................7-2
8-1 Absolute Maximum Ratings (TA = 25 °C) ..........................................................................8-2
8-2 Recommended Operating Conditions ...............................................................................8-2
8-3 MII Pads Specification .......................................................................................................8-3
8-4 100Base-TX Transceiver Specification .............................................................................8-3
8-5 10Base-T Transceiver Specification .................................................................................8-4
8-6 Clock Frequency ...............................................................................................................8-5
8-7 MII-Transmit Clock Tolerance ...........................................................................................8-5
8-8 MII-Receive Clock Tolerance ............................................................................................8-6
8-9 MII/10Base-T Transmit Timing ..........................................................................................8-7
8-10 MII/10Base-T Receive Timing ...........................................................................................8-8
8-11 MII/100Base-TX Transmit Timing .....................................................................................8-9
8-12 MII/100Base-TX ReceiveTiming .......................................................................................8-10
8-13 MII-Management Interface Timing ....................................................................................8-11
8-14 10Base-T SQE(Heartbeat) Timing ....................................................................................8-13
8-15 10Base-T Jabber Timing ...................................................................................................8-14
8-16 10Base-T Normal Link Pulse Timing .................................................................................8-15
8-17 10Base-T Jabber Timing ...................................................................................................8-16

KS8910 100/10 Mbps ETHERNET TRANSCEIVER PRODUCT OVERVIEW
1-1
Preliminary Spec. ver 1.4
1 PRODUCT OVERVIEW
INTRODUCTION
The KS8910 10Base-T/100Base-TX Ethernet transceiver is fully compliant with the IEEE 802.3u specification,
provides configurable 100Mbs support for Category 5 unshielded twisted pair (UTP) and supports 10Mbs operation
on Category 3 UTP or Category 5 UTP. The transceiver provides an electrical interface between the Media
Independent Interface (MII) of the Media Access Controller (MAC) and the physical wire pair, and includes support
for the basic and extended register set of station management registers.
The Transceiver provides compatibility with full-duplex Ethernet and Fast Ethernet networks making it suitable for
applications such as switched hubs. Advanced features include Auto-Negotiation for enabling automatic
configuration of network characteristics as well as automatic power-down mode for reduced power consumption.
Functions provided by the transceiver include encoding and decoding of the serial data stream and delimiters, level
conversion, collision detection, signal quality error and link integrity testing, jabber control, and loopback testing.
The device also provides outputs for receive, transmit, collision, speed and link test LEDs.
The new 100-Mbit/s implementation of Ethernet increases the capacity of a network by a factor of ten while using
existing twisted-pair wiring. By maintaining the Media Access Control (MAC) layer and the CSMA/CD protocol
unchanged, network administrators can quickly deploy newer and faster implementations. This approach also
lowers cost of deployment since it allows re-use of existing software applications while supporting both 100- and
10-Mbit/s speeds, and new products may be deployed into transition markets.
Ordering Information
Applications
•10BASE-T/100BASE-TX Network-ready PCs Interface, 10/100 Switches, Switched hubs
Figure 1-1. KS8910 PHY Transceiver (64-QFP-1414 Package)
Device Package Operating Temperature
KS8910 64-QFP-1414 From 0 °C to + 70 °C

PRODUCT OVERVIEW KS8910 100/10 Mbps ETHERNET TRANSCEIVER
1-2
Preliminary Spec. ver 1.4
FEATURES
•Support for old and new media : Compatible with existing 10-Mbit/s networks.
•10BASE-T/100-BASE-TX operation : Range of price/performance points, Phased Conversion
•Full IEEE 802.3 compatibility : Compatible with existing hardware and software.
•Standard CSMA/CD,Full duplex capability at 10 and 100 Mbit/s : Increase in data throughput performance.
•Power management : Reduces power dissipation
•CMOS process with Single 3.3 volt operating supply : Compatible with standard system power supplies.
•On-chip filtering : Providing integrated lower cost solution
•Manual or automatic negotiation of port configuration : Provides ease of use in a mixed 10/100 Mbit/s network
configuration
•MII compliant interface : Can be used with many 100Base-TX MACs.
•Built-in transmit and receive filtering for 10BASE-T and 100BASE-TX
•Built-in LED drivers
ETHERNET SYSTEM BLOCK DIAGRAM
The complete Ethernet subsystem shown in Figure1-2 is divided into three sections:
•The system bus interface and Direct Memory Access (DMA) engine
•The Media Access Control (MAC) layer
•The Physical or Medium Dependent Interface (MDI) layer
The PCI bus interface section contains transmit and receive data buffering, DMA control buffering, and a register
access module buffering.
The MAC layer consists of transmit and receive blocks, a Content Addressable Memory (CAM) for address
recognition, along with control, status, and error counter registers.
This representative PCI-based 100/10-Mbit/s Ethernet controller supports the Media Independent Interface (MII).
The MII is a standard for a media-independent layer which separates physical-layer issues from the MAC layer.
The MII is part of the ISO approved IEEE 802.3 100-Base-T standard for 100 Mbit/s Ethernet.
This specification describes a single chip which implements a Physical or MDI layer capable of accepting 100/10
Mbit/s Ethernet signals that provides a Media Independent Interface (MII) for connectivity to the MAC layer. It is
intended as an interface specification and an architectural overview of the device and its operation.

KS8910 100/10 Mbps ETHERNET TRANSCEIVER PRODUCT OVERVIEW
1-3
Preliminary Spec. ver 1.4
ETHERNET 10BASE-T AND 100BASE-TX BLOCK DIAGRAM
Figure 1-2. Ethernet System Overview Diagram with Emphasis on MDI
Figure 1-3. 100/10 Mbps Ethernet Transceiver Block Diagram
Processor Transformer
MII 10Base-T
100Base-TX
P
C
I
B
U
S
10/100Mbps
PHY
10/100Mbps
MAC
KS8920 KS8910
Auto-Negotiation 20MHz
Link Status
Link Control
+
TX
-
MI
Station
MGM
Interface Control
Registers Status Registers Power Management Auto-neg
Arbitration
10 Base-T
10/20MHz
Fast Ethernet
100 Base-TX
25MHz/125MHz
Mll Data Interface
Driver
MLT3
Driver
100RX
10RX
Registers
+
RX
-
TX
RX
MDC
MDIO
20MHz
4
4

PRODUCT OVERVIEW KS8910 100/10 Mbps ETHERNET TRANSCEIVER
1-4
Preliminary Spec. ver 1.4
REFERENCE DOCUMENTS
Supplement to ANSI/IEEE Std 802.3, 1993 Edition. Supplement to Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) Access Method & Physical Layer Specifications: “MAC Parameters, Physical Layer, Medium
Attachment Units and Repeater for 100 Mb/s Operation”
Document # 802.3u / D5.3. June 14, 1995. This document has been approved, and is being submitted for
publication. This document has also been submitted and approved as an ISO/IEC standard.
International Standard ISO/IEC 8802-3: 1993(E), ANSI/IEEE Std 802.3. information technology--Local and
metropolitan area networks--Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access
method and physical layer specifications: Fourth Edition, July 8, 1993.
FDDI Twisted Pair Physical Layer Medium Dependent (TP-PMD). ANSI T12/94-X3T9.5/93-TP-PMD/312 Rev 2.1.
March, 1994.

KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS
2-1
Preliminary Spec. ver 1.4
2 EXTERNAL SIGNALS
OVERVIEW
Figure2-1 shows the 44 external signals for the 10/100 Mbit/s Ethernet Physical Layer Transceiver, divided into
functional groups. Power and ground pins need to be added to this signal list. The device will require a 64 pin
package. This chapter groups the signal definitions by functional area, giving each signal’s symbolic name, full
name, type, and a brief definition. The groups are:
•pins for MII Transmit
•pins for MII Receive
•pins for MII Station Management
•pins for Twisted-Pair Interface
•pins for Analog Pins
•pins for LED Indicators
•pins for Control Signals

EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
2-2
Preliminary Spec. ver 1.4
EXTERNAL SIGNALS
Figure 2-1. External Signals
Transmit
Media
Independent
Interface(MII)
LED
Interface
Col
Receive
Media
Independent
Interface(MII)
MII
Management
Twisted
Pair
Interface
Analog Pins
Controls
Tx_clk
TxD[3:0]
Tx_en
Tx_er
CrS
Rx_clk
RxD[3:0]
Rx_DV
Rx_er
MDC
MDIO
LEDL
LEDT
LEDR
LEDS
LEDC
TPOP
TPON
TPOB
TPIP
TPIN
XTAL_OUT
XTAL_IN
RB
SP_SEL
FDUPL
RESET
AN_EN
PD

KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS
2-3
Preliminary Spec. ver 1.4
PIN ASSIGNMENTS
Figure 2-2. KS8910 Pin Assignments
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSSDIG
VDDDIG
LEDC[ID4]
LEDL[ID3]
LEDT[ID2]
LEDR[ID1]
LEDS[ID0]
FDPLX
VSSIO
VDDIO
XTAL_OUT
XTAL_IN
VSSTXA
VDDTXA VSSTXQ
VDDTXQ
TPIP
TPIN
SUBANA
SP_SEL
VDDREF
VSSREF
RB
RBGND
AN_EN
TPON
VSSDRV
TPOP
SUBDRV
TPOB
VDDDRV
VSSDRV
Rx_DV
Rx_clk
Rx_er
Tx_er
Tx_clk
SUBDIG
SUBIO
VSSIO
VDDIO
Tx_en
TxD0
TxD1
TxD2
TxD3
Col
CrS
VSSDIG VDDDIG RxD0 RxD1 RxD2 RxD3 MDC MDIO VSSIO VDDIO VSSRXA VDDRXA PD VSSRXQ VDDRXQ RESET
KS8910
64QFP-1414
Top View
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16

EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
2-4
Preliminary Spec. ver 1.4
SIGNAL DESCRIPTIONS
Table 2-1. KS8910 Signal Descriptions
Signal Pin Number I/O Description
MEDIA INDEPENDENT INTERFACE (MII) SIGNALS
The MII is the interface between the 10/100 Mbit/s Ethernet Transceiver and a Media Access Control (MAC)
device. MII is a nibble-wide interface clocked at either 2.5MHz or 25MHz. The Transceiver side MII interface
supplies both the transmit and receive clocks.
Transmit MII Signals
The next sub-table shows the MII signals supported by the 10/100Mbit/s Ethernet Transceiver for transmitting
data packets. For a detailed description of these signals, see the MII sections of the IEEE 802.3u documents listed
in the reference document section
Col 63 O
5T
t/s
Collision :
Asserted asynchronously with minimum delay from the start of a collision
on the medium.
Tx_clk 53 O
5T
t/s
Transmit clock :
TxD[3:0] and Tx_en are driven off the rising edge of the Tx_clk by the
MAC, and sampled by the Transceiver on the rising edge of the Tx_clk.
TxD[3:0] 62,61,60,59 I
5T
PD
Transmit data :
Transmit data is aligned on nibble boundaries. TxD[0] corresponds to the
first bit to transmit on the physical medium and is the LSB of the first byte,
followed by the fifth bit of that byte during the next clock.
Tx_en 58 I
5T
PD
Transmit enable :
Tx_en provides precise framing for the data carried on TxD[3:0]. It is active
during the clock periods that TxD[3:0] contains valid data to be transmitted,
from preamble through CRC.
Tx_er 52 I
5T
PD
Transmit coding error :
Tx_er is driven synchronously to Tx_clk and is sampled continuously by
the Transceiver. If asserted for one or more Tx_clk periods, it causes the
Transceiver to emit one or more symbols which are not part of the valid
data or delimiter set somewhere in the frame being transmitted.
Receive MII Signals
The next sub-table shows the MII signals supported by the 10/100Mbit/s Ethernet Transceiver for receiving data
RX_CLK packets. For a detailed description of these signals, see the MII sections of the IEEE 802.3u standard
listed in the reference document section.
CrS 64 O
5T
t/s
Carrier sense :
Asserted asynchronously with minimum delay from the detection of a non-
idle medium.

KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS
2-5
Preliminary Spec. ver 1.4
Signal Pin Number I/O Description
Rx_clk 50 O
5T
t/s
Receive clock :
Rx_clk is a continuous clock. In 4-bit mode, its frequency is 25 MHz for
100Mbit/s operation, and 2.5 MHz for 10Mbit/s. RXD[3:0], Rx_DV, and
Rx_er are driven by the Transceiver off the falling edge of Rx_clk, and
sampled on the rising edge of Rx_clk.
RxD[3:0] 46,45,44,43 O
5T
t/s
Receive data :
RxD is aligned on nibble boundaries. RxD[0] corresponds to the first bit
received on the physical medium which is the LSB of the byte in one clock
period and the fifth bit of that byte in the next clock.
Rx_DV 49 O
5T
t/s
Receive data valid :
PHY asserts Rx_DV synchronously and holds it active during the clock
periods that RxD[3:0] contains valid received data. The Transceiver
asserts Rx_DV no later than the clock period when it places the first
nibble of the start frame delimiter (SFD) on RxD[3:0]. If the Transceiver
asserts Rx_DV prior to the first nibble of the SFD, then RxD[3:0] carries
valid preamble symbols.
Rx_er 51 O
5T
t/s
Receive error :
PHY asserts Rx_er synchronously whenever it detects a physical medium
error, e.g., a coding violation. The Transceiver asserts Rx_er only when it
asserts Rx_DV.
MII Station Management Signals
The next sub-table shows the two MII station management signals. Use of these signals for configuring the
transceiver or negotiating a link protocol is optional.
MDC 42 I
5T
PD
Management Data Clock :
The timing reference for transfer of information on the MDIO signal. With
the PCI clock at 33 MHz, the MDC clock has a maximum clock frequency
of 33/14 = 2.36 MHz. The minimum clock period is 424 ns.
MDIO 41 I/O
5T
t/s
PD
Management Data I/O :
MDIO transfers control and status management data from the attached
MAC. MDIO Transmits status information from the PHY to the MAC.
LED INTERFACE
These signals allow connection of LEDs to monitor the status of the Transceiver. The next sub-table shows a
summary of the LED signals generated by the Transceiver.
LEDC[D4] 3
I/O
5T
t/s
Collision Indicator /Device ID4:
Pulled low for 10ms when a collision is detected. Otherwise LEDC is high
LEDL[D3] 4Link Integrity Indicator /Device ID3:
Pulled low during link test pass
LEDT[D2] 5Transmit Indicator /Device ID2:
Table 2-1. KS8910 Signal Descriptions

EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
2-6
Preliminary Spec. ver 1.4
Signal Pin Number I/O Description
LEDR[D1] 6
I/O
5T
t/s
Receive Indicator /Device ID1:
LEDS[D0] 7Speed Indicator /Device ID0:
Pulled low when 100Mbit/s operation is in affect either by manual
selection or after Arbitration. Pulled high when 10Mbit/s operation is in
affect and during Auto-Negotiation.
ANALOG PINS
The next sub-table shows the signals needed to support the analog circuitry in the Transceiver.
XTAL_OUT 11 OOscillator Input/Output :
A ±50ppm 25 MHz oscillator is connected between these two pins. This
oscillator is used to time the 10Mbit/s transmitter and as a reference for the
clock recovery of both the 10Mbit/s and 100Mbit/s serial data. A frequency
synthesizer uses this crystal reference to produce the 100Mbit/s transmit
clock(125MHz).
XTAL_IN 12 I
TWISTED PAIR INTERFACE
The next sub-table lists the signals used to send and receive 100Mbit/s data on twisted pairs.
TPOP 21 OTPOP/TPON :
Differential driver outputs to the cable magnetics. The on-chip driver circuit
automatically switches between 10Mbit/s and 100Mbit/s operation.
TPON 23 O
TPIP 32 ITPIP/TPIN :
Differential receiver inputs from the cable magnetics.
TPIN 31 I
TPOB 19 OProvides a bias for the transmit transformer center tap. This bias is about
2.6 volts and should be connected with the Capacitor on GND.
CONTROL SIGNALS
The next sub-table shows the control signals. These control signals select various modes of operation of the
Transceiver
AN_EN 24 5T
PU Enables autonegotiation of operation speed.
SP_SEL 29 100/10 Mbit/s is sampled at the negation of the RESET signal. A high level
on this input selects 100Mbit/s operation. A low level selects 10Mbit/s.
When undriven, this input will float high setting the default operation to
100Mbit/s.
RESET 33 Master reset for the Transceiver. Resets all digital logic and some analog
circuits.This Reset is an active Low.
PD 36 5T
PD Power Down Mode
FDPLX 8Enables full duplex operation.
Table 2-1. KS8910 Signal Descriptions

KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS
2-7
Preliminary Spec. ver 1.4
NOTES:
1.t/s: (sustained)tri-state, 5T: 5V Tolerance,
2.PD: Pull Down, PU: Pull Up
3.P: Power Supply
4.G: Ground
Signal Pin Number I/O Description
Power and Ground Signals
VDDDIG 2,47 P3.3V Power Supply for Digital Internal Block
VDDIO 10,39,57 P3.3V Power Supply for Digital I/O Block
VDDTXA 14 P3.3V Power Supply for Analog Block
VDDRXA 37 P3.3V Power Supply for Analog Block
VDDREF 28 P3.3V Power Supply for Analog Reference Block
VDDTXQ 16 P3.3V Power Supply for Analog Block
VDDRXQ 34 P3.3V Power Supply for Analog Block
VDDDRV 18 P3.3V Power Supply for Analog Driver Block
VSSDIG 1,48 GGround for Digital Internal Block
VSSIO 9,40,56 GGround for for Digital I/O Block
VSSTXA 13 GGround for for Analog Block
VSSRXA 38 GGround for for Analog Block
VSSREF 27 GGround for for Analog Reference Block
VSSTXQ 15 GGround for for Analog Block
VSSRXQ 35 GGround for for Analog Blcok
VSSDRV 17,22 GGround for for Analog Driver Block
SUBIO 55 GBulk Ground for Digital I/O Block
SUBDIG 54 GBulk Ground for Digital Internal Block
SUBANA 30 GBulk Ground for Analog Block
SUBDRV 20 GBulk Ground for Analog Driver Block
RBGND 25 GReference Ground
RB 26 Reference Bias Resistor
Table 2-1. KS8910 Signal Descriptions