Sanken SLA7070MPRT Series User guide

SANKEN ELECTRIC CO., LTD.
http://www.sanken-ele.co.jp/en/
SLA7070MPRT Series Unipolar 2-Phase
Stepper Motor Driver ICs
Application Information
SLA7070MPRT-AN, Rev. 2.1
General Description
This document describes the SLA7070MPRT series,
which are unipolar 2-phase stepping motor driver ICs. The
SLA7070MPRT series employs a clock input method as
a control signal input method, enabling full control of the
device operation using only a few signal lines, instead of
the conventional phase input method that requires about 10
signal lines. This allows simplification of the circuit design
and a reduced workload on the control microprocessor.
In addition, the SLA7070MPRT series is improved in its
reliability by preventing the IC from damage due to abnor-
mal conditions. For example, it has a flag output terminal
to signal that a protection circuit has operated. The series
also has a built-in protection circuitry against motor coil
opens/shorts and thermal shutdown protection as well.
All the SLA7070MPRT series ICs are compatible in their
pin layouts and interface specifications, allowing custom-
ers the flexibility of choosing the IC that is optimal for the
target equipment characteristics.
Features and Benefits
• Power supply voltages, VBB : 46 V (max.), 10 to 44 V
normal operating range
• Logic supply voltages, VDD : 3.0 to 5.5 V
• Maximum output currents: 1 A, 1.5 A, 2 A, 3 A
• Built-in sequencer
• Full-, half-, and microstepping available (microstepping
options are capable of full-, half-, quarter-, eighth-, and
sixteenth-stepping
Figure 1. SLA7070MPRT packages are fully molded ZIPs with an
exposed pad for heatsink mounting.
The SLA7070MPRT series product variants and optional features
Part Number Stepping
Rate
Output Current
(IOUT)
(A)
Input Clock
Edge Detection
Blanking Time
(µs)
Standard Standard
SLA7070MPRT
Full and
half step
1
Rising (positive)
edge 3.2
SLA7071MPRT 1.5
SLA7072MPRT 2
SLA7073MPRT 3
SLA7075MPRT
Microstep
1
Rising (positive)
edge 1.7
SLA7076MPRT 1.5
SLA7077MPRT 2
SLA7078MPRT 3
• Built-in sense resistor, RSInt
• All variants are pin-compatible for enhanced
design flexibility
• ZIP type 23-pin molded package (SLA package)
• Self-excitation PWM current control with fixed off-time
(microstepping options off-time adjusted automatically by
step reference current ratio; 3 levels)
• Built-in synchronous rectifying circuit reduces losses at
PWM-off
• Synchronous PWM chopping function prevents motor
noise in Hold mode
• Sleep mode for reducing the IC input current in
stand-by state
• Built-in protection circuitry against motor coil
opens/shorts and thermal shutdown protection options
Applications
• LBPs, PPCs, ATMs, industrial robots, and so forth
January 10, 2013

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Table of Contents
Specifications 3
Functional Block Diagrams 3
Pin Descriptions 3
Package Outline Drawing 5
Electrical Characteristics 6
Allowable Power Dissipation 10
Typical Application 11
Device Logic 12
Pin Logic and Timing 12
Common Input Pins 12
Monitor Output Pin 12
Logic Input Pins 13
Clock Edge Timing 13
Reset Release and Clock Input Timing 13
Logic Level Change 13
Stepping Sequence Diagrams 14
Motor Excitation Sequencing 21
Individual Circuit Descriptions 22
Monolithic IC (MIC) 22
Output MOSFET Chip 22
Sense Resistor 22
Functional Description 23
PWM Current Control 23
Blanking Time 23
PWM Off-Time 26
Protection Functions 27
Application Information 29
Motor Current Ratio Setting (R1, R2, RS) 29
Lower Limit of Control Current 29
Avalanche Energy 29
On-Off Sequence of Power Supply (VBB
and VDD) 30
Motor Supply Voltage (VM) and Main Power
Supply Voltage (VBB) 31
Internal Logic Circuits 31
Reset 31
Clock Input 31
Chopping Synchronous Circuit 31
Output Disable (Sleep1 and Sleep2) Circuits 31
Ref/Sleep1 Pin 32
Logic Input Pins 32
Thermal Design Information 32
Characteristic Data 34

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Functional Block Diagrams
SLA7070MPRT to SLA7073MPRT: Full and Half step
Sequencer
and
Sleep Circuit
Synchro
Control
PWM
Control
OSC
Comp
+
-
DAC
Pre-
Driver
PWM
Control
OSC
DAC
Pre-
Driver
+
-
MIC
SLA707xMPRT
Reg.
OutA OutA OutA OutA OutB OutB OutB
OutB
V
DD
Ref/Sleep1
Flag
N.C.
M1
M2 M3
CW/CCW
Clock
Reset
V
BB
SenseBSenseA
GndSync
Rs Rs
1 2 3 4
5
6 7 8 9 10 11
12
1314 1516
17
18
19
20 21 22 23
Protect Protect
TSD
Comp
Pin Number. Symbol Function
1, 2 OutA Output of phase A
3, 4 ¯ O
¯
¯
u
¯ ¯
t
¯ ¯
A
¯ Output of phase A ¯
5 SenseA Phase A current sensing
6 N.C. No connection
7 M1
Commutation and Sleep2 setting8 M2
9 M3
10 Clock Step clock input
11 VBB Main power supply (for motor)
12 Gnd Ground
13 Ref/Sleep1 Input for control current and Sleep1 setting
14 VDD Power supply to logic
15 Reset Reset for internal logic
16 CW/CCW Forward/reverse switch input
17 Sync Synchronous PWM control switch input
18 Flag Output from protection circuits monitor
19 SenseB Phase B current sensing
20, 21 ¯ O
¯
¯
u
¯ ¯
t
¯ ¯
B
¯ Output of phase B ¯
22, 23 OutB Output of phase B
1357911 13 15 17 19 21 23
2 4 6 8 10 12 14 16 18 20 22
Pad Side

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Sequencer
and
Sleep Circuit
Synchro
Control
PWM
Control
OSC
+
-
DAC
Pre-
Driver
PWM
Control
OSC
DAC
Pre-
Driver
+
-
Reg.
OutA OutA OutA OutA OutB OutB OutB
OutB
V
DD
Ref/Sleep1
Flag
MO
M1 M2 M3
Clock
Reset
V
BB
SenseBSenseA
GndSync
Rs Rs
1 2 3 4
5
6 7 8 9 10 11
12
1314 1516
17
18
19
20 21 22 23
Protect Protect
TSD
CW/CCW
Comp Comp
MIC
SLA707xMPRT
SLA7075MPRT to SLA7078MPRT: Microstep
Pin Number. Symbol Function
1, 2 OutA Output of phase A
3, 4 ¯ O
¯
¯
u
¯ ¯
t
¯ ¯
A
¯ Output of phase A ¯
5 SenseA Phase A current sensing
6 MO2-phase commutation status monitor output
7 M1
Commutation and Sleep2 setting8 M2
9 M3
10 Clock Step clock input
11 VBB Main power supply (for motor)
12 Gnd Ground
13 Ref/Sleep1 Input for control current and Sleep1 setting
14 VDD Power supply to logic
15 Reset Reset for internal logic
16 CW/CCW Forward/reverse switch input
17 Sync Synchronous PWM control switch input
18 Flag Output from protection circuits monitor
19 SenseB Phase B current sensing
20, 21 ¯ O
¯
¯
u
¯ ¯
t
¯ ¯
B
¯ Output of phase A ¯
22, 23 OutB Output of phase B
1357911 13 15 17 19 21 23
2 4 6 8 10 12 14 16 18 20 22
Pad Side

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Leadframe plating Pb-free. Device composition
includes high-temperature solder (Pb >85%),
which is exempted from the RoHS directive.
1.7 ±0.1
4.8 ±0.2
16.4 ±0.2
31 ±0.2
24.4 ±0.2
φ3.2 ±0.15
12.9 ±0.2
0.65 +0.2
-0.1
16 ±0.2
9.9 ±0.2
4-(R1)
5 ±0.5
0.55+0.2
-0.1
9.5 +1
-0.5
4.5
22 × P1.27±0.5 = 27.94±1
±0.7
R-end
31.3 ±0.2
1234 10 115 678912 13
14
15
16
17
18
19
20
21
22
23
(Includes Mold Flash)
2.45 ±0.2
(Measured at
Base of Pins)
(Measured at Pin Tips)
Unit: mm
Pin material: Cu
Pin Plating: Solder plating (Pb free)
a: Item name 1: SLA707xMRT (x is 0 to 3, or 5 to 8; last digit
of part number, corresponding to current rating and stepping rate)
b: Item name 2: P
c: Lot number:
1st letter is last digit of year
2nd letter is month
January to September: 1 to 9
October: O
November: N
December: D
3rd and 4th are date of manufacture (01 to 31)
(Measured at
Pin Tips)
(Heatsink Pad)
Gate Flash
Japan
a
bc
(4.3)
φ3.2 ±0.15 x 3.8
Package Outline Drawing, SLA 23-Pin

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Recommended Operating Conditions Unless specifically noted, TA is 25°C
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Load (Motor Supply) Voltage VM– – 44 V
Main Power Supply Voltage VBB 10 – 44 V
Logic Supply Voltage VDD
Surge voltage at VDD pin should
be less than ±0.5 V to avoid
malfunctioning in operation
3.0 – 5.5 V
Case Temperature TcMeasured at pin 12, without
heatsink – – 90 °C
Electrical Characteristics
• This section provides separate sets of electrical characteristic data for each product.
• The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC.
• Please refer to the datasheet of each product for additional details.
Absolute Maximum Ratings Unless specifically noted, TA is 25°C
Characteristic Symbol Notes Rating Unit
Load (Motor Supply) Voltage VM46 V
Main Power Supply Voltage VBB 46 V
Logic Supply Voltage VDD
6 V
≤1μs(5%duty) 7 V
Output Current IO
SLA7070MPRT
SLA7075MPRT
Control current value
1.0 A
SLA7071MPRT
SLA7076MPRT 1.5 A
SLA7072MPRT
SLA7077MPRT 2.0 A
SLA7073MPRT
SLA7078MPRT 3.0 A
Logic Input Voltage VIN −0.3toVDD+0.3 V
REF Input Voltage VREF −0.3toVDD+0.3 V
Sense Voltage VRS ±2 V
Power Dissipation PDWithout heatsink 4.7 W
Junction Temperature TJ150 °C

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Electrical Characteristics Common to All Variants Unless specifically noted, TA is 25°C
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Main Power Supply Current IBB Normal mode – – 15 mA
IBBS Sleep1 and Sleep2 mode – – 100 μA
Logic Power Current IDD – – 5 mA
MOSFET Breakdown Voltage VDSS VBB = 44 V, ID = 1 mA 100 – – V
Maximum Response Frequency fclk Clockduty=50% 250 – – KHz
Logic Supply Voltage VIL – – 0.25 × VDD V
VIH 0.75 × VDD – – V
Logic Supply Current IIL – ±1 – μA
IIH – ±1 – μA
REF Input Voltage1VREF See figure 1 – – – V
VREFS Output off, Sleep1 mode 2.0 – VDD V
REF Input Current IREF – ±10 – μA
SENSE Voltage VSENSE VREF = 0 to 1.5 V
Stepreferencecurrentratio:100%
VREF –
0.03 –VREF – 0.03 V
Sleep to Enable Recovery Time tSE Sleep1 and Sleep2 100 – – μs
Switching Time tcon Clock edge to output on – 2.0 – μs
tcoff Clock edge to output off – 1.5 – μs
Overcurrent Detection Voltage2VOCP At motor coil short-circuit 0.65 0.7 0.75 V
Overcurrent Detection Current
( VOCP / RS )IOCP
SLA7070MPRT, SLA7075MPRT,
SLA7071MPRT, SLA7076MPRT – 2.3 – A
SLA7072MPRT, SLA7077MPRT – 3.5 – A
SLA7073MPRT, SLA7078MPRT – 4.6 – A
Load Disconnection Undetected Time topp From PWM off – 2 – µs
Overheat Protection Temperature Ttsd Measured at back of device case (after heat
has saturated) – 140 – °C
Flag Output Voltage
VFlagL IFlagL = 1.25 mA – – 1.25 V
VFlagH IFlagH = –1.25 mA VDD –
1.25 – – V
Flag Output Current IFlagL – – 1.25 mA
IFlagH –1.25 – – mA
1In a state of: Sleep1, IBBS, output off, and Sequencer enabled.
2In a condition of VSENSE ≥ VOCP , the protection circuit will activate.

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Electrical Characteristics Varying with Stepping Sequence Unless specifically noted, TA is 25°C, VBB = 24 V, VDD = 5 V
SLA7070MPRT, SLA7071MPRT, SLA7072MPRT, and SLA7073MPRT (Full- and Half-Stepping)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Step Reference Current Ratio Mode F VREF≈VSENSE = 100 V,
VREF = 0 to 1.0 V
– 100 – %
Mode 8 – 70 – %
PWM Minimum On-Time ton(min) – 3.2 – µs
PWM Off-Time toff – 12 – µs
SLA7075MPRT, SLA7076MPRT, SLA7077MPRT, and SLA7078MPRT (Microstepping)
Step Reference Current Ratio
Mode F
VREF≈VSENSE = 100 V,
VREF = 0 to 1.0 V
– 100 – %
Mode E – 98.1 – %
Mode D – 95.7 – %
Mode C – 92.4 – %
Mode B – 88.2 – %
Mode A – 83.1 – %
Mode 9 – 77.3 – %
Mode 8 – 70.7 – %
Mode 7 – 63.4 – %
Mode 6 – 55.5 – %
Mode 5 – 47.1 – %
Mode 4 – 38.2 – %
Mode 3 – 29 – %
Mode 2 – 19.5 – %
Mode 1 – 9.8 – %
MO (Load) Output Voltage VMOL IMOL = 1.25 mA – – 1.25 V
VMOH IMOH = –1.25 mA VDD – 1.25 – – V
MO (Load) Output Current IMOL – – 1.25 mA
IMOH –1.25 – – mA
PWM Minimum On-Time ton(min) – 1.7 – µs
PWM Off-Time
toff1 Mode 8, 9, A, B, C, D, E, and F – 12 – µs
toff2 Mode 4, 5, 6, and 7 – 9 – µs
toff3 Mode 1, 2, and 3 – 7 – µs

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Electrical Characteristics Varying with Output Current Range Unless specifically noted, TA is 25°C, VBB = 24 V, VDD = 5 V
SLA7070MPRT and SLA7075MPRT (IO= 1.0 A)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Output On-Resistance RDS(on) ID = 1 A – 0.7 0.85 Ω
Body Diode Forward Voltage VfIf = 1 A – 0.85 1.1 V
Sense Resistor* RS±3%tolerance 0.296 0.305 0.314 Ω
REF Input Voltage VREF Within specified current limit, IO = 1.0 A 0.04 – 0.3 V
SLA7071MPRT and SLA7076MPRT (IO= 1.5 A)
Output On-Resistance RDS(on) ID = 1.5 A – 0.45 0.6 Ω
Body Diode Forward Voltage VfIf = 1.5 A – 1.0 1.25 V
Sense Resistor* RS±3%tolerance 0.296 0.305 0.314 Ω
REF Input Voltage VREF Within specified current limit, IO = 1.5 A 0.04 – 0.45 V
SLA7072MPRT and SLA7077MPRT (IO= 2.0 A) Electrical Characteristics
Output On-Resistance RDS(on) ID = 2 A – 0.25 0.4 Ω
Body Diode Forward Voltage VfIf = 2 A – 0.95 1.2 V
Sense Resistor* RS±3%tolerance 0.199 0.205 0.211 Ω
REF Input Voltage VREF Within specified current limit, IO = 2.0 A 0.04 – 0.4 V
SLA7073MPRT and SLA7078MPRT (IO= 3.0 A) Electrical Characteristics
Output On-Resistance RDS(on) ID = 3 A – 0.18 0.24 Ω
Body Diode Forward Voltage VfIf = 3 A – 0.95 2.1 V
Sense Resistor* RS±3%tolerance 0.150 0.155 0.160 Ω
REF Input Voltage VREF Within specified current limit, IO = 3.0 A 0.04 – 0.45 V
*Includestheinherentbulkresistance(approximately5mΩ)oftheresistoritself.

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
V
OCP= 0.7 V
0.3V
VDD
0V
2.0V
Sleep
Prohibition Zone
1 Set Range
0.4V
0.45V
1.0 A
Devices 2.0 A Devices 1.5 A and 3.0 A
Devices
Motor Current Set Range*
*Motor Current Set Range is determined
by the value of the resistor built into the device.
Figure 1. Reference Voltage Setting (VREF, REF/SLEEP1 Pin). Please pay extra
attention to the change-over between the motor current specification range, IMO , and
the Sleep1 Set Range. VOCP falls on the "prohibition zone" threshold. If the change-
over time is too slow, OCP operation will start when VSInt > VOCP.
Rθj-a
=
26.6℃/W
0
1
2
3
4
5
0 10 20 30 40 50 60 70 80 90
Ambient Temperature, T
A
[℃]
Allowable Power Dissipation, P
D[W]
Figure 2. Allowable Power Dissipation

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
SLA7075MPRT
SLA7076MPRT
SLA7077MPRT
SLA7078MPRT
VBBOutA OutA OutBOutB
VDD
Clock
Sync
CW/CCW
Ref/Sleep
Sense B
Sense AGnd
R1
R3R2
Sleep
Q1
CA
CB
Vs=10 to 44 V
VCC =3.0 5to .5V
Logic Gnd Power Gnd
Pin12
Gnd
Reset/Sleep1
M1
M2
M3
Mo
Flag
C1
C2
Micro-
controller
Typical Application
(Microstepper Variants)
External Component Typical Values
(for reference use only):
Component Value Component Value
R1 10kΩ CA 100μF/50V
R2 1kΩ(varistor) CB 10μF/10V
R3 10kΩ C1 0.1μF
• Take precautions to avoid noise on the VDD line; noise
levels greater than 0.5 V on the VDD line may cause device
malfunction. Noise can be reduced by separating the logic
ground and the power ground on a PCB from the GND pin
(pin 12).
• Unused logic input pins (CW / CCW, M1, M2, M3, Reset,
and SYNC) must be pulled up or down to VDD or ground. If
those unused pins are left open, the device malfunctions.
• Unused logic output pins (Mo, Flag) must be kept open.
Figure 3. Typical Application Circuit

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Truth Tables
Common Input Pins
Table 1 shows the truth table for input pins common to both
half/full step and microstep variants of the SLA7070MPRT
series.
• The Reset function is asynchronous. If the input on the Reset
pin is high, the internal logic circuit is reset. At this point, if the
Ref pin stays low, then the DMOS outputs turn on at the starting
point of excitation. Note that the Disable control functions are not
available with the Reset pin signal set high.
• Voltage at the Ref / Sleep1 pin controls the PWM current and
the Sleep1 function. For normal operation, VREF should be below
1.5 V (low level). Applying a voltage greater than 2.0 V (high
level) to the Ref / Sleep1 pin disables the outputs and puts the
motor in a free state (coast). This function is used to minimize
power consumption when the device is not in use. Although
it disables much of the internal circuitry, including the out-
put MOSFETs and regulator, the sequencer / translator circuit
remains active.
• The Sync function is active only for 2-phase excitation timing.
If this function is used during other than 2-phase excitation tim-
ing, the overall stepping sequence might collapse because PWM
off-time and set current are different in each phase A and phase
B control scenario. (2-phase excitation timing is when the step
reference current ratio of both phase A and phase B is Mode 8.)
Commutation/Sleep2 Function
Table 2 shows the logic of the pins (M1, M2, and M3) which set
commutation. In the Sleep2 function, the outputs are disabled and
the driver supply current (IBB) is reduced. However, unlike the
Sleep1 function, the logic circuitry is put into a standby state and
therefore the sequencer / translator circuit is not active.
Note: When awakening from Sleep2 mode, a delay of 100 μs or
longer before sending a Clock pulse is recommended.
Monitor Output Pin
The SLA7070MPRT series provides two device status monitor
outputs:
• Flag pin – Protection feature operation
• Mo pin (microstep variants only) – Stepping sequence
Table 3 shows the logic for the monitor pins. The outputs turn off
when the protection circuit starts operating. To release the protec-
tion state, cycle (set low, and then high) the logic supply voltage
(VDD).
Table 1. Truth Table for Common Input Pins (Half/Full and Microstep)
Pin Name Low Level High Level Clock
Reset Normal operation Logic reset
(Positive Edge)
CW/CCW Forward (CW) Reverse (CCW)
M1, M2, M3 Commutation (Sleep2 is not included)
Ref / Sleep1 Normal operation Sleep1 function
Sync Non-sync PWM control Sync PWM control
Table 2. Commutation-Sleep2 Truth Table for
Common Input Pins (Half/Full and Microstep)
Pin Name Full / Half Step Microstep
M1 M2 M3
LLLFull step (Mode 8 fixed) Full step (Mode 8 fixed)
H L L Full step (Mode F fixed) Full step (Mode F fixed)
L H L Half step Half step
H H L Half step (Mode F fixed) Half step (Mode F fixed)
L L H
Sleep2 function
Quarter step
H L H Eighth step
L H H Sixteenth step
H H H Sleep2 function
Table 3. Monitor Output Pins Logic
Pin Name Low Level High Level
Flag Normal operation Protection circuit operation
Mo Other than 2-phase
excitation timing 2-phase excitation timing

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure4.InputSignalTiming.WhenawakeningfromSleep1orSleep2mode,adelayof100μsor
longer before sending a Clock pulse is recommended.
Reset 2 µs(min)
2 µs(min)
2 µs(min)
2 µs(min)
1 µs(min) 1 µs(min)
1 µs(min) 1 µs(min)
2 µs(min)
5 µs(min) 4 µs(min)
Clock
CW/CCW
M1, M2, M3
Logic Input Pins
The low pass filter incorporated with the logic input pins (Reset,
Clock, CW/CCW, M1, M2, M3, and Sync) improves noise rejec-
tion. The logic inputs are CMOS input compatible, and therefore
they are in a high impedance state. Use the IC at a fixed input
level, either low or high.
Input Logic Timing
Clock Signal
A low-to-high then high-to-low transition on the Clock input
advances the sequencer / translator. The Clock pulse width should
be set at 2 μs in both positive and negative polarities. Therefore,
clock response frequency should be 250 kHz. Only the positive
edge is used for timing, however, it is necessary to control the
logic levels of the Clock signal both before and after each Clock
signal edge sent to the sequencer logic circuit, in order to main-
tain proper stepping operation.
Clock Edge Timing
With regard to the input logic of the CW/CCW, M1, M2, and M3
pins, a 1 μs delay should occur both before and after the pulse
edges and as setup and hold times. The sequencer logic circuitry
might malfunction if the logic polarity is changed during these
setup and hold times. (Refer to figure 4).
Reset Release and Clock Input Timing
The Reset pulse width is equivalent to the high pulse level hold
time. It should be greater than the 2 μs Clock input pulse width.
When the timing of a Reset release (falling edge) and a Clock
edge is simultaneous, the internal logic might cause an unex-
pected operation. Therefore, a greater than 5 μs delay is required
between the falling edge of the Reset input and the next rising
edge of the Clock input. (Refer to figure 4).
Logic Level Change
Logic level inputs on CW/CCW, M1, M2, and M3 set the transla-
tor step direction (CW/CCW) and step mode (M1, M2, and M3;
refer to the Commutation Truth Table). Changes to these inputs
do not take effect until the rising edge of the Clock input. How-
ever, depending on the type and state of a motor, there may be
errors in motor operation. A thorough evaluation on the changes
of sequence should be carried out.

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 5. Full step; for microstep and full/half step products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Full Step
8Low Low Low
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.
A
B
B
A
012
70.7
0
70.7
0
…
RESET
CLOCK
CW
CCW
Stepping Sequence Diagrams

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SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 6. Full step; for microstep and full/half step products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Full Step
FHigh Low Low
0 1 2
…
R E S ET
C LO C K
AA
1
0
0
B
CCW
B
C W
00
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.

16
SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 7. Half step; for microstep and full/half step products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Half Step
8, F Low High Low
A
B
B
A
0 1 2 3 4
100
70.7
0
70.7
0
…
RESET
CLOCK
CW
CCW
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.

17
SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 8. Half step; for microstep and full/half step products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Half Step
FHigh High Low
A
B
B
A
0 1 2 3 4
100
0
0
…
RESET
CLOCK
CW
CCW
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.

18
SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 9. Quarter step; for microstep products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Quarter
Step Low Low High
A
B
B
A
0 1 2 3 4 5 6 7 ８
92.4
100
70.7
38.2
0
70.7 38.2
0
92.4
…
RESET
CLOCK
CW
CCW

19
SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 10. Eighth step; for microstep products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Eighth
Step High Low High
A
B
B
A
0 1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
98.1
92.4
100
98.1
83.1
70.7
55.5
38.2
19.5
0
83.1 70.7 55.5 38.2 19.5
0
92.4
…
RESET
CLOCK
CW
CCW
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.

20
SANKEN ELECTRIC CO., LTD.
SLA7070MPRT-AN, Rev. 2.1
Figure 11. Sixteenth step; for microstep products
Sequence Selection
Mode Pin Logic
M1 M2 M3
Sixteenth
Step Low High High
A
B
B
A
98.1
92.4 95.7
100
98.1 95.7
88.2
83.1
77.3
70.7
63.4
55.5
47.1
38.2
29.0
19.5
9.8
0
88.2 83.1 77.3 70.7 63.4 55.5 47.1 38.2 29.0 19.5
9.8
0
92.4
CW
CCW
10 2 3 4 65 7 8 9 1
0
1
1
1
2
1
3
1
5
1
4
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
…
RESET
CLOCK
Shows the state to which the stepping sequence progresses at the rising
(positive) edge of the Clock input.