Scenix SX18AC User manual

SX User’s Manual Rev. 1.0 2© 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Scenix™
SX18AC/SX20AC/SX28AC
User’s Manual

© 1998 Scenix Semiconductor, Inc. All rights reserved. 3SX User’sManual Rev. 1.0
www.scenix.com
Revision History
©1998 Scenix Semiconductor, Inc. All rights reserved. No warranty is provided and no liability is
assumed by Scenix Semiconductor with respect to the accuracy of this documentation or the
merchantability orfitnessof theproduct for a particular application. Nolicense of any kind is conveyed
by Scenix Semiconductor with respect to its intellectual property or that of others. All information in
this document is subject to change without notice.
Scenix Semiconductor products are not authorized for use in life support systems or under conditions
where failure of the product would endanger the life or safety of the user, except when prior written
approval is obtained from Scenix Semiconductor.
Scenix™ and the Scenix logo are trademarks of Scenix Semiconductor, Inc.
I2C™ is a trademark of PhilipsCorporation
PIC® is a registered trademark of Microchip Technology, Inc.
Microchip® is a registered trademark of Microchip Technology, Inc.
SX-Key™ is a trademark of Parallax, Inc.
Microwire™ is a trademark of National Semiconductor Corporation
All other trademarks mentioned in this document are property of their respective companies.
Scenix Semiconductor, Inc., 3160 De la Cruz Boulevard, Suite 200, Santa Clara,CA 95054 USA
Telephone: [phone], Web site: hhtp://www.scenix.com
REVISION RELEASEDATE SUMMARY OF CHANGES
1.0 October 16, 1998 First Release

SX User’s Manual Rev. 1.0 4© 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Contents
Chapter 1 Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.6 Programming and Debugging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8 Part Numbers and Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Architecture
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.1 W (Working Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.2 FSR (Indirect through FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.3 RTCC (Real-Time Clock/Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.4 PC (Program Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.5 STATUS (Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.6 FSR (File Select Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.7 RA, RB, and RC (Port Data Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.8 Port Control Registers and MODE Register . . . . . . . . . . . . . . . . . . . . . . 27
2.4.9 OPTION (Device Option Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Instruction Execution Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.2 Pipeline Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.3 Read-Modify-Write Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.1 Test and Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 Jump Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.3 Jump Indirect and Jump Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.4 Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.5 Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.7 Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.8 Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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Chapter 3 Instruction Set
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.3 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.1 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.2 Arithmetic and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.3 Bitwise Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.4 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.5 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.6 System Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 Equivalent Assembler Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7 Detailed Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7.1 ADD fr,W Add W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.7.2 ADD W,fr Add fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.7.3 AND fr,W AND of fr and W into fr . . . . . . . . . . . . . . . . . . . 58
3.7.4 AND W,fr AND ofW and fr into W . . . . . . . . . . . . . . . . . . . 59
3.7.5 AND W,#lit AND ofW and Literal into W . . . . . . . . . . . . . . . 60
3.7.6 BANK addr8 Load Bank Number into FSR(7:5) . . . . . . . . . . . . 61
3.7.7 CALL addr8 Call Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.7.8 CLR fr Clear fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.7.9 CLR W Clear W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.7.10 CLR !WDT Clear Watchdog Timer . . . . . . . . . . . . . . . . . . . . . 66
3.7.11 CLRB fr,bit Clear Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.7.12 DEC fr Decrement fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7.13 DECSZ fr Decrement fr and Skip if Zero . . . . . . . . . . . . . . . 69
3.7.14 INC fr Increment fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7.15 INCSZ fr Increment fr and Skip if Zero . . . . . . . . . . . . . . . 71
3.7.16 IREAD Read Word from Instruction Memory . . . . . . . . . 72
3.7.17 JMP addr9 Jump to Address . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.7.18 MOV fr,W Move W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.7.19 MOV M,#lit Move Literal to MODE Register . . . . . . . . . . . . . 76
3.7.20 MOV M,W Move W to MODE Register . . . . . . . . . . . . . . . . 77
3.7.21 MOV !OPTION,W Move W to OPTION Register . . . . . . . . . . . . . . . 78
3.7.22 MOV !rx,W Move W to Port Rx Control Register . . . . . . . . . 79
3.7.23 MOV W,fr Move fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.7.24 MOV W,/fr Move Complement of fr to W . . . . . . . . . . . . . . . 82
3.7.25 MOV W,fr-W Move (fr-W) to W . . . . . . . . . . . . . . . . . . . . . . . . 83
3.7.26 MOV W,--fr Move (fr-1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.7.27 MOV W,++fr Move (fr+1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.28 MOV W,<<fr Rotate fr Left through Carry and Move to W . . . 86
3.7.29 MOV W,>>fr Rotate fr Right through Carry and Move to W . . 87
3.7.30 MOV W,<>fr Swap High/Low Nibbles of fr and Move to W . . 88

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3.7.31 MOV W,#lit Move Literal to W . . . . . . . . . . . . . . . . . . . . . . . . 89
3.7.32 MOV W,M Move MODE Register to W . . . . . . . . . . . . . . . . 90
3.7.33 MOVSZ W, --fr Move (fr-1) to W and Skip if Zero . . . . . . . . . . . 91
3.7.34 MOVSZ W, ++fr Move (fr+1) to W and Skip if Zero . . . . . . . . . . . 92
3.7.35 NOP No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.7.36 NOT fr Complement of fr into fr . . . . . . . . . . . . . . . . . . . 94
3.7.37 OR fr,W OR of fr and W into fr . . . . . . . . . . . . . . . . . . . . . 95
3.7.38 OR W,fr OR of W and fr into W . . . . . . . . . . . . . . . . . . . . 96
3.7.39 OR W,#lit OR of W and Literal into W . . . . . . . . . . . . . . . . 97
3.7.40 PAGE addr12 Load Page Number into STATUS(7:5) . . . . . . . . 98
3.7.41 RET Return from Subroutine . . . . . . . . . . . . . . . . . . . . 99
3.7.42 RETI Return from Interrupt . . . . . . . . . . . . . . . . . . . . . 100
3.7.43 RETIW Return from Interrupt and Adjust RTCCwith W 101
3.7.44 RETP Return from Subroutine Across Page Boundary 102
3.7.45 RETW lit Return from Subroutine withLiteral in W . . . . . 103
3.7.46 RL fr Rotate fr Left through Carry . . . . . . . . . . . . . . . 104
3.7.47 RR fr Rotate fr Right through Carry . . . . . . . . . . . . . . 105
3.7.48 SB fr,bit Test Bit in fr and Skip if Set . . . . . . . . . . . . . . . 106
3.7.49 SETB fr,bit Set Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.7.50 SLEEP Power Down Mode . . . . . . . . . . . . . . . . . . . . . . 108
3.7.51 SNB fr,bit Test Bit in fr and Skip if Clear . . . . . . . . . . . . . . 109
3.7.52 SUB fr,W Subtract W from fr . . . . . . . . . . . . . . . . . . . . . . . 110
3.7.53 SWAP Swap High/Low Nibbles of fr . . . . . . . . . . . . . . 112
3.7.54 TEST fr Test fr for Zero . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.7.55 XOR fr,W XOR of fr and W into fr . . . . . . . . . . . . . . . . . . . 114
3.7.56 XOR W,fr XOR of W and fr into W . . . . . . . . . . . . . . . . . . 115
3.7.57 XOR W,#lit XOR of W and Literal into W . . . . . . . . . . . . . . 116
Chapter 4 Clocking, Power Down, and Reset
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.2 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.2.1 Clock/Instruction Rate Option (Compatible or Turbo Mode) . . . . . . . . 117
4.2.2 Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.2.3 External RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.2.4 External Crystal/Resonator (XT, LP, or HS Mode) . . . . . . . . . . . . . . . . 119
4.2.5 External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3.1 Entering the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3.2 Waking Up from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 123
4.4 Multi-Input Wakeup/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.1 Port B Configuration for Multi-Input Wakeup/Interrupt . . . . . . . . . . . . 123
4.4.2 Reading the Wakeup Pending Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5.1 Register States Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.5.2 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.3 Wakeup from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.5.4 Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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4.5.5 Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.5.6 MCLR Input Signal (Master Clear Reset) . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 5 Input/Output Ports
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2 Reading and Writing thePorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.1 Accessing the Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.2 MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.3 Port Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.4 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.5 Port Configuration Upon Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.6 Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Chapter 6 Timers and Interrupts
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2 Real-Time Clock/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2.1 Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2.2 Maximum Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.2.3 RTCC Operation as a Real-Time Clock or Timer . . . . . . . . . . . . . . . . . 139
6.2.4 RTCC Operation as an Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.2.5 RTCC Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.1 Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.2 Watchdog Operation in the Power Down Mode . . . . . . . . . . . . . . . . . . 141
6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.4.1 Single-Level Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.4.2 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.4.3 RTCC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.4.4 Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.4.5 Return-from-Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.4.6 Interrupt Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 7 Analog Comparator
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.2 Comparator Enable/Status Register (CMP_B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.2.1 Accessing the CMP_B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.3 Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 8 Device Programming
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.1.1 Erasure and Reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8.1.2 Standard and Custom Programming Tools . . . . . . . . . . . . . . . . . . . . . . 149
8.1.3 In-System and Parallel Programming Modes . . . . . . . . . . . . . . . . . . . . 149

SX User’s Manual Rev. 1.0 8© 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comContents
8.2 In-System Programming (ISP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.2.1 Scenix In-System Programming Implementation . . . . . . . . . . . . . . . . . 150
8.2.2 Entering the ISP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.2.3 Programming in ISP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.2.4 Exiting the ISP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.3 Parallel Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.3.1 Parallel Programming Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.3.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8.3.3 Erasing theMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

SX User’s Manual Rev. 1.0 9© 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comContents
List of Figures
Figure 1-1 Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1-2 Part Numbering Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2-1 SX28AC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2-2 Program Counter Loading for Jump Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 2-3 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 2-4 Stack Operation for a “Call” Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2-5 Stack Operation for a “Return” Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2-6 Device Configuration Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3-1 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 4-1 External RC Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 4-2 Crystal or Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-3 External Clock Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 4-5 On-Chip Reset Circuit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 4-6 Power-On Reset Timing, Fast VDD Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 4-7 Power-On Reset Timing, VDD Rise Time Too Slow . . . . . . . . . . . . . . . . . . . . 129
Figure 4-8 External Power-On MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 4-9 Power-On Reset Timing, Separate MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 5-1 Port B Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 6-1 RTCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 6-2 Interrupt Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 7-1 Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 8-1 ISP Mode Entry with External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 8-2 ISP Mode Entry with the Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 8-3 ISP Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 8-4 ISP Circuit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 8-5 Erase Timing in Parallel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 8-6 Read Timing in Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 8-7 Program Timing in Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

© 1998 Scenix Semiconductor, Inc. All rights reserved. 10 SX User’sManual Rev. 1.0
www.scenix.com Contents
List of Tables
Table 1-1 Device Package Names ...............................................................................................15
Table 1-2 Pin Descriptio n .........................................................................................................18
Table 2-1 RAM Register Map ....................................................................................................21
Table 2-2 Register Summary ......................................................................................................23
Table 2-3 STATUS Register Bits ................................................................................................25
Table 2-4 MODE Register Settings ............................................................................................28
Table 2-5 Prescaler Divide-By Factors ......................................................................................29
Table 2-6 Pipeline Execution Sequence ......................................................................................30
Table 2-7 Return-from-Subroutine/Interrupt Instructions ...........................................................36
Table 2-8 FUSE Word Register Configuration Bits ..................................................................39
Table 2-9 FUSEX Word Register Configuration Bits ................................................................40
Table 2-10 DEVICE Word Register Configuration Bits (Read-Only) .........................................41
Table 3-1 Logic Instructions .......................................................................................................49
Table 3-2 Arithmetic and Shift Instructions (Sheet 1 of 2) .........................................................49
Table 3-3 Bitwise Operation Instructions ...................................................................................50
Table 3-4 Data Movement Instructions (Sheet 1 of 2) ................................................................50
Table 3-5 Program Control Instructions ......................................................................................52
Table 3-6 System Control Instructio n .......................................................................................52
Table 3-7 Equivalent Assembler Mnemonics .............................................................................53
Table 3-8 Key to Abbreviations and Symbols ...........................................................................55
Table 4-1 Clock Modes and Component Values (Murata Ceramic Resonators) ......................121
Table 4-2 Clock Modes and Component Values (Crystal Oscillators) .....................................121
Table 4-3 Register States Upon Reset .......................................................................................127
Table 5-1 MODE Register and Port Control Register Access ..................................................133
Table 6-1 Watchdog Timeout Settings ......................................................................................141
Table 8-1 ISP Commands .........................................................................................................155
Table 8-2 ISP Commands .........................................................................................................159

SX User’s Manual Rev. 1.0 11 © 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Chapter 1
Overview
1.1 Introduction
The Scenix SX18AC, SX20AC, and SX28AC are members of the SX family of high-performance 8-
bit microcontrollers fabricated with an advanced CMOS process technology. The advanced process,
combined with a RISC-based architecture, allows high-speed computation, flexible I/O control, and
efficient data manipulation. Throughput is enhanced by operating the device at frequencies up to 50
MHz and by optimizing the instruction set to include mostly single-cycle instructions.
On-chip functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a
brown-out detector, a watchdog timer, a power-save mode with multi-source wakeup capability, an
internal R/C oscillator, user-selectable clock modes, and high-current outputs.
1.2 Key Features
These are the key features of the SX18AC, SX20AC, and SX28AC devices:
• 50 MIPS performance at 50 MHz oscillator frequency
• 2048 x 12 bits EE/Flash program memory rated for 10,000 rewrite cycles
• 136 x 8 bits SRAM
• In-system programming capability through OSC pins
• User-selectable clock modes using an internal oscillator, external clock signal, or external oscil-
lator (crystal or RC)
• Analog comparator
• Brown-out detector (4.2V, on/off)
• Multi-InputWakeup (MIWU) on eight pins
• Fast lookup capability through run-time readable code
• Complete development tool support available from Parallax, Inc.

© 1998 Scenix Semiconductor, Inc. All rights reserved. 12 SX User’sManual Rev. 1.0
www.scenix.com Chapter 1 Overview
1.3 CPU Features
These are the key features of the device CPU:
• Fully static design – DC to 50 MHz operation
• 20 ns instruction cycle time at 50 MHz
• Mostly single-cycle instructions
• Selectable 8-level deep hardware subroutine stack
• Single-level interrupt processing
• Fixed interrupt response time: 60 ns internal, 100 ns external at 50 MHz
• Hardware context save/restore for interrupt processing
• Designed to be pin-compatible and upwardly code-compatible with the PIC16C5x® microcon-
troller
1.4 I/O Features
These are the key features of the device I/O ports:
• Software-selectable I/O configuration
• Each pin programmable as an input or output
• TTL or CMOS level selection on inputs
• Internal weak pull-up selection on inputs (~20 kΩto VDD)
• Schmitt trigger inputs on Port B and Port C
• All outputs capable of sinking/sourcing 30 mA
• Symmetrical drive on Port A outputs (same Vdrop +/-)
1.5 Architecture
The SX device uses a modified Harvard architecture. This architectureis based on having two separate
memories with separate address buses, one for the program and one for data, while allowing transfer
of data from program memory to SRAM. This ability allows accessing data tables from program
memory. The advantage of this architecture is that instruction fetch and memory transfers can be
overlapped in a multi-stage pipeline, which means the next instructioncan be fetched from program
memory while the current instruction is being executed.

SX User’s Manual Rev. 1.0 13 © 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
The SXfamily implements afour-stagepipeline (fetch,decode, execute, and write back),which results
in a throughput of one instruction per clock cycle. At the maximum operating frequency of 50 MHz,
instructions are executed at the rate of one per 20-ns clock cycle.
1.6 Programming and Debugging Support
The SX devices are currently supported by the SX-Key™ development package offered by Parallax,
Inc. This package provides an integrated development environment including editor, macro assembler,
debugger, and device programmer. The available package components include the SX-Key
programmer/emulator unit, a demonstration board, a prototyping board, a serial interface cable,
development software that runs under Windows 95, and complete documentation.
1.7 Applications
Emerging applications and advances in existing ones require higher performance while maintaining
low cost and fast time-to-market.
The SX devices provide solutionsformanyfamiliar applications such asprocess controllers, electronic
appliances/tools, security/monitoring systems, and personal communication devices. In addition, the
enhanced throughput of the device allows efficient development of software modules called “Virtual
Peripherals” to replace on-chip hardware peripherals. The concept of Virtual Peripherals provides
benefits such as using a more simple device, reduced component count, fast time to market, increased
flexibility in design, and ultimately overall system cost reduction.
Here are some examples of Virtual Peripheral applications:
• Serial, Parallel, I2C™, Microwire™ (µ-Wire), Dallas µ-Wire, SPI, DMX-512, X-10, IR trans-
ceivers
• Frequency generation and measurement
• Spectrum analysis
• Multi-tasking, interrupts, and networking
• Resonance loops
• DRAM drivers
• Music and voice synthesis
• PPM/PWM output
• Delta/Sigma ADC
• DTMF generation/detection
• PSK/FSK generation/detection

© 1998 Scenix Semiconductor, Inc. All rights reserved. 14 SX User’sManual Rev. 1.0
www.scenix.com Chapter 1 Overview
• Quadrature encoder/decoder
• Peripheral Interface Device (PID) and servo control
• Video controller
1.8 Part Numbers and Pinout Diagrams
This user’s guide describes the Scenix SX18AC, SX20AC, and SX28AC microcontrollers, which are
available in the four pin configurations shown in Figure 1-1. All of these devices are functionally the
same, except that the 18-pin and 20-pin devices do not havethe port pins RC0 through RC7. Therefore,
Port C cannot be used in the smaller devices.
Figure 1 -1Device Pin Assignments
SSOP
1
2
3
4
5
6
7
8
16
15
RC4
RC3
RB6
RB5
SX 28-PIN
OSC2
RC7
RC6
RC5
Vdd
Vdd
RA2
RA3
RB0
RB1
RB2
RB3
RB4
Vss
MCLR
OSC1
RC2
RC1
RC0
RB7
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
Vss
RTCC
RA0
RA1
1
2
3
4
5
6
7
8
16
15
RC4
RC3
RB6
RB5
SX 28-PIN
OSC2
RC7
RC6
RC5
n.c.
Vss
RA2
RA3
RB0
RB1
RB2
RB3
RB4
MCLR
OSC1
RC2
RC1
RC0
RB7
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
RTCC
Vdd
RA0
RA1
n.c.
SDIP/SOIC
1
2
3
4
5
6
7
8
16
15
RB5
RB4
SX 20-PIN
OSC2
RTCC RA0
RB0
RB1
RB2
RB3
MCLR OSC1
Vdd
Vdd
RB7
RB6
9
10
14
13
12
11
20
19
18
17
RA2
RA3
Vss
RA1
Vss
SSOP
1
2
3
4
5
6
7
8
16
15
RB5
RB4
SX 18-PIN
OSC2
RTCC RA0
RB0
RB1
RB2
RB3
MCLR OSC1
Vdd
RB7
RB6
910
14
13
12
11
18
17
RA2
RA3 RA1
Vss
SDIP/SOIC

SX User’s Manual Rev. 1.0 15 © 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
Table 1-1 is a list of the available SX device packages and the corresponding number of pins, number
of I/O pins, program (flash) memory size, and general-purpose RAM size. Use this table as a guide for
ordering the parts that fit your requirements.
Figure 1-2 is a diagram showing the general naming conventions for SX family devices. The part
number consists of several fields that specify the manufacturer, pin count, feature set, memory size,
supply voltage, operating temperature range, and package type, as indicated in Figure 1-2.
Throughout this manual, the term “SX” refers to all the devices listed in Table 1-1, except where
indicated otherwise.
Table 1-1 Device Package Names
Device Pins I/O EE/Flash (Words) RAM (Bytes)
SX18AC/SO 18 12 2K 136
SX18AC/DP 18 12 2K 136
SX20AC/SS 20 12 2K 136
SX28AC/SO 28 20 2K 136
SX28AC/DP 28 20 2K 136
SX28AC/SS 28 20 2K 136

© 1998 Scenix Semiconductor, Inc. All rights reserved. 16 SX User’sManual Rev. 1.0
www.scenix.com Chapter 1 Overview
Figure 1-2 Part Numbering Reference Guide
SX18AC-LI/SO
Package Type
Extended Temperature
LowVoltage
Memory Size
Feature Set
Pin Count
SceniX
A = 512 word
B = 1k word
C = 2k word
D = 4k word
E = 8k word
F = 16k word
G = 24k word
H = 32k word
I = 48k word
J = 64k word

SX User’s Manual Rev. 1.0 17 © 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.comChapter 1 Overview
1.9 Pin Descriptions
Table 1-2 describes the SX28AC device pins. For each pin, thetable shows the pin type (input, output,
or power), the input voltage levels (TTL, CMOS, or Schmitt trigger), and the pin function. The
following abbreviations are used in the table:
• I = device input
• O = device output
• I/O = bidirectional I/O pin
• P = power supply pin
• NA = not applicable
• TTL = TTL input levels
• CMOS = CMOS input levels
• ST = Schmitt trigger input
• MIWU = Multi-InputWakeup

© 1998 Scenix Semiconductor, Inc. All rights reserved. 18 SX User’sManual Rev. 1.0
www.scenix.com Chapter 1 Overview
Table 1-2 Pin Descriptions
Name Pin
Type Input Levels Description
RA0 I/O TTL/CMOS Bi-directional I/O Pin; Symmetrical Source / Sink
Capability
RA1 I/O TTL/CMOS Bi-directional I/O Pin; Symmetrical Source / Sink
Capability
RA2 I/O TTL/CMOS Bi-directional I/O Pin; Symmetrical Source / Sink
Capability
RA3 I/O TTL/CMOS Bi-directional I/O Pin; Symmetrical Source / Sink
Capability
RB0 I/O TTL/CMOS/ST Bi-directional I/O Pin; Comparator Output; MIWU
Input
RB1 I/O TTL/CMOS/ST Bi-directional I/O Pin; Comparator Negative Input;
MIWU Input
RB2 I/O TTL/CMOS/ST Bi-directional I/O Pin; Comparator Positive Input;
MIWU Input
RB3 I/O TTL/CMOS/ST Bi-directional I/O Pin; MIWU Input
RB4 I/O TTL/CMOS/ST Bi-directional I/O Pin; MIWU Input
RB5 I/O TTL/CMOS/ST Bi-directional I/O Pin; MIWU Input
RB6 I/O TTL/CMOS/ST Bi-directional I/O Pin; MIWU Input
RB7 I/O TTL/CMOS/ST Bi-directional I/O Pin; MIWU Input
RC0 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC1 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC2 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC3 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC4 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC5 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC6 I/O TTL/CMOS/ST Bi-directional I/O Pin
RC7 I/O TTL/CMOS/ST Bi-directional I/O Pin
RTCC I ST Input to Real Time Clock/Counter
MCLR I ST Master Clear Reset Input – Active Low
OSC1/In/Vpp I ST Crystal Oscillator Input - External Clock Source Input
OSC2/Out O CMOS Crystal Oscillator Output – in R/C mode, internally
pulled to Vdd through weak pullup
Vdd P NA Positive Supply Pin
Vss P NA Ground Pin

SX User’s Manual Rev. 1.0 19 © 1998 Scenix Semiconductor, Inc. All rights reserved.
www.scenix.com
Chapter 2
Architecture
2.1 Introduction
The SX28AC is a complete 8-bit RISC microcontroller with an electrically erasable (flash) program
memory and in-system programming capability. The device can operate with a clock rate of up to 50
MHz andcan execute instructions at a rate of up to50million instructions per second.
The SX28AC device has three multi-pin I/O ports, an internal oscillator, a Watchdog timer, a Real-
Time Clock/Counter, an analog comparator, power-on and brownout reset control, and Multi-Input
Wakeup capability. Figure 2-1 is a block diagram of the device. The SX18AC and SX20AC have the
same features, except that they have two rather than three I/O ports.
The SX device uses a modified Harvard architecture, in which the program and data are stored in
separate memory spaces. The advantage of this architecture is that instruction fetches and data
transfers can be overlapped with a multi-stage pipeline, which means the next instruction can be
Figure 2 -1SX28AC Block Diagram
Prescaler for RTCC
Postscaler for WDT
or Interrupt
MIWU
Port B Comp
Power-On
Reset RESET
8-bit Watchdog
Timer (WDT) 8-bit Timer
RTCC
888
Port C
8
8
Port A
8
4
Internal Data Bus
In-System
Debugging
In-System
Programming
2k x 12
EEPROM
System
Clock
Brown-Out MIWU
MCLR
OSC
Driver
4MHz
Internal
RC OSC
Clock
Select
÷4 or ÷1
136 Bytes
SRAM
Address
Write Data
Read Data
Instruction
W
FSR
STATUS
PC
MODE
OPTION
System Clock
OSC1 OSC2
Instruction Pipeline
Four - Stage
8812
Address 12
8
8
88
ALU
8
83
RTCC
Analog
88

© 1998 Scenix Semiconductor, Inc. All rights reserved. 20 SX User’sManual Rev. 1.0
www.scenix.com Chapter 2 Architecture
fetched from program memory while the current instruction is being executed uses data from the data
memory. This device has a “modified” Harvard architecture because instructions are available for
transferringdata from the program memory to the data memory.
2.2 Program Memory
The program memory holds the application program for the device. It is an electrically erasable, flash-
programmed memory containing 2,048 words of 12 bits per word. Each memory location holds a
single 12-bit instruction opcode or 12 bits of fixed data that can be accessed by the program. The
memory can be programmed and reprogrammed through the device oscillator pins, even with the
device installed in the target system.
The program memory is addressed by the program counter, an11-bitregister. Operation of the program
counter is described in detail in Section .
2.3 Data Memory
The data memory is a RAM-based register set consisting of 136 general-purpose registers andeight
dedicated-purpose registers. All of these registers are eight bits wide. The registers are organized into
eight banks, designated Bank 0 through Bank 7. This organization allows the SX instructions to
address the registers using just five bits of the 12-bit instruction opcode.
Because the registers are organized into banks or “files,” these memory-mapped registers are called
“file registers.” In the descriptions of the SX instructions inChapter 3, the abbreviation “fr” represents
a 5-bit register address encoded into the instruction opcode.
2.3.1 Banks
The SX devicecan be programmed to use any one of the eight banks atany given time. The three high-
order bits in the File Select Register (FSR) specify the current bank number. To change from one bank
to another, the program can either write an eight-bit value to the FSR register or use the “bank”
instruction. The “bank” instruction writes the three bank-selection bits in the FSR register without
affecting the other bits in the register. Bank 0 is selected by default upon power-up or reset.
Within each bank, there are 32 available addresses, ranging from 00h to 1Fh. Table 2-1 shows the
organization of file registersin the memory-mapped address space. The numbers along the left sidethe
table (ranging from $00 to $1F) show the 32 possible register addresses that can be specified an
instruction. The bank numbers listed across the top (ranging from 0 to 7) are the numbers that can be
programmed into the three high-order bits of the FSR register. The entries inside the table shows the
registers accessed by each combination of register address and bank selection.
The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX
assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the
table, the register addresses are shown as 8-bit hexadecimal values.