Cmsemicon CMS80F731 Series User manual

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CMS80F731x Reference Manual
CMS80F731x Series
Reference Manual
Enhanced flash 8-bit 1T 8051 microcontroller
Rev. 1.00
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CMS80F731x Reference Manual
Table of Content
CMS80F731x Series .................................................................................................................2
Table of Content.......................................................................................................................3
1. Central Processing Unit (CPU) .......................................................................................12
1.1 Reset Vector (0000H)................................................................................................................................................12
1.2 BOOT Partition ..........................................................................................................................................................12
1.3 Accumulator (ACC) ...................................................................................................................................................14
1.4 B Register(B).............................................................................................................................................................14
1.5 Stack Pointer Register (SP).......................................................................................................................................14
1.6 Data Pointer Register (DPTR0/DPTR1) ....................................................................................................................14
1.7 Data Pointer Selection Register (DPS)......................................................................................................................15
1.8 Program Status Register (PSW)................................................................................................................................15
1.9 Program Counter (PC) ..............................................................................................................................................16
1.10 Timing Access Register (TA) .....................................................................................................................................16
2. Memory and Register Mapping.......................................................................................17
2.1 Program Storage Flash .............................................................................................................................................17
2.2 Non-volatile Data Memory Data FLASH....................................................................................................................18
2.3 General Purpose Data Memory RAM........................................................................................................................18
2.4 General External Data Register XRAM .....................................................................................................................20
2.5 Special Function Register SFR .................................................................................................................................21
2.6 External Special Function Register XSFR.................................................................................................................22
3. Reset.................................................................................................................................29
3.1 Power-on Reset.........................................................................................................................................................29
3.2 External Reset...........................................................................................................................................................31
3.3 LVR Low-voltage Reset .............................................................................................................................................31
3.4 Watchdog Reset........................................................................................................................................................32
3.5 Software Reset..........................................................................................................................................................32
3.6 CONFIG Status Protection Reset..............................................................................................................................33
3.7 Power-on Configuration Monitor Reset .....................................................................................................................33
4. Clock Structure ................................................................................................................34
4.1 System Clock Structure.............................................................................................................................................34
4.2 Related Registers......................................................................................................................................................35
4.2.1 Oscillator Control Register CLKDIV ......................................................................................................................35
4.2.2 System Clock Switching Register SCKSEL...........................................................................................................35
4.2.3 System Clock Status Register SCKSTAU .............................................................................................................36
4.2.4 System Clock Monitor Register SCM ....................................................................................................................37
4.2.5 Function Clock Control Registers..........................................................................................................................38
4.3 System Clock Switching ............................................................................................................................................39
4.4 System Clock Monitoring...........................................................................................................................................40
5. Power Management .........................................................................................................41
5.1 Power Management Register PCON.........................................................................................................................41
5.2 Power Supply Monitor Register LVDCON .................................................................................................................42
5.3 IDLE Idle Mode..........................................................................................................................................................42
5.4 STOP Sleep Mode.....................................................................................................................................................43
5.4.1 Sleep Wakes up ....................................................................................................................................................43
5.4.2 Wake-up Wait State...............................................................................................................................................43
5.4.3 Sleep Wake-up Time .............................................................................................................................................43
5.4.4 Reset Operation Under Sleep ...............................................................................................................................44

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5.4.5 Sleep Power Consumption in Debug Mode...........................................................................................................44
5.4.6 Example of a Sleep Mode Application...................................................................................................................44
6. Interrupt ............................................................................................................................45
6.1 Interrupt Overview .....................................................................................................................................................45
6.2 External Interrupts .....................................................................................................................................................46
6.2.1 INT0/INT1 Interrupt ...............................................................................................................................................46
6.2.2 GPIO Interrupt.......................................................................................................................................................46
6.3 Interrupt With Sleep Wake-up ...................................................................................................................................46
6.4 Interrupt Register.......................................................................................................................................................47
6.4.1 Interrupt Mask Registers .......................................................................................................................................47
6.4.1.1 Interrupt Mask Register IE ............................................................................................................................47
6.4.1.2 Interrupt Mask Register EIE2........................................................................................................................48
6.4.1.3 Timer2 Interrupt Mask Register T2IE ............................................................................................................48
6.4.1.4 P0 Interrupt Control Register P0EXTIE.........................................................................................................49
6.4.1.5 Port P1 Interrupt Control Register P1EXTIE .................................................................................................49
6.4.1.6 P2 Interrupt Control Register P2EXTIE.........................................................................................................49
6.4.1.7 P5 Interrupt Control Register P5EXTIE.........................................................................................................50
6.4.2 Interrupt Priority Controls the Register ..................................................................................................................51
6.4.2.1 Interrupt Priority Control Register IP .............................................................................................................51
6.4.2.2 Interrupt Priority Control Register EIP1.........................................................................................................51
6.4.2.3 Interrupt Priority Control Register EIP2.........................................................................................................52
6.4.2.4 Interrupt Priority Control Register EIP3.........................................................................................................53
6.4.3 Interrupt Flag Bit Register .....................................................................................................................................54
6.4.3.1 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON ......................................................................................54
6.4.3.2 Timer2 Interrupt Flag Bit Register T2IF.........................................................................................................54
6.4.3.3 Peripheral Interrupt Flag Bit Register EIF2 ...................................................................................................55
6.4.3.4 SPI Interrupt Flag Bit Register SPSR............................................................................................................56
6.4.3.5 I2C Master Mode Interrupt Flag Registers I2CMCR/I2CMSR .......................................................................56
6.4.3.6 I2C Slave Mode Status Register I2CSSR .....................................................................................................57
6.4.3.7 UART Control Register SCONn....................................................................................................................57
6.4.3.8 P0 port Interrupt Flag Register P0EXTIF ......................................................................................................58
6.4.3.9 Port P1 Interrupt Flag Register P1EXTIF......................................................................................................58
6.4.3.10 P2 Port Interrupt Flag Bit Register P2EXTIF ............................................................................................58
6.4.3.11 P5 Port Interrupt Flag Bit Register P5EXTIF ............................................................................................58
6.4.4 The Clear Operation For the Interrupt Flag Bit ......................................................................................................59
6.4.5 Special Interrupt Flag Bits in Debug Mode............................................................................................................60
7. I/O Port..............................................................................................................................61
7.1 GPIO Function...........................................................................................................................................................61
7.1.1 PORTx Data Register Px ......................................................................................................................................61
7.1.2 PORTx Direction Register PxTRIS........................................................................................................................61
7.1.3 PORTx Open-drain Control Register PxOD ..........................................................................................................62
7.1.4 PORTx pull-up Resistor Control Register PxUP....................................................................................................62
7.1.5 PORTx Pull-down Resistor Control Register PxRD ..............................................................................................62
7.1.6 PORTx Slope Control Register PxSR ...................................................................................................................63
7.1.7 The PORTx Data Input Selects Register PxDS.....................................................................................................63
7.2 Multiplexed Functions................................................................................................................................................64
7.2.1 Port Multiplexing Feature Table.............................................................................................................................64
7.2.2 Port Multiplexing Feature Configuration Register..................................................................................................66
7.2.3 The Port Input Function Allocation Registers ........................................................................................................66
7.2.4 Communication Input Function Allocation Registers .............................................................................................68
7.2.5 Port External Interrupt Control Registers ..............................................................................................................69

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7.2.6 Multiplexing Features Application Notes ...............................................................................................................69
8. Watchdog Timer (WDT) ...................................................................................................71
8.1 Overview ...................................................................................................................................................................71
8.2 Related Registers......................................................................................................................................................71
8.2.1 Watchdog Control Register WDCON ....................................................................................................................71
8.2.2 Watchdog Overflow Control Register CKCON ......................................................................................................72
8.3 WDT Interrupt............................................................................................................................................................73
8.3.1 Interrupt Mask Register EIE2 ................................................................................................................................73
8.3.2 Interrupt Priority Control Register EIP2 .................................................................................................................74
9. Timer Counter 0/1 (Timer0/1) ..........................................................................................75
9.1 Overview ...................................................................................................................................................................75
9.2 Related Registers......................................................................................................................................................76
9.2.1 Timer0/1 Mode Register TMOD ............................................................................................................................76
9.2.2 Timer0/1 Control Register TCON ..........................................................................................................................77
9.2.3 Timer0 Data Register Low Bit TL0 ........................................................................................................................78
9.2.4 Timer0 Data Register High Bit TH0 .......................................................................................................................78
9.2.5 Timer1 Data Register Low Bit TL1 ........................................................................................................................78
9.2.6 Timer1 Data Register High TH1 ............................................................................................................................78
9.2.7 Function Clock Control Register CKCON..............................................................................................................79
9.3 Timer0/1 Interrupt ......................................................................................................................................................80
9.3.1 Interrupt Mask Register IE.....................................................................................................................................80
9.3.2 Interrupt Priority Control Register IP .....................................................................................................................81
9.3.3 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON...............................................................................................82
9.4 Timer0 Working Mode ...............................................................................................................................................83
9.4.1 T0 - Mode 0 (13-bit Timing/Counting Mode)..........................................................................................................83
9.4.2 T0 - Mode 1 (16-bit Timing/Counting Mode)..........................................................................................................83
9.4.3 T0 - Mode 2 (8-bit Auto-reload Timing/Counting Mode) ........................................................................................84
9.4.4 T0 - Mode 3 (Two Separate 8-bit Timers/Counters) ..............................................................................................84
9.5 Timer1 Working Mode ...............................................................................................................................................85
9.5.1 T1 - Mode 0 (13-bit Timing/Counting Mode)..........................................................................................................85
9.5.2 T1 - Mode 1 (16-bit Timing/Counting Mode)..........................................................................................................85
9.5.3 T1 - Mode 2 (8-bit Auto Reload Timing/Counting Mode) .......................................................................................86
9.5.4 T1 - Mode 3 (Stop Count)......................................................................................................................................86
10. Timer Counter 2 (Timer2) ................................................................................................87
10.1 Overview ...................................................................................................................................................................87
10.2 Related Registers......................................................................................................................................................88
10.2.1 Timer2 Control Register T2CON ...........................................................................................................................88
10.2.2 Timer2 Data Register Low bit TL2.........................................................................................................................88
10.2.3 Timer2 Data Register High TH2 ............................................................................................................................89
10.2.4 Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL............................................................................89
10.2.5 Timer2 Compare/Capture/Auto Reload Register High Bit RLDH ..........................................................................89
10.2.6 Timer2 Compares/Captures Channel 1 Register Low Bit CCL1............................................................................89
10.2.7 Timer2 Compares/Captures Channel 1 Register High Bit CCH1 ..........................................................................89
10.2.8 Timer2 Compares/Captures Channel 2 Register Low-bit CCL2............................................................................90
10.2.9 Timer2 Compares/Captures Channel 2 Register High-bit CCH2 ..........................................................................90
10.2.10 Timer2 Compares/Captures Channel 3 Register Low-bit CCL3............................................................................90
10.2.11 Timer2 Compares/Captures Channel 3 Register High-bit CCH3 ..........................................................................90
10.2.12 Timer2 Compares the Capture Control Register CCEN ........................................................................................91
10.3 Timer2 Interrupts .......................................................................................................................................................92
10.3.1 Interrupt Correlation Registers ..............................................................................................................................92
10.3.1.1 Interrupt Mask Register IE ........................................................................................................................92

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10.3.1.2 Timer2 Interrupt Mask Register T2IE ........................................................................................................93
10.3.1.3 Interrupt Priority Control Register IP .........................................................................................................93
10.3.1.4 Timer2 Interrupt Flag Bit Register T2IF.....................................................................................................94
10.3.2 Timer Interrupts .....................................................................................................................................................95
10.3.3 Externally Triggered Interrupts ..............................................................................................................................95
10.3.4 Compare Interrupts ...............................................................................................................................................95
10.3.5 Capture Interrupts .................................................................................................................................................95
10.4 Timer2 Feature Description .......................................................................................................................................96
10.4.1 Timing Mode .........................................................................................................................................................96
10.4.2 Reload Mode.........................................................................................................................................................96
10.4.3 Gated Timing Mode...............................................................................................................................................97
10.4.4 Event Counting Mode............................................................................................................................................97
10.4.5 Compare Mode .....................................................................................................................................................98
10.4.5.1 Compare Mode 0 ......................................................................................................................................98
10.4.5.2 Comparison Mode 1 .................................................................................................................................99
10.4.6 Capture Mode .....................................................................................................................................................100
10.4.6.1 Capture Mode 0......................................................................................................................................100
10.4.6.2 Capture Mode 1......................................................................................................................................101
11. Timer 3/4 (Timer3/4) .......................................................................................................102
11.1 Overview .................................................................................................................................................................102
11.2 Related Registers....................................................................................................................................................102
11.2.1 Timer3/4 Control Register T34MOD....................................................................................................................102
11.2.2 Timer3 Data Register Low Bit TL3 ......................................................................................................................103
11.2.3 Timer3 Data Register High Bit TH3 .....................................................................................................................103
11.2.4 Timer4 Data Register Low Bit TL4 ......................................................................................................................103
11.2.5 Timer4 Data Register High Bit TH4 .....................................................................................................................103
11.3 Timer3/4 Interrupt ....................................................................................................................................................104
11.3.1 Interrupt Mask Register EIE2 ..............................................................................................................................104
11.3.2 Interrupt Priority Control Register EIP2 ...............................................................................................................105
11.3.3 Peripheral Interrupt Flag Bit Register EIF2..........................................................................................................106
11.4 Timer3 Working Mode .............................................................................................................................................107
11.4.1 T3 - Mode 0 (13-bit Timing Mode) .......................................................................................................................107
11.4.2 T3 - Mode 1 (16-bit Timing Mode) .......................................................................................................................107
11.4.3 T3 - Mode 2 (8-bit Auto Reload Timing Mode).....................................................................................................108
11.4.4 T3 - Mode 3 (Two Separate 8-bit Timers)............................................................................................................108
11.5 Timer4 Working Mode .............................................................................................................................................109
11.5.1 T4 - Mode 0 (13-bit Timing Mode) .......................................................................................................................109
11.5.2 T4 - Mode 1 (16-bit Timing Mode) .......................................................................................................................109
11.5.3 T4- Mode 2 (8-bit Auto Reload Timing Mode)......................................................................................................110
11.5.4 T4 - Mode 3 (Stop Count)....................................................................................................................................110
12. LSE Timer(LSE_Timer) .................................................................................................. 111
12.1 Overview ................................................................................................................................................................. 111
12.2 Related Registers.................................................................................................................................................... 111
12.2.1 LSE Timer Data Register Low 8 Bit LSECRL...................................................................................................... 111
12.2.2 LSE Timer Data Registers are 8 Bits High LSECRH........................................................................................... 111
12.2.3 LSE Timer Control Register LSECON .................................................................................................................112
12.3 Interrupt With Sleep Wake-up .................................................................................................................................113
12.4 Feature Description .................................................................................................................................................114
13. Wake-up Timer (WUT).................................................................................................... 115
13.1 Overview .................................................................................................................................................................115
13.2 Related Registers....................................................................................................................................................115

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13.2.1 WUTCRH Register..............................................................................................................................................115
13.2.2 WUTCRL Register...............................................................................................................................................115
13.3 Feature Description .................................................................................................................................................116
14. Baud Rate Timer (BRT).................................................................................................. 117
14.1 Overview .................................................................................................................................................................117
14.2 Related Registers....................................................................................................................................................117
14.2.1 BRT Module Control Register BRTCon...............................................................................................................117
14.2.2 The BRT Timer Data is Loaded With a Low 8-bit Register BRTDL .....................................................................117
14.2.3 The BRT Timer Data is Loaded With a High 8-bit Register BRTDH ....................................................................117
14.3 Feature Description .................................................................................................................................................118
15. Cyclic Redundancy Check Unit (CRC)......................................................................... 119
15.1 Overview .................................................................................................................................................................119
15.2 Related Registers....................................................................................................................................................119
15.2.1 CRC Data Input Register CRCHIN......................................................................................................................119
15.2.2 The CRC Operation Results in a Low 8-bit Data Register, CRCDL ....................................................................119
15.2.3 The CRC Operation Results in a High 8-bit Data Register With CRCDH............................................................119
15.3 Feature Description .................................................................................................................................................120
16. Buzzer Driver (BUZZER)................................................................................................121
16.1 Overview .................................................................................................................................................................121
16.2 Related Registers....................................................................................................................................................121
16.2.1 BUZZER Control Register BUZCON...................................................................................................................121
16.2.2 BUZZER Frequency Control Register BUZDIV ...................................................................................................121
16.3 Feature Description .................................................................................................................................................122
17. PWM Module ..................................................................................................................123
17.1 Overview .................................................................................................................................................................123
17.2 Characteristic ..........................................................................................................................................................123
17.3 Port Configuration ...................................................................................................................................................123
17.4 Feature Description .................................................................................................................................................124
17.4.1 Functional Block Diagram ...................................................................................................................................124
17.4.2 Edge Alignment ...................................................................................................................................................125
17.4.3 Complementary Model ........................................................................................................................................126
17.4.4 Synchronous Mode .............................................................................................................................................127
17.5 PWM-related Registers ...........................................................................................................................................128
17.5.1 PWM Control Register PWMCON.......................................................................................................................128
17.5.2 PWM Output Enable Control Register PWMOE..................................................................................................128
17.5.3 PWM0/1 Clock Prescale Control Register PWM01PSC......................................................................................129
17.5.4 PWM2/3 Clock Prescale Control Register PWM23PSC......................................................................................129
17.5.5 PWM4/5 Clock Prescale Control Register PWM45PSC......................................................................................129
17.5.6 PWM Clock Divide Control Register PWMnDIV (n=0-5) .....................................................................................130
17.5.7 PWM Data Loading Enable Control Register PWMLOADEN..............................................................................130
17.5.8 PWM Output Polarity Control Register PWMPINV..............................................................................................130
17.5.9 PWM Counter Mode Control Register PWMCNTM.............................................................................................131
17.5.10 PWM Counter Enable Control Register PWMCNTE ...........................................................................................131
17.5.11 PWM Counter Mode Control Register PWMCNTCLR.........................................................................................131
17.5.12 PWM Cycle Data Register Low 8 Bits PWMPnL (n=0-5).....................................................................................131
17.5.13 PWM Cycle Data Register High 8 Bits PWMPnH (n=0-5) ...................................................................................132
17.5.14 PWM Compare Data Register Low 8 Bits PWMDnL (n=0-5)...............................................................................132
17.5.15 PWM Compare Data Register High 8 BitS PWMDnH (n=0-5) ............................................................................132
17.5.16 PWM Dead-zone Enable Control Register PWMDTE .........................................................................................132
17.5.17 PWM0/1 Dead-zone Delay Data Register PWM01DT ........................................................................................133

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17.5.18 PWM2/3 Dead-zone Delay Data Register PWM23DT ........................................................................................133
17.5.19 PWM4/5 Dead-zone Delay Data Register PWM45DT ........................................................................................133
17.6 PWM Interrupt .........................................................................................................................................................134
17.6.1 Interrupt Mask Register EIE2 ..............................................................................................................................134
17.6.2 Interrupt Priority Control Register EIP2 ...............................................................................................................135
17.6.3 PWM Zero Interrupt Mask Register PWMZIE......................................................................................................135
17.6.4 PWM Down Compare Interrupt Mask Register PWMDIE....................................................................................136
17.6.5 PWM Zero Interrupt Flag Register PWMZIF .......................................................................................................136
17.6.6 PWM Down Compare Interrupt Flag Register PWMDIF .....................................................................................136
18. Hardware LED Matrix Driver .........................................................................................137
18.1 Overview .................................................................................................................................................................137
18.2 Characteristic ..........................................................................................................................................................137
18.3 Related Registers....................................................................................................................................................137
18.3.1 LED Drive Mode Select Register LEDMODE ......................................................................................................137
18.3.2 LED Control Register LEDCON ..........................................................................................................................138
18.3.3 LED Clock Prescale Data Register Low 8 Bit LEDCLKL.....................................................................................138
18.3.4 LED Clock Prescale Data Register High 8 Bit LEDCLKH ...................................................................................139
18.3.5 COM Port Valid Time Selection Register LEDCOMTIME ....................................................................................139
18.3.6 COM Port Enable Control Register LEDCOMEN ................................................................................................139
18.3.7 SEG Port Enable Control Register LEDSEGEN0................................................................................................139
18.3.8 SEG Port Enable Control Register LEDSEGEN1................................................................................................140
18.3.9 COM0 Corresponding SEG Data Register LEDC0DATAn (n=0-1)......................................................................140
18.3.10 COM1 Corresponding SEG Data Register LEDC1DATAn (n=0-1)......................................................................140
18.3.11 COM2 Corresponding SEG Data Register LEDC2DATAn (n=0-1)......................................................................140
18.3.12 COM3 Corresponding SEG Data Register LEDC3DATAn (n=0-1)......................................................................141
18.3.13 COM4 Corresponding SEG Data Register LEDC4DATAn (n=0-1)......................................................................141
18.3.14 COM5 Corresponding SEG Data Register LEDC5DATAn (n=0-1)......................................................................141
18.3.15 COM6 Corresponding SEG Data Register LEDC6DATAn (n=0-1)......................................................................141
18.3.16 COM7 Corresponding SEG Data Register LEDC7DATAn (n=0-1)......................................................................142
18.3.17 P04-P07 Drive Current Control Register LEDSDRP0H.......................................................................................142
18.3.18 P10-P13 Drive Current Control Register LEDSDRP1L .......................................................................................142
18.3.19 P14-P17 Drive Current Control Register LEDSDRP1H.......................................................................................143
18.3.20 P20-P23 Drive Current Control Register LEDSDRP2L .......................................................................................143
18.3.21 LED Pin Drive Enable Low 8-bit LEDENL ...........................................................................................................144
18.3.22 LED Pin Drive Enable High 8-bit LEDENH..........................................................................................................146
18.3.23 COM Port Sink Current Selection Register P0DR...............................................................................................148
18.4 LED Driver Output Waveform..................................................................................................................................149
19. Hardware LED Dot Matrix Driver ..................................................................................150
19.1 Overview .................................................................................................................................................................150
19.2 Characteristic ..........................................................................................................................................................150
19.3 Feature Description .................................................................................................................................................151
19.4 Related Registers....................................................................................................................................................156
19.4.1 LED Drive Mode Select Register LEDMODE ......................................................................................................156
19.4.2 LED Dot Matrix Drive Controller LEDCON1 ........................................................................................................156
19.4.3 LED Dot Matrix Drive Clock Prescale Register Low 8 Bit LEDCLKL1.................................................................157
19.4.4 LED Dot Matrix Drive Clock Prescale Register High 8 Bits LEDCLKH1..............................................................157
19.4.5 LED Dot Matrix Drive First Stage Configuration Register Higher 8 Bits scan1WH..............................................157
19.4.6 LED Dot Matrix Drive First Stage Configuration Register Low 8 Bits SCAN1WL................................................157
19.4.7 LED Dot Matrix Drives Second Stage Configuration Register High 8 Bits scan2WH ..........................................158
19.4.8 LED Dot Matrix Drive Second Stage Configuration Register Low 8 Bits SCAN2WL...........................................158
19.4.9 LED Dot Matrix Drive Display Data Register LEDnDATA (n=0-7)........................................................................158

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19.4.10 LED Dot Matrix Drive Cycle Select Register LEDnSEL (n=0-7). .........................................................................159
19.4.11 P00-P03 Drive Current Control Register LEDSDRP0L .......................................................................................159
19.4.12 P04-P07 Drive Current Control Register LEDSDRP0H.......................................................................................160
19.4.13 LED Pin Drive Enable Low 8-bit LEDENL ...........................................................................................................160
19.4.14 LED Pin Drive Enable High 8-bit LEDENH..........................................................................................................162
19.5 LED Dot Matrix Drive Interrupt ................................................................................................................................164
19.5.1 LED Dot Matrix Drive Status Register LEDSTATUS............................................................................................164
19.5.2 Interrupt Priority Control Register EIP2 ...............................................................................................................164
20. SPI Module .....................................................................................................................165
20.1 Overview .................................................................................................................................................................165
20.2 SPI Port Configuration.............................................................................................................................................166
20.3 SPI Hardware Description .......................................................................................................................................167
20.4 SPI-related Registers ..............................................................................................................................................169
20.4.1 SPI Control Register SPCR.................................................................................................................................169
20.4.2 SPI Data Register SPDR ....................................................................................................................................169
20.4.3 SPI Device Select Control Register SSCR..........................................................................................................170
20.4.4 SPI Status Register SPSR ..................................................................................................................................170
20.5 SPI Master Mode.....................................................................................................................................................171
20.5.1 Write Conflict Error..............................................................................................................................................172
20.6 SPI Slave Mode.......................................................................................................................................................173
20.6.1 Address Error ......................................................................................................................................................173
20.6.2 Write Conflict Error..............................................................................................................................................173
20.7 SPI Clock Control Logic ..........................................................................................................................................175
20.7.1 SPI Clock Phase and Polarity Control.................................................................................................................175
20.7.2 SPI Transfer Format............................................................................................................................................175
20.7.3 CPHA=0 Transfer Format....................................................................................................................................175
20.7.4 CPHA=1 Transfer Format....................................................................................................................................176
20.8 SPI Data Transfer....................................................................................................................................................177
20.8.1 SPI Transfer Starts..............................................................................................................................................177
20.8.2 SPI Transfer Ends ...............................................................................................................................................177
20.9 SPI Timing Diagram ................................................................................................................................................178
20.9.1 Master Mode Transmission .................................................................................................................................178
20.9.2 Slave Mode Transmission ...................................................................................................................................178
20.10 SPI Interrupt ............................................................................................................................................................179
20.10.1 Interrupt Mask Register EIE2 ..............................................................................................................................179
20.10.2 Interrupt Priority Control Register EIP2 ...............................................................................................................180
20.10.3 Peripheral Interrupt Flag Bit Register EIF2..........................................................................................................181
21. I2C Module......................................................................................................................182
21.1 Overview .................................................................................................................................................................182
21.2 I2C Port Configuration.............................................................................................................................................183
21.3 I2C Master Mode.....................................................................................................................................................183
21.3.1 I2C Master Mode Timing Cycle Register.............................................................................................................183
21.3.2 I2C Master Mode Control and Status Registers ..................................................................................................184
21.3.3 I2C Slave Address Register ................................................................................................................................187
21.3.4 I2C Master Mode Transmit and Receive Data Registers ....................................................................................187
21.4 I2C Slave Mode.......................................................................................................................................................188
21.4.1 I2C Own Address Register I2CSADR .................................................................................................................188
21.4.2 I2C Slave Mode Control and Status Registers I2CSCR/I2CSSR ........................................................................188
21.4.3 I2C Slave Mode Transmit and Receive Buffer Registers I2CSBUF ....................................................................189
21.5 I2C Interrupt ............................................................................................................................................................190
21.5.1 Interrupt Mask Register EIE2 ..............................................................................................................................190

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21.5.2 Interrupt Priority Control Register EIP2 ...............................................................................................................191
21.5.3 Peripheral Interrupt Flag Bit Register EIF2..........................................................................................................192
21.6 I2C Slave Mode Transmission Mode.......................................................................................................................193
21.6.1 Single Receive ....................................................................................................................................................193
21.6.2 Single Send.........................................................................................................................................................194
21.6.3 Continuous Reception.........................................................................................................................................195
21.6.4 Continuous Sending............................................................................................................................................196
22. UARTn Module ...............................................................................................................197
22.1 Overview .................................................................................................................................................................197
22.2 UARTn Port Configuration.......................................................................................................................................197
22.3 UARTn Baud Rate...................................................................................................................................................198
22.3.1 Baud Rate Clock Source .....................................................................................................................................198
22.3.2 Baud Rate Calculation ........................................................................................................................................198
22.3.3 Baud Rate Error ..................................................................................................................................................199
22.4 UARTn Register ......................................................................................................................................................201
22.4.1 UART0/1 Baud Rate Selection Register FUNCCR .............................................................................................201
22.4.2 UARTn Buffer Register SBUFn ...........................................................................................................................201
22.4.3 UART Control Register SCONn ..........................................................................................................................202
22.4.4 PCON Registers..................................................................................................................................................203
22.5 UARTn Interrupt ......................................................................................................................................................204
22.5.1 Interrupt Mask Register IE...................................................................................................................................204
22.5.2 Interrupt Priority Control Register IP ...................................................................................................................205
22.6 UARTn Mode...........................................................................................................................................................206
22.6.1 Mode 0 - Synchronous Mode ..............................................................................................................................206
22.6.2 Mode 1-8 Bit Asynchronous Mode (Variable Baud Rate) ....................................................................................206
22.6.3 Mode 2-9 Bit Asynchronous Mode (Fixed Baud Rate) ........................................................................................207
22.6.4 Mode 3-9 Bit Asynchronous Mode (Variable Baud Rate) ....................................................................................207
23. Analog-to-digital Converter (ADC) ...............................................................................208
23.1 Overview .................................................................................................................................................................208
23.2 ADC Configuration ..................................................................................................................................................209
23.2.1 Port Configuration ...............................................................................................................................................209
23.2.2 Channel Selection ...............................................................................................................................................209
23.2.3 ADC Reference Voltage ......................................................................................................................................209
23.2.4 Convert the Clock................................................................................................................................................210
23.2.5 Result Format......................................................................................................................................................210
23.3 The ADC Hardware Trigger Start.............................................................................................................................211
23.3.1 The External Port Edge Triggers the ADC...........................................................................................................211
23.3.2 PWM Triggers the ADC .......................................................................................................................................211
23.3.3 Hardware Trigger Start Delay..............................................................................................................................211
23.4 ADC Results Comparison .......................................................................................................................................212
23.5 How the ADC Works................................................................................................................................................212
23.5.1 Start the Conversion ...........................................................................................................................................212
23.5.2 Complete the Conversion....................................................................................................................................212
23.5.3 Terminate the Conversion ...................................................................................................................................212
23.5.4 A/D Conversion Steps.........................................................................................................................................212
23.5.5 Go to Sleep During the Conversion Process.......................................................................................................213
23.6 Related Registers....................................................................................................................................................214
23.6.1 AD Control Register ADCON0.............................................................................................................................214
23.6.2 AD Control Register ADCON1.............................................................................................................................215
23.6.3 AD Control Register ADCON2.............................................................................................................................215
23.6.4 AD Channel Selection Register ADCCHS...........................................................................................................216

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23.6.5 AD Comparator Control Register ADCPC ...........................................................................................................217
23.6.6 AD Hardware Trigger Delay Data Register ADDLYL ...........................................................................................217
23.6.7 AD Data Register High ADRESH, ADFM=0 (Left Aligned) ..................................................................................217
23.6.8 AD Data Register Low ADRESL, ADFM=0 (Left Aligned)....................................................................................217
23.6.9 AD Data Register High ADRESH, ADFM=1 (Right-aligned)................................................................................218
23.6.10 AD Data Register Low ADRSL, ADFM = 1 (Right-aligned)..................................................................................218
23.6.11 AD Comparator Data Register ADCCMPH..........................................................................................................218
23.6.12 AD Comparator Data Register ADCOP ...............................................................................................................218
23.6.13 AD Reference Voltage Control Register..............................................................................................................219
23.7 ADC Interrupt ..........................................................................................................................................................220
23.7.1 Interrupt Mask Register EIE2 ..............................................................................................................................220
23.7.2 Interrupt Priority Control Register EIP2 ...............................................................................................................221
23.7.3 Peripheral Interrupt Flag Bit Register EIF2..........................................................................................................222
24. Touch Module (TOUCH).................................................................................................223
24.1 Touch Module Usage Considerations......................................................................................................................223
25. Flash Memory.................................................................................................................224
25.1 Overview .................................................................................................................................................................224
25.2 Related Registers....................................................................................................................................................225
25.2.1 Flash Protect Lock Register MLOCK ..................................................................................................................225
25.2.2 FLASH Memory Data Register MDATA ...............................................................................................................225
25.2.3 FLASH Memory Address Register MADRL .........................................................................................................225
25.2.4 FLASH Memory Address Register MADRH ........................................................................................................225
25.2.5 Program CRC Operation Result Data Register Lower 8-bit PCRCDL.................................................................226
25.2.6 Program CRC Operation Result Data Register Higher 8-bit PCRCDH ...............................................................226
25.2.7 FLASH Memory Control Register MCTRL ..........................................................................................................226
25.3 Feature Description .................................................................................................................................................227
26. Unique ID (UID) ..............................................................................................................229
26.1 Overview .................................................................................................................................................................229
26.2 UID Register Description.........................................................................................................................................229
27. User Configuration ........................................................................................................232
28. In-circuit Programming and Debugging ......................................................................234
28.1 Online Programming Mode......................................................................................................................................234
28.2 Online Debug Mode ................................................................................................................................................235
29. Instruction Description..................................................................................................236
29.1 Symbol Description .................................................................................................................................................236
29.2 List of Instructions ...................................................................................................................................................237
30. Version Revision Notes .................................................................................................240

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1. Central Processing Unit (CPU)
This series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which
is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data
arithmetic and logic operations, bit variable processing and data transfer operations; the controller module mainly decodes
instructions, and then sends out various control signals; the special register group is mainly used to indicate the memory address
of the current instruction to be executed , Store the operand and indicate the state after the instruction is executed. The special
register group mainly includes accumulatorACC, general register B, stack pointer SP, data pointer DPTR, Program status
registerPSW, Program counterPC, etc.
1.1 Reset Vector (0000H)
The microcontroller has a word-long system reset vector (0000H), after which the program will restart execution at 0000H
and the system registers will revert to their default values. The following program demonstrates how to define a reset vector in
FLASH.
Example: Define a reset vector
ORG
0000H
; System reset vector
LJMP
START
ORG
0010H
; The user program starts
START:
…
; User programs
…
END
; The program ends
1.2 BOOT Partition
The size of the program area space is 16K*8Bit, where the program is divided into BOOT area and APROM area, and the
BOOT area size is allocated by the user configuration register.
When the chip is powered on, if the program is started from the BOOT area, it needs to be satisfied: the address space
allocation method is 1/2/3 (set BOOT_1K/BOOT_2K/BOOT_4K through CONFIG), otherwise the program will be launched from
the APROM area.
Take the 1K space in the BOOT area as an example: confIG configuration BOOT_1K, after the chip is powered on
configuration, the program starts running from address 3C00H. If the program needs to switch between the BOOT region and
the APROM region, it is necessary to write a 0xAA/0x55 to the BOOT region control register BOOTCON (see register description
for details), and then perform a software reset or generate a watchdog reset.
When power-on reset, external reset, voltage reset, bootcon reset value is 0x00, software reset and watchdog reset can
not clear the register.

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BOOT Control Register (BOOTCON)
F691H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BOOTCON
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
D<7:0>:
BOOT zone control bit (this register can only be written when the chip is configured to
BOOT_1K/BOOT_2K/BOOT_4K);
0x55=
If you switch from the APROM area to the BOOT area, you need to write 0x55 to it, and then perform
a software reset or generate a watchdog reset;
0xAA=
If you switch from the BOOT area to the APOROM area, you need to write 0xAA to it, and then
perform a software reset or generate a watchdog reset;
Other
values=
Invalid.
For example, after the chip is powered on and booted from the BOOT area, use the software reset method to switch to the
APROM area, and the configuration is as follows:
1) The BOOTCON register needs to write AAH
MOVDPTR,# BOOTCON
MOVE,#0AAH
MOVX@DPTR,A
2) Perform a software reset
MOVTA,#0AAH
MOVTA,#055H
MOVWDCON,#080H
For example, use the software reset method to switch from the APROM area to the BOOT area, and configure it as follows:
1) The BOOTCON register needs to write 55H
MOVDPTR，# BOOTCON
MOVA,#055H
MOVX@DPTR,A
2) Perform a software reset
MOVTA,#0AAH
MOVTA,#055H
MOVWDCON,#080H
Note: When the BOOT function is valid, the APROM program needs to ensure that the PC does not overflow (overflow
means that the PC is out of the address range of the APROM), and if the PC overflows, the system may run
abnormally.

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1.3 Accumulator (ACC)
The ALU is an 8Bit wide arithmetic logic unit through which all mathematical and logical operations of the MCU are
completed. It can add, subtract, shift and logical operations on data; The ALU also controls the status bits (in the PSW status
register) that represent the state of the result of the operation.
The ACC register is an 8Bit register where the results of ALU operations can be stored.
1.4 B Register(B)
The B register is used when using multiplication and division instructions. If the multiplication and division instruction is not
used, it can also be used as a universal register.
1.5 Stack Pointer Register (SP)
The SP register points to the address of the stack, and the default value after reset is 0x07, which means that the area of
the stack starts at 08H of the RAM address. The value of the SP can be modified, and if the stack region is set to start 0xC0,
the value of the SP needs to be set to 0xBF after the system reset.
Operations that affect SP are: instruction PUSH, LCALL, ACALL, POP, RET, RETI, and entering interrupts.
PUSH instructions occupy one byte in the stack, LCALL, ACALL, and interrupt occupy two bytes in the stack, POP
instructions release one byte, and RET/RETI instructions free two bytes.
Using the PUSH instruction automatically saves the current value of the operated register to RAM.
1.6 Data Pointer Register (DPTR0/DPTR1)
The data pointer is mainly used in MOVX, MOVC instructions, and its role is to locate the addresses of XRAM and ROM.
Inside the chip, there are two data pointer registers DPTR0 and DPTR1, selected by the DPS register.
Each set of pointers includes two 8-bit registers: DPTR0={DPH0,DPL0}; DPTR1={DPH1,DPL1};
For example, the assembly code for operating XRAM is as follows:
MOV
DPTR,#0001H
MOV
A,#5AH
MOVX
@DPTR,A
; Write the data in A to XRAM address 0001H

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1.7 Data Pointer Selection Register (DPS)
The data pointer selects register DPS
0x86
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DPS
ID1
ID0
TSL
AT
--
--
--
SALT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit6
ID<1:0>:
Subtract/add function selection.
00=
DPTR0 plus 1 or DPTR1 plus 1;
01=
DPTR0 minus 1 or DPTR1 plus 1;
10=
DPTR0 plus 1 or DPTR1 minus 1;
11=
DPTR0 minus 1 or DPTR1 minus 1.
Bit5
TSL:
Flip selection enable;
1=
After executing the DPTR instruction, the SEL bit is automatically flipped;
0=
DPTR-related instructions do not affect the SEL bits.
Bit4
AT:
Self-addition/subtraction enable bits;
1=
Allows MOVX @DPTR or MOVC @DPTR instructions to run, perform subtractive/self-addition
operations (determined by ID1-ID0).
0=
DPTR-related directives do not affect DPTR itself.
Bit3~Bit1
--
Reserved, must be 0.
Bit0
SALT:
Data pointer selection bit;
1=
Select DPTR1;
0=
Select DPTR0.
1.8 Program Status Register (PSW)
Program status register PSW
0xD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PSW
CY
AND
F0
RS1
RS0
OV
--
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7
CY:
Carry marker bits;
1=
There are carry-ons;
0=
No carry.
Bit6
AND:
Auxiliary carry markers (half-carry markers);
1=
There are carry-ons;
0=
No carry.
Bit5
F0:
Generic flag bits.
Bit4~Bit3
RS<1:0>:
Working register BANK select bit;
00=
Select Bank0;
01=
Select Bank1;
10=
Select Bank2;
11=
Select Bank3.
Bit2
OV:
Overflow flag bit;
1=
There is an overflow in arithmetic or logical operations;
0=
There is no overflow of arithmetic or logical operations.
Bit1
--
Reserved, must be 0.
Bit0
P:
Check bit;
1=
The highest level of the result occurred.
0=
The highest bit of the result did not occur carry.

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1.9 Program Counter (PC)
The program counter (PC) controls the order of instruction execution in the program memory FLASH, it can address the
entire flash range, after obtaining the instruction code, the program counter (PC) will automatically add one, pointing to the
address of the next instruction code. However, when performing operations such as jumps, conditional jumps, assigning values
to PCL, subroutine calls, initial resets, interrupts, interrupt returns, subprogram returns, etc., the PC loads the address associated
with the instruction instead of the address of the next instruction.
When a conditional jump instruction is encountered and the jump condition is met, the next instruction read during the
execution of the current instruction will be discarded and an empty instruction operation cycle will be inserted before the correct
instruction can be obtained. Instead, the next instruction is executed sequentially.
1.10 Timing Access Register (TA)
Timing access register TA
0x96
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HE
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
TA<7:0>:
Timing access control bits.
Some protected registers must be written to the TA before they can be performed
as follows.
MOV
HE, #0AAH
MOV
TA, #055H
No other instructions can be inserted in the middle, and this sequence needs to
be re-executed when modified again.
Protected registers:
WDCON，CLKDIV，SCKSEL，MLOCK.

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2. Memory and Register Mapping
This series of Microcontrollers has the following types of memory:
◆Up to 16 KB of FLASH program memory (shared by APROM and BOOT).
◆Non-volatile data memory (Data FLASH) up to 1 KB.
◆Up to 256B of general-purpose internal data memory (RAM).
◆General External Data Memory (XRAM) up to 1 KB.
◆Special function register SFR.
◆External special function register XSFR.
2.1 Program Storage Flash
Program memory FLASH is used to store source program and table data, and the program counter PC is used as an
address pointer. The PC is a 16-bit program counter, so the address space that can be addressed is 64KB, but this chip only
has 16K bytes of program storage space.
The FLASH space allocation block diagram is shown in the following figure:
FLASH: 16KB APROM
BOOT
3FFFH
0000H
After the chip is reset, the CPU starts executing from 0000H. Each interrupt is assigned a fixed address in the program
memory, and the interrupt causes the CPU to jump to that address to start executing the service program.
For example, external interrupt 1, which is assigned the address 0013H, if external interrupt 1 is used, its service program
must start at the 0013H location. If the interrupt is not used, its service address is used as a normal program store address.

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2.2 Non-volatile Data Memory Data FLASH
The non-volatile data memory Data FLASH can be used to store important data such as constant data, calibration data,
protection safety-related information, etc. The data stored in this area has the characteristic that the data is not lost in the event
of a chip power outage or a sudden or unexpected power outage. The Data FLASH space allocation block diagram is shown in
the following figure:
03FFH
DataFLASH
1KB
0000H
The read, write and erase operations of the Data FLASH memory are implemented through the FLASH control interface.
2.3 General Purpose Data Memory RAM
The internal data memory is divided into three parts: low 128Bytes, high 128Bytes, and special function register SFR. The
RAM space allocation block diagram is shown in the following figure:
internal RAM
Higher 128 Bytes
(IndirectAddressing mode)
FFH
80H
internal RAM
Lower 128 Bytes
(Indirector Direct Addressing
mode)
7FH
00H
Special Functional Register
128 Bytes
(Direct Addressing Mode)
FFH
80H

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The high 128 Bytes shown above and SFR occupy the same area (80H to FFH), but they are independent. Storage spaces
with direct addressing above 7FH (SFR) and indirect addressing above 7FH (128 Bytes high) go into different storage spaces.
The low 128Bytes spatial register allocation shown in the figure above is shown in the figure below. The lowest 32 bytes
(00H~1FH) make up 4 register groups, each group of 8 storage units, with R0~R7 as the unit number, used to save operands
and intermediate results. After reset, the 0 group is selected by default, and if a different register group is selected, it is decided
by changing the program state. The 16 Bytes (20H to 2FH) behind the register bank form a bit-addressable storage space, and
the RAM units in this area can operate either byte-byte or directly on each bit in the unit. With the remaining 80 storage units
(30H to 7FH), users can set stack areas and store intermediate data.
General Purpose Register
7FH
30H
80Bytes
2FH
20H
16Bytes
(128Bits) Bit Addressable
1FH
18H
8Bytes
17H
10H
8Bytes
0FH
08H
8Bytes
07H
00H
8Bytes
Register Bank3
(8Bytes)
Register Bank2
(8Bytes)
Register Bank1
(8Bytes)
Register Bank0
(8Bytes)
R7
R6
R5
R4
R3
R2
R1
R0
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 76 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00

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2.4 General External Data Register XRAM
There is a maximum 1KB XRAM area inside the chip, this area is not connected to FLASH/RAM, and the XRAM space
allocation block diagram is shown in the following figure:
03FFH
XRAM
1KB
(Indirect Addressing
Mode)
0000H
XRAM/XSFR spatial access operates through DPTR data pointers, which consist of two sets of pointers: DPTR0, DPTR1,
selected by the DPS registers. For example, through movx indirection operations, the assembly code is as follows:
MOV
R0.#01H
MOV
A,#5AH
MOVX
@R0,A
; Write the data in A to XRAM address 01H, the high 8-bit address is
determined by DPH0/1
After target--> Memory Model is set to Large in Keil51, the C compiler will take XRAM as the variable address. XRAM/XSFR
operations are generally performed with DPTR.

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2.5 Special Function Register SFR
Special function registers refer to a set of registers with special purposes, essentially some on-chip RAM units with special
functions, discretely distributed in the address range of 80H to FFH. Users can byte access them through direct addressing
instructions, and addresses four bits lower than 0000 or 1000 can be addressed bitwise, such as P0, TCON, P1.
The register table is as follows:
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
0xF8
--
PCRCDL
PCRCDH
MLOCK
MADRL
MADRH
MDATA
MCTRL
0xF0
B
I2CSADR
I2CSCR
I2CSBUF
I2CMSA
I2CMCR
I2CMBUF
I2CMTP
0xE8
--
ADCON2
SCON1
SBUF1
SPCR
SPSR
SPDR
SSCR
0xE0
ACC
--
TL4
TH4
--
--
--
--
0xD8
P5
ADCCHS
TL3
TH3
ADRESL
ADRESH
ADCON1
ADCON0
0xD0
PSW
ADCMPC
T34MOD
ADDLYL
ADCMPL
ADCMPH
SCKSEL
SCKSTAU
0xC8
T2CON
T2IF
RLDL
RLDH
TL2
TH2
CCEN
T2IE
0xC0
--
--
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
0xB8
IP
EIP1
EIP2
EIP3
WUTCRL
WUTCRH
BUZDIV
BUZCON
0xB0
--
--
EIF2
--
P0EXTIF
P1EXTIF
P2EXTIF
--
0xA8
IE
--
EIE2
--
P0EXTIE
P1EXTIE
P2EXTIE
--
0xA0
P2
P1TRIS
P2TRIS
--
--
P5TRIS
--
P5EXTIF
0x98
SCON0
SBUF0
P0TRIS
--
P5EXTIE
--
--
--
0x90
P1
FUNCCR
--
--
--
--
HE
WDCON
0x88
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
CLKDIV
0x80
P0
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON