Scientific data systems 8271 User manual

TeCHNICAL MANUAL
MULTIPLEXING
INPUT/OUTPUTPROCESSOR
MODELS
8271/8471 AND 8272/8472
SCIENTIFIC CATA SYSTEMS

TECHNICAL MANUAL
MULTIPLEXING
I'NPUT jOUTPUT PROCESSOR
MODELS 8271/8471 AND 8272/8472
May 1968
SDS 901515A
$5.25
SCIENTIFIC DATA SYSTEMS. 1649 Seventeenth Street. Santa Monica, Calif .• [phone]
<9
1968, Scientific Data Systems, Inc.

Effective Pages
SDS 901515
I LIST OF EFFECTIVE PAGES
I
I
Total number of pages is 156, as follows:
A
Page No.
Issue
Title. • • • • • . . • . • • . . • . • • . •• Original
A .•..••••.•.••.••••..• Original
i thru iv. • • • • • • • • • • . . • . • • .• Original
1-1 thru 1-2 • • . . . • . . • .• • • • •• Original
2-1 thru 2-2 ••..••.•.• '. . . • •• Origina I
3 -1 thru 3-142 •••.•.•..•.•.. Orig ina I
4-1 thru 4-4 • • . • . . . • . • . . • . •• Original
Page No. Issue

Section
II
III
SDS 901515
CONTENTS
Title
GENERAL DESCRIPTION
1 -1
1-2
1-3
1-4
Introduction •.•••.••.•...•..•.•..•....••..•••.•....•..•...•.•...
Physica I Description •.••.•.••••.....•.•.••..••••••.•.•.•..•••. 0 •••
FunctionaI Description ••.•••••.••• 0 •••• 0 ••••••••••••••••• 0 ••• 0 •••••
Specifications and Leading Particulars •••..•••.......•••..•••.•..••.•..•.
OPERATION AND PROGRAMMING •• 0 0 •••••••• 0 0 ••••• 0 ••••••••••••• 0 •• 0 ••••• 0
2-1
General
PRINCIPLES OF OPERATION 0 0 ••••••••••••••••••••••• 0 •• 0 0 ••• 0 • 0 ••••••••••••
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Introduction 0 0 ••••••••••••••• 0 ••••••••• 0 0 0 •••••••••••••••••••••
Genera I Principles of Operation ••.••.••.•.•.•.•...••••••••••••..•......
Genera I ••...••...•••.•..••...•...•...•••••.••••••.••......
Overa II Operation ....••....•••••••••.••..•••••..•.•.•.•••••....
Interrupt Ca lis .••.••.•• 0 •••••••••••• 0 •••••••••••••••••••••
Chaining ..•...•••..... 0 ••••••••••••••• 0 •••••••••••••• 0 ••
Detailed Principles of Operation •••.•..••••.•.••..••••.••.•.... 0 0 • 0 0 0 0 •
MIOP Registers 0 0 0 0 •••• 0 0 • 0 0 0 0 0 •• 0 0 0 0 • 0 00 •• 0 0 • 0 ••• 0 •• 0 0 • 0 0 ••• 0
A-Register. 0 • 0 0 •• 0 0 • 0 0 0 0 0 0 •••• 0 •• 0 • 0 •••• 0 • 0 0 0 •• 0 •• 0 0 • 0 0 • 0
C-Register 0 0 0 0 •• 0 • 0 •••• 0 •• 0 •• 0 0 • 0 0 • 0 •• 0 • 0 •••••••••• 0 •••••
CA-Register ••••••••••.•.. 0 •••• 0 •••• 0 ••••••••• 0 •••••••• 0 ••
BA-Register .• 0 •••••••••• 0 0 •••••• 0 ••• 0 • 0 0 ••••••••••••••• 0 •
BC -Register .• 0 • 0 ••••• 0 ••••••••••••••••••••••••• 0 •••••••••
FS-Register .....•.••.. 0 •••••• 0 •••••• 0 •••••••••• 0 0 ••••••••
OF-Register ........••......•..•.•.. ' ........•.•.•......••.
IS-Register .•......••••........•.••..•.•...•....•..••.•..
F-Register •.....•..•..•..•••.........••.•.........•.•....
H-Register ......•.......•....•..•...........•...........•
J -Register . . . . • . . . . . . • . • . . • • . . . • . . • . . . . . . • . . • . . . . . . . . . . . .
I-Register
.•.........••.•..•..••..•.••..•..••......•..•..
O-Register .•....•...••.•..•.....•.••.••••.••.....•....•..
S-Register • . . . . • . . . . . . . . • • • • . . . . • • . • • • • . . • . • • • • . . • • . . . . . .
M-Register
......••...•..•.••....•.•.••.•••..••...•..•...•
W-Register ...•.•..•..••••.••..•....••.•...••.•..........•
Adder ....•••••..••••••.••..•.......•...•...••.............
Typica I I/O Operation Starting With an SIO Instruction ....•................
I/O System Interface Connections ...••.....•...•.. ~ ..•..•..•........
MIOP Interface Signa Is ........••.•..............................
MIOP/Memory Interface ....•........•...•.•.••...............
MIOP/CPU Interface ..•.•.....••..•.•...•..••....•.......•..
MIOP /Dev ice Contro II er Interface ••.•...••..•.•..••....•........
Subchannel Addressing ...••••.•.•..••......•..•..•••............
MIOP Timing Signals ...••.........•..•...•...•....•.......•....
Delay Line Operation .......•.•.•.......•.•..................
Phase Latches .•...••••••.•....•....•.•••..................
Phase Sequences ...........•.•...•.......•..•................•
SIO Instruction ....•••.••••....•••..•.•.•.•••••.••.....•.••
HIO, TIO, and TDV Instructions ••..••..•..••.•.•....••.•........
AIO Instruction ..•...•....•...•..........•...••.•..••......
Contents
Page
1-1
1 -1
1-1
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2-1
2-1
3-1
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Contents -Tables-Illustrations
SDS 901515
Section
IV
Table
1 -1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
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3-15
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4-1
4-2
Figure
1-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
ii
CONTENTS (Cont.)
Title·
3-40 Order-Out Service Cyc Ie .••••••••.••••••••••••••••.••..•••.••
3-41 Order-In Service Cycle .•••••••••••..•.•...•••.••••..•...•.••
3-42 Data-Out Service Cycle •••••••.•.•••.••..••.••••••••••••...••
3-43 Data -In Service Cyc Ie •.•••••••.••••.••.••••••..•••••••••••••
3-44 Glossary ••••••••••••••••••.••••.•••••.••••••••••••.•••••••..••
MAINTENANCE AND PARTS LIST •••••••••••••••••••••••••••••••••••••••.••••
4-1 General ••••••.••••••••••••.•••••••.•••.••••••...•••.••••••.••
4-2 Preventive /lkintenance •.••.•.•••••....••.•..•••..••..•••••••.•••••
4-3 ExternaI VisuaI Inspection •.•.••••••••.•••••••••••••••••.•••.••••.
4-4 InternaI VisuaI Inspection ..•••..•••.•.••••••••.•••••..•••.•.••••.
4-5 MIOP Test Programs •..•..•••..••••.•.•.•.•••.•.•.••••••.....•••
4-6 Parts List Table •••.•..•••.••.•••.••.••••••.•.•••••••••.•.••••••.•
TABLES
Title
Genera I Specifications ••.••••••.••••••••••••.•••••.•••••••••••••.•..•••••.
MIOP/Memory Interface Signals •••••.•••••••••••••••.••• ~ ••••••••.•.•.•••••••
MIOP/CPU Interface Signals .•.•.••••.••••••••••••••••••.•••.•.••••••.••••••
Condition Code Settings •••••..••••.••.•.••••.•.••.•••••••••••••••..•••••.•
MIOP/Device Controller Interface. ..••..••••••••••••.•••••••••••••.•••••••••.•
MIOP/Device Controller Interface Line Utilization ••••••.••••••••.•••.••.•.••.•••.•
Data Input/Output Line Definition ••••..••••••••••.••••••••••••••••.••••••••••
Data Order Request and Input/Output Request Line Definitions •••••••••••••••••••....•.•
Function Response Line Definition ..••••••••••••••.•••.••••••••••.••••••••••••
Coding of End Data and End Service Lines During Data In/Out Operations •••••••••••••••.•••
Permitted Next States of End Data and End Service Lines .••.•.•...•....••..••.•...••..
MIOP/Memory Phase Sequence ••••••.•••••.••.•••••••••.••.••.••••.••••••••.
SIO Instruction Phase Sequence .......•.•.•••••.•••••.••••.•.•••.•.•.•....•••
HIO, TIO, and TDV Instruction Phase Sequence ••••.•.••.•••••••••••••••...•.••..•
AIO Instruction Phase Sequence •••••••.••...•••••••••••••.••••••••..•.•..•...
Order-Out Service Cyc Ie Phase Sequence •..•.••••••••••••••.••.••••••.••.•••••.
Order-in Service eyc Ie Phase Sequence •.••••••••••.••••.••••.•••••••..•.•..•...
Data-Out Service Cycle. Phase Sequence .••••••••••••••••••••••.••••••••••••••••
Data-In Service Cyc Ie Phase Sequence •.•.•••...••••.•..•••••••••.••••.•..•••.•
Glossary of MIOP Signals' ........••••••.•••••••••••••••••.•••••.••••..•..•.
Checkout Programs for MIOP ..•••..•.•••••..••••..••.•••••••.••..••••.••.••.
Multiplexing Input/Output Processor, Replaceable Parts ..••.•••..••••.•••••.•..••....
ILLUSTRA nONS
Title
MIOP Basic and Optiona I Subchannel Locations •••••.•.•••••••••••••••••.••••••..•.
I/O System, Simplified Overall Block Diagram ••••••••••.•••••••••.•••.••.•••.••••
Loading Core Memory Location X'20' During an SIO Instruction ••••••••••••••••••.•.••.•
MIOP Block Diagram •.•.•.•.••••.••••••.•.•••.••.•••••.••••.•••••.•••....
A-Register Inputs •......•••.••.•••••••••.•••.•••••••••••••••••••.••••....
C-Register Inputs •••••••••.•••••.••••••••••.•••.••.•••••••••••.••••••.••
BA- and CA-Register Inputs ••.•••••.••••.•••••••••.•.•••••••••.•••••••••••.•
BC- and FS-Register Inputs •.•••.••••••••••••••••••••••••••••••••••••••.•••.
OF- and IS-Register Inputs ••..•••••.••••••••.••••••••••••••••••••••••••..••
F-Register Inputs •.•.•••......••.••.••••.•.••..•.•••.••.•.•.••.•.•..••..
Page
3-68
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4-1
4-1
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Figure
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4-1
SDS 901515 Illustrations
ILLUSTRATIONS (Cont.)
Title
H- and J -Reg ister Inputs ••••....••.••.••••••••••..•.•••••••••••.•.••.••.•..
I-Register Inputs ••••.•••.•....••••.••••••..•••.•.•••••••••••.•...•.•..••
O-Register Inputs .••.•••.•••.••.•....•••••.••••.•.••••••.•••••..•••.•..•
S-Register Inputs ••••••••••••.•••••••••••••..••.••.•••••••••.•.••.••••.•
M-Register Inputs •••••••••.•..••.•..••.•••••••.••.••.•.•..•••.•..•......
W-Register Inputs ••••.••••.••••...•..••••.•.•••.••••••••••...•••••.....•
Adder, Overall Block Diagram •••.••..•.•.•.•.•.••.•••.•.•••••••.•.•••.•.••..
TypicaI I/O Operation, Overa II Sequence Diagram ••.•••..••.••••.••.•••..•.....•..
Typical I/O Operation, Timing Diagram ...•••.....•.•.•.•.•••.•.....••.••••...•
MIOP, Overall Block Diagram •..•.•••••..•••••••••••••••••••.•••••.•••...•..
I/O System Interconnection Diagram •.•.••••••.•.•.••••••.••....•••••••••......
MIOP/Memory Interface Signal Timing Diagram (Port A or B) •••••••••••••••••••••••••••
Setting Memory Data Release Flip-Flop MDR1 •..••••••...•.•.•••.•••••••••.•......
MIOP Fast Access Memory Organization •••••.•••..••••••.•.•••••.•••••••.••....•
Assignment of Subchanne[ Groups •..••.•. " ..•.• " .•.•••••.•.••••••••••••••••..••.
Decoding the Address Register .•••..•••••••.•.••••.••.••••••••••..••..•.•••.•
Decoding SPA5, SPA6, and SPA7 Address Signals to Select One Subchannel in Group Zero .•••••..
Typical FT25 Fast Access Memory Module •.••••.•.•..•••..•..•••••••..•.•••.•.•.•
Delay Line 1 Logic Diagram ••.•.•••••••.•.•.•.•••••.•..•.••••••.•......•.•.
Delay Line 1 Timing Signals ••..•..•.•••.•••.••..•...•.•.••••.••..•..•.•.•..
Delay Line 2 Logic Diagram ...••..•••.•••.•.•••.•••.•.•••.•....••...•..••.•
Delay Line 2 Timing Diagram ••..•.•.•••••••••.....••.•••..•••..••.••.•.....•
Phase Diagram for SIO, HIO, TIO, and TOY Instructions •.•••..•••..••.•..•.•••••.••.•
Data Flow During an" SIO Instruction ..•••.•••.•••.••••.•.••••••••••..••...•..•.
Phase Diagram for an AIO Instruction •.•.•...•.•.•..•....••••.••.•..•..•........
Phase Diagram for an Order-Out Service Cycle .•••••.••.•.••••.•.•••••..•..••.•..•
Processing a Transfer in Channel Command ..•.•••...••.•..••.••.•.••••.•.....••.•
Processing a Command Doubleword ....••••.•..•...•.•.•.•••••••••.•.•..•.•.•..
Termination Phase of an Order-Out Service Cyc Ie ••....•......•.•.•...•.•••....••..
Phase Sequences For an Order-In Service Cycle ..••..•..•..•..•••.•.••.......•....•
Updating Flags and Status During an Order-In Service Cycle •.••.•••.•..•...••..•..•.•..
Updating Interrupt Status During an Order-In Service Cycle .••..•••••.••••••.•..•.•.•..
Phase Sequence Diagram For a Data-Out Service Cycle ..•••••..•••••••••••.•.•.••....
Processing a Data-Out Service Cyc Ie ..••••...••.•.•..•..•.••••••......•........
Processing Data During a Data-Out Service Cycle, Timing Diagram ••....•...•..•.•.......
Phase Sequence Diagram For a Data-In Service Cycle .•...•.•.•.•.•••....•.•.••..•...
Processing Data During a Data-In Service Cyc Ie ....•...•..••..•.•..•••...•.•......
MIOP Module Location Chart .......••..•....•........•.•••...•..•....••.....
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4-2
iii

Related Publications
iv
SDS 901515
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SDS 901S1S Paragraphs
1- 1 to 1-4
SECTION I
GENERAL DESCRIPTION
1-1 INTRODUCTION
This manual describes SDS Multiplexing Input/Output
Processor (MIOP) Models 8471 and 8271 and optional sub-
channels, Models 8472 and 8272. The manual consists of
four sections that provide general information, program-
ming information, a functional description, maintenance
information, and parts lists.
The MIOP provides
independent control of data transfers
between core memory and certain peripheral devices, and
starts, tests, and acknowledges interrupts
pertaining to
certain peripherals under control of a Sigma S or 7 central
processing unit.
Figure 1-1 shows
the physical layout of the basic MIOP,
Models 8471 (Sigma 7) and 8271 (Sigma S), and the
optional subchannels, Models 8472 (Sigma 7) and 8272
(Sigma S).
Technical manuals describing equipment associated with the
MIOP are referred to in the list of Related Publications in
the front matter of this manual.
1-2 PHYSICAL DESCRIPTION
The basic MIOP consists of 98 modules installed in chassis
A,
S, C, and D, and includes eight subchannels. Each
subchannel accommodates
one device controller. Five
fast-access memory modules (FT25) provide eight sub-
channels. Since one fifth of each subchannel is contained
on each of the five FT25
ls, the
FT25
ls must be
installed in
groups
of five. Three additional groups of FT25
ls provide
a
total of 32 subchannels.
1-3 FUNCTIONAL DESCRIPTION
The MIOP contains input and output data storage registers
and buffers, fast-access memory registers for command mani-
pulation, a timing signal generator, and control logic. The
function
of the MIOP is to control and sequence input and
output operations for a number of peripheral devices simul-
taneously, allowing the CPU to concentrate on program
execution. The active devices time-share the hardware in
the MIOP. Any input-output events that require CPU in-
tervention are brought to the attention of the CPU by means
of the interrupt system. The device controllers and devices
are described in other manuals.
1-4 SPECIFICATIONS AND LEADING PARTICULARS
The general specifications for the MIOP are given in
table 1-1.
Table 1-1. General Specifications
Power requirements (supplied
by PTl6
power supply)
Logic signal levels
Data format
Temperature
Nonoperating:
Operating:
Relative humidity (operating)
Altitude
Nonoperati ng:
Operating:
+8Vdc (9.0 amps)
-8Vdc (2.4 amps)
+4Vdc (20 amps)
Total watts:
171
One, +4Vdci Zero,
Ov (low impedance
to ground) .
8-bit byte, 32-bit
word
-40
0C to
60
0C
(-40
0F to 1400
F)
soC to SOOC
(41°F to 122°F)
1 0'/0 to 9S%
20,000 feet maximum
10, 000 feet maximum
1-1

1-2
SDS 901515
I t- .. ....--SLOTS 1 THROUGH 32
-I
CHASSIS A
CHASSIS B
CHASSIS C
r-----------,
I I
CHASSIS D I I
I I
L ________ -.I
SLOT NO. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
FAST ACCESS MEMO
MODULES (FT25)
SUBCHAN NELS 0 - 7
(BASIC lOP)
RV{
SUBCHANNELS 16-23
(OPTIONAL)
SUBCHANNELS 8-15
(OPTIONAL)
SUBCHANNELS 24-32
(OPTIONAL)
• !~ ~ . .
~ .
. ~
~~ .
~ A~
~ . ~ . •
~~ .
Figure 1-1. MIOP Basic and Optional Subchannel Locations
~ ~ . .
..
I
901515A.101

SOS 901515 Paragraph 2-1
SECTION II
OPERATION AND PROGRAMMING
2-1 GENERAL
The MIOP contains no controls or indicators other than
address switches and switch LASTONE, which is closed on
all MIOPs connected to a CPU except the last one. These
switches are contained on the switch comparator module
(LT26) in slot 13 of chassis C. The module contains eight
switches; the three address switches that apply to the MIOP
are S 1-1, S2-1, and S3-1, and the switch that applies to
signal LASTONE
is S 1-2.
In the Sigma 5 and 7 I/O system, the CPU executes instruc-
tions, the MIOP executes commands, and the I/O device
executes orders. For example, the CPU may execute a
start input/output (SIO) instruction to initiate an I/O
operation. During the course of the operation, the MIOP
fetches a command doubleword (command) from the com-
mand list in core memory and stores it (except the order
bits) in its own fast access memory. The command provides
the MIOP with information needed to perform its functions;
commands are, therefore, executed by the MIOP. The
order bits of the command are transmitted to the device.
The order defines the operation to be performed by the
device; the I/O devices, therefore, execute orders.
For a description of I/O instructions, commands, and
orders, see SDS Sigma 7 Computer Reference Manual
900950 and SDS Sigma 5 Computer Reference Manual
900959.
2-1/2-2

SDS 901515 Paragraphs
3-1 to 3-4
SECTION III
PRINCIPLES OF OPERATION
3-1 INTRODUCTION
This section describes the principles of operation of the
MIOP on a general information level and on a detailed
level in terms of the logic equations. The detailed descrip-
tion includes a description of each lOP register, a typical
I/O operation, the interface signals, timing generation,
interface signals, lOP phase sequences, and a glossary of
logic signals. There is a phase sequence description for
each CPU-initiated I/O instruction and for each of the
four service cycles. Each phase sequence description
includes a
table that lists every logic operation that occurs
in the MIOP relating to the specific instruction or service
cycle, starting with the first timing signal of the first phase.
3-2 GENERAL PRINCIPLES OF OPERATION
3-3 GENERAL
The maximum number of devices that can be uniquely
addressed by a computer with one MIOP installed is 152.
Up to eight MIOP's can be connected to one computer.
The basic MIOP is mechanized with eight subchannels that
accommodate eight device controllers. Because of the
addressing structure of the I/O instructions, only these first
eight subchannels can be used for servicing multiunit device
controllers. The multiunit device controllers are capable
of controlling up to 16 devices each. When the multiunit
device controllers are used, the subchannel is shared by all
the devices controlled by that device controller. Each
subchannel contains all the information necessary to control
any I/O operation between core memory and the device.
Once an I/O operation has been started by the CPU, the
operation is performed to completion by the MIOP, device
controller, and core memory without intervention by the
CPU. Timing between these units is asynchronous. The
MIOP processes the I/O operation while the CPU is per-
forming functions possibly unrelated to the I/O operation.
The MIOP controls the I/O operations by executing a
command list prepared by the CPU and stored in core
memory (figure 3-1).
3-4 OVERALL OPERATION
An I/o operation starts when the CPU issues a start input/
output (SIO) instruction addressed to a particular MIOP and
device controller. The addressed MIOP, after receiving the
address information, places the device controller address on
the MIOP/device controller interface lines and waits for
a response.
The addressed device controller responds by
sending condition code and status information to the MIOP.
The MIOP sends the condition code information to the CPU
and, depending upon the coding of the SIO instruction, may
or may not send status and other information related to the
MIOP, device, and device controller to the CPU. The SIO
instruction, if successful, causes the addressed device con-
troller to make service requests from the MIOP. As a result
of the servi ce requests (after the SIO instruction has been
concluded), the device controller electrically connects
itself to the MIOP/device controller interface lines. The
time the device controller is electrically connected is
called a service cycle. It is during the service cycles that
follow an SIO instruction that data is exchanged between
the device controller and core memory. During these
service cycles the MIOP performs core memory accesses as
required by the device, continually updates information
such as byte address and byte count, and controls the I/o
operation until it is completed, aborted, or halted by a halt
input/output (HIO) instruction.
During execution of the I/O instructions, core memory
locations, X' 20
' and X'21' (hexadecimal
20 and 21), are
used to exchange information between the MIOP and CPU.
These are in addition to the MIOP/CPU interface lines.
During the early phases (CPU phases) of an SIO instruction,
the CPU writes the address of the device/device controller,
the address of the first command doubleword, and the nature
of the R field into core memory location X' 20
' (see figure
3-2).
The function code (SIO) and MIOP address are sent directly
to the MIOP on the MIOP/CPU interface lines. The ad-
dressed MIOP then reads core memory location X'20', stores
the address of the command doubleword in its internal
registers, and pI aces the devi ce contro II er address on the
MIOP/DC interface lines. After the addressed device con-
troller responds by sending status and condition code infor-
mation to the MIOP, the MIOP loads the status and other
information (if the CPU so specifies by the coding of the
R field of the instruction) into core memory location X' 20
'
and X'211, where it is available to the CPU. The other
information consists of information previously stored in the
subchannel for the addressed device controller. The con-
dition code is sent directly to the CPU.
At the conclusion of a successful SIO instruction, the device
controller starts making service requests to the MIOP. The
first service request, which will be for an order out, causes
the MIOP to access the command list in core memory for the
first command doubleword.
The address of the command
doubleword was obtained
from the CPU during the SIO in-
struction. The order that is encoded in the command double-
word is sent to the device controller so that it wi II know what
3-1

SDS 901515
r CORE MEMORY I
DEVICE ADDRESS AND I DEVICE ADDRESS AND
COMMAND ADDRESS I
.. I
COMMAND ADDRESS
-1
LOCATIONS
- I
STATUS 1--.
X'20' AND X'21' I
STATUS
I I
...
I I
I I
---
COMMANDS
I
COMMAND
I COMMANDS
CENTRAL
-I
LIST
-I PROCESSING
UNIT
I/O DATA (WORDS)
I I
-
-L ______ .J
MUL TIPLEXING
lOP CONDITION
CODE AND INTERRUPT CALLS
.
lOP ADDRESS AND FUNCTION CODE
-
SERVICE CALLS, INTERRUPT CALLS, CONDITION CODE, AND STATUS
-
I/O DATA
DEVICE AND
...
DEVICE
--
ORDERS
CONTROLLER
!' -
r ,r
I
OTHER I/O DEVICES
AND DEVICE CONTROLLERS
901515A.301
Figure 3-1. I/O System, Simplified Overall Block Diagram
SIO INSTRUCTION REGISTER 0 (CPU PRIVATE MEMORY)
~I----------~'--------~I I '
I~I
I
MEMORY LOCATION X'20' 90l515A.302
Figure 3-2. Loading Core Memory Location X' 20
' During
an SIO Instruction
3-2

SDS 901515 Paragraphs
3-5 to 3-10
function to perform. The balance of the command double-
word is related to the I/o operation and is retained by the
MIOP. This information directs the operations of the MIOP
until the I/O operation is concluded. The exchange of
I/O data takes place after the device controller has re-
ceived the order.
As a result of subsequent service requests from the device
controller, data is exchanged between core memory and the
device through the MIOP. The exchange of data between
core memory and the MIOP is on a word basis and between
the lOP and the device controller on a byte basis. A maxi-
mum of four bytes of data may be exchanged between the
MIOP and device controller for each service request. For
example, if the order the device received initially was a
write order, the operation would be an output operation.
In this case, as a result of a service request from the device
controller, the MIOP would access core memory for one
word of data and store it in an MIOP register. The word is
then fed to the device controller one byte at a time. If the
order the devi ce received was a read order, the operati on
would be an input operation. During an input operation,
the MIOP accepts data from the device controller one byte
at a time and stores it until it has a maximum of four bytes.
The four bytes (one word) are then stored in core memory by
the MIOP. In addition to transferring I/O data, the MIOP
keeps track of the number of bytes of data transmitted and
their core memory locations, records status for future inter-
rogations by the CPU, checks parity, and performs other
operations as required.
3-5 Interrupt Calls
Interrupt calls made by a device controller are passed along
to the CPU by the MIOP. One standard interrupt level is
provided to service all interrupts generated by all devices
connected to all MIOP's controlled by a CPU. In response
to an interrupt call, the CPU issues an acknowledge input/
output interrupt (AlO) instruction. The primary purpose of
the AIO is to determine the address of the interrupting lOP
and device controller. The highest priority device con-
troller with an interrupt pending sends its address (along
with status and condition code information) to the MIOP.
The MIOP writes its own address, the device controller
address, and status information in memory location X'20'
and sends the condition code information to the CPU. The
CPU then reads memory location X'20' to acquire the
address and status, and takes acti on based on the status
and condition code information it has just received.
3-6 Chai ni ng
Chaining is the term applied to the operation that permits
an activity to continue after the functions specified by the
current command have been completed. The MIOP employs
both data chaining and command chaining. Both types of
chaining are controlled by a flag setting of the current
command and result in a new command being fetched by
the
MIOP when all data specified by the current command has
been transferred. Each new command
fetched by the MIOP
is the next command in sequence in the command list in
core memory.
Data chaining is used for scatter-read or gather-write oper-
ations, where the peripheral device is operating with a
record ~f continuous data that may come from, or be delivered
to, noncontiguous areas of core memory in subblocks of any
size specified by the programmer.
Command chaining provides a means of writing a program
to operate on several records without intervention by the
CPU. Command chaining causes the MIOP to load a new
command at the end of a record, send the new order to the
device controller, and start processing the new record.
3-7 DETAILED PRINCIPLES OF OPERATION
3-8 MIOP REGISTERS
The various data and control registers wi thi n the MIOP are
shown in figure 3-3. The MIOP address logic and timing is
shown as a single block, since these two sections are de-
scribed separately. For convenience, the formats of the
subchannel registers, the data lines, and the function
response Iines are also included in fi gure 3-3. With the
description of each register is a flow diagram showing the
source of all input signals to that register. The transfer sig-
nal that enables the input signals to enter the registers is
shown in the break of the line connecting the input source
to the register•
3-9 A-Register
The A-register (see fi gure 3-4) consists of eight buffer
latches, AO through A7, and normally contains the device/
device controller address. During execution of an instruc-
tion (except an AIO), the A-register receives the address
information from the M-register. During an acknowledge
service call (ASC) function and an AIO instruction, the A-
register receives the address from a device controller by
means of the FR lines. The address in the A-register is de-
coded by the address decoding logic (SPA3 through SPA7) to
select one of the 32 possible subchannels (see figure 3-25).
The A-register is cleared to zeros when signal AXO is true.
3-10 C-Register
The C-register (see figure 3-5) consists of 15 buffer latches,
CO through C14, and one buffered latch, flip-flop C15. The
C-register is the only input to the adder. The C-register,
with the adder, is used as a common point for the distribu-
tion of data between various MIOP registers. The C-register
is also used with the adder and two buffered latches (K15
and SUB), as a means of incrementing or decrementing a
number by one. Input data to the C-register consists of
status information which comes from various sources, the M-
register, the BA lines, and the BC lines. When signal LSO
is true, the information on the BA lines is the output of the
command address (CA) register, and when signal LSD is
false, the information on the BA lines is the output of the
byte address (BA) register. When si gnal LS 1 is true, the
information on the BC lines is the output of the flags and
status
(FS) register, and when si gnal LS 1 is fal se, the infor-
mati
on on the BC lines is the output of the byte count (BC)
register. The C-register is cleared to zeros when signal
CXD is true.
3-3/3-4

SDS 901515 Paragraphs 3-11 to
3-14
t
AXO
I
M-REGISTER
I
AXM
t A-REGISTER
f
AXFR
I
CLEAR A
FR LIN ES (FRO-FR7)
901515A. 304
Fi gure 3-4. A-Register Inputs
3-11 CA-Register
The
CA-register (see figure 3-6) is one of the six registers
that comprise each of the 32 possible subchannels. Each
CA-regi ster consists of 16 fast-access fli p-flops, CAO
through CA15. This register holds the current command
doubleword plus
one. During execution of an instruction
(when
the current command doubleword is to be sent back
to the CPU as part of the response information), the con-
tents of the CA-register are transferred through the adder
and decremented by one. During chaining operations, the
contents of the CA-register are circulated through the C-
register and adder to increment them by one every time a
command doubleword is accessed
from core memory. The
CA-register receives its input data from the adder. The
output of the CA-register is available to the C-, M-, and
S-registers.
Both the input data lines and the output data
lines of the CA-register are shared with the BA-register.
The command address (16 bits) is set into the 16 most
si g-
nificant bits (MSB) of the S-register whenever a new
command doubleword is to be
accessed. The 17th bit, S31,
which is the least significant bit (LSB) of the S-register,
is
controlled separately. This permits the MIOP to access
the first word of the command doubleword when S31 is false
and to access the second word when it is true.
3-12 BA-Register
The BA-register (see
fi gure 3-6) is one of the si x registers
that comprise each of the 32 possible subchannels. Each
BA-register consists
of 16 fast-access flip-flops, BAO
through BA 15. This register contains the 16 MSB's of the
current byte address. The three LSB's of the byte address
are contained in the OF-register (see figure 3-46). Bit
position OF2 is
the LSB of the byte address and OFO is the
third LSB. The 16 bits (BAO through BA15) of the BA-
register and
OFO constitute a word address in core memory.
The two
LSB's (OF2 and OFl) define the particular byte of
that word. Every time a byte of data is processed the byte
address is incremented or decremented as required. After
every fourth byte a carry to, or borrow from, the LSB of the
word address (OFO) is required. The BA-register contents
must, therefore, be updated when a carry to, or borrow from,
the three LSB's in the OF-register occurs. Whether the
byte address is
incremented or decremented depends on the
backward flag (BK) stored in the OF-register. This flag is
true only if a read backward order was sent to the device.
When the device is reading backward, data received from
that device is written into descending core memory loca-
tions. Therefore, the byte address must be decremented by
one with
each byte processed. If the BK flag is false, the
byte address is incremented by one with each byte
processed.
3- 13 BC -Register
The BC-register (see figure
3-7) is one of the six registers
that comprise each of the 32 possible subchannels. Each
BC-register consists
of 16 fast-access flip-flops, BCO
through BC15, and contains the current byte count. During
a
data-in or data-out operation, the byte count is decre-
mented by one by circulati ng it through the C-register and
adder after each byte of data is processed. The BC-register
receives its input data from the adder. The output of the
BC-register is
available to the C-register when decre-
menting during a data operation and the M-register as part
of the response information during execution of an instruc-
ti on. Both the input data lines and the output data lines of
the BC-register are shared with the FS-register. The BC-
register is addressed when signal LSI is false.
3-14 FS-Register
The FS-register (see figure 3-7) is one of the six registers
that comprise each of the 32 possible subchannels. Each
FS-register consists
of 16 fast-access flip-flops, FSO through
FS15. The upper half of the FS-register (bits FSO through
FS7) contains the flags specified by the command doubl e-
word. During an order-out service cycle, the second word
of the command doubleword is set into the M-register. Dur-
ing the termination phase of the service cycle, if there are
no error conditions detected, the flags from the command
doubleword
are transferred from the M-register by means of
the C-register and adder to the FS-register (see figure 3-38).
If error conditions are detected, the old flags are effec-
tively retained by the FS-register. During an order-in
service cycle, the old flags are retained by the FS-register.
The lower
half of the FS-register (bits FS8 through FSI5)
contains status information. The status information is up-
dated during the service cycles. Figures 3-38 and 3-40
show the source of status update information during an
order-out and order-in service cycle. An OR operation is
performed on the new status,
acquired during the service
cycle, with part of the 01d status in the FS-register. The
flags and status control the operations of the MIOP during
the service
cycles.
3-7

Paragraph 3-15
SOS 901515
BC/FS-REGISTER
I
CXBCL
CXBCU
I
BA/CA-REGISiER
"
M-REGISTER
STATUS
BITS
I
l
I
CXM
I
CLEAR C
I
CXO
I
901515A. 305
Fi gure 3-5. C-Register Inputs
Both the input
data lines and the output data lines of the
FS-register are shared wi th the BC-register. The FS-
register is addressed when si gnaI LS 1 is true.
3-15 OF-Register
The OF-regi ster (see fi gure 3-8) is one of si x registers that
comprise each of the 32 possible subchannels. Each OF-
register consists of eight fast-access flip-flops, OFO through
OF7. Bit positions OFO through OF2 contain the three LSB's
of the current byte address. The 16 MSB's of the byte ad-
dress are contained in the BA-register (see paragraph 3-12).
Bit positions OF3 through OF7 contain operating flags. The
flags in bits OF3, OF5,
and OF6 are duplicates of the flags
specified in the command doubleword. Bit OF4 is the back-
ward (BK) flag. This flag is set during an order-out service
3-8
cycle if the order bits of the command doubleword specify a
read backward order. Figure 3-37 shows how the three LSB's
of the byte address (bits OFO through OF2) and the four
flags in bits
OF3 through OF6 are set. Bit OF7 contains the
transmission error
halt (TEH) flag. This flag is set during a
data-in service cycle if an error condition is detected too
late in that service cycle for the MIOP to report error halt
to the device by means of a terminal order. In effect, the
error is recorded by the TEH flag until the next communi-
cation with that device, at which time the error condition
may
be used to halt the device.
The OF- and IS-registers share the same input data lines
and the same output data lines. The OF-register is ad-
dressed when LS2 is faI see

SDS 901515
ADDER
I I
BA-LINES
I
BAXADD NLSO
BAXADD LSO
l BA-REGISTER
1 CA-REGISTER
901515A. 306
Figure 3-6. BA- and CA-Register Inputs
ADDER
I
I BC-LINES
I
BCXADD NLSI
BCXADD LSI
! BC-REGISTER ! FS-REGISTER
FS-REGISTER FORMAT
BIT POSITION
BIT POSITION
o- DATA CHAIN (DC)
8 - INCORRECT LENGTH (IL)
9 - TRANSMISSION DATA ERROR (TE) 1 - INTERRUPT ON ZERO BYTE COUNT (IZC)
2 - COMMAND CHAIN (CC)
3 - INTERRUPT ON CHANNEL END (ICE)
10 - TRANSMISSION MEMORY ERROR (TMP)
11 - MEMORY ADDRESS ERROR (MAE)
4 - HALT ON TRANSMISSION ERROR (HTE)
5 - INTERRUPT ON UNUSUAL END (IUE)
6 - SUPPRESS INCORRECT LENGTH (SIL)
7 - SKIP (S)
12 -lOP MEMORY ERROR (CMP)
13 -lOP CONTROL ERROR (CE)
14 -lOP HALT (lOP UE)
15 -CHAINING MODIFIER (CM)
Figure 3-7. BC- and FS-Register Inputs
901515A.307
3-9

Paragraphs 3-16 to 3-17
SDS 901515
H-REGISTER
I
OFXH NLS2
1 OF-REGISTER
OF-REGISTER FORIvtAT
BIT POSITION
o- BYTE ADDRESS (BA2)
1 -
BYTE ADDRESS (BA 1)
2 - BYTE ADDRESS (BAO)
3 - SKIP (S)
4 - BACKWARD
(BK)
5 - HALT ON TRANSMISSION ERROR (HTE)
6 - DATA CHAIN (DC)
7 - TRANSMISSION ERROR HALT (TEH)
tOF UNES
I
OFXH LS2
! IS-REGISTER
IS-REGISTER FORIvtAT
BIT POSITION
o- ZERO COUNT INTERRUPT (ZCI)
1 - CHANNEL END INTERRUPT (CEI)
2 - UNUSUAL END INTERRUPT (UEI)
3-
4 - DEVICE NO. 23
5 - DEVICE
NO. 22
6 - DEVICE NO. 21
7 - DEVICE NO. 20 901515A.308
Figure 3-8. OF- and IS-Register Inputs
3-16 IS-Register
The IS-regi ster (see fi gure 3-8) is one of six registers that
comprise each of the 32 possible subchannels. Each IS-
register consists of eight fast-access flip-flops, ISO through
IS7. Bits ISO through IS2 contain the interrupt status.
These three flags are sent to the CPU as part of the status
information during an AlO instruction. The flags are up-
dated as shown in figure 3-41 during an order-in service
cycle. Bit IS3 is not used. Bits IS4 through IS7 contai n the
address of the last successfully started (by means of an SIO)
device connected to the device controller associated with
this subchannel. This address pertains only to subchannels
associated with multiunit device controllers. All devices
controlled by a multiunit device controller share the sub-
channel assigned to that devi ce controll er. It is, therefore,
possible that the information stored in the subchannel is for
a
devi ce other than the one requesti ng an interrupt. During
an SIO instruction, the address in the IS-register is com-
pared with the address presently being offered to the MIOP
by the interrupti ng devi ceo If they compare, the i nforma-
tion stored in the subchannel is for that device, and can be
sent to the CPU.
Both the input data I ines and the output data I ines are
shared by the OF-register. The IS-register is addressed
when LS2 is true.
3-10
3- 17 F-Regi ster
The F-register (see figure 3-9) consists of six buffered latch
flip-flops, FO through F5. Flip-flops FO, and F2 through
F5 accept decoded information from the three CPU function
code lines, FNCO through FNC2, and provide on a single
function indicator line, the function to be performed (SIO,
HIO, TIO, TDV, or AIO). Function indicator line ASC is
controlled by Fl. Flip-flop Fl is set when one or more
device controllers drive the service call (SC) line true.
The F-register flip-flops are reset by signal FXO. Signal
FNT is
true during a CPU-initiated function that is addressed
to this MIOP.
The function code lines are decoded by the function code
decoding logic as follows:
SIO
Function Code Li ne ~
FNCO o
FNCl
o
FNC2
o
Instruction
TIO TDV
iffi ill}
o o
o
o
HIO AIO
@ JEQL
o
o

SDS 901515 Paragraphs
3-18 to 3-21
3-18 H-Register
The H-register (see fi gure 3-10) consists of eight buffered
latch flip-flops, HO through H7. The H-register is used
primari Iy as a temporary storage register for the data in
the OF- and IS-registers while the data is operated on.
Figure 3-46 shows how the H-register is used with the J-
register to increment or decrement the byte address during
a data-in service cycle. The H-register is the only input
to the OF- and IS-registers.
3-19 J-Register
The J-register (see figure 3-10) consists of three buffered
latch flip-flops, JO through J2. The J-register is used to
increment the H-register when signal HXJP1 is true and
decrement it when signal HXJM1 is true. Signal HXJM1
is true only when a device is performing a read backward
operation. Signal HXJP1 may be true when a device is
performing a read (forward) or write operation. The three
upper bits of the H-register (HO through H2) are cleared
by signal HUXO, and the five lower bits (H3 through H7)
are cleared by signal HXO.
3-20 I-Register
The I-register (see figure 3-11) consists of nine buffer
latches, IO through 17, and IP. The I-register accepts data
from the device controller as shown in figure 3-46. Bit IP
is also controlled by signal DAP during a data-in service
cycle if the device is capable of transmitting a parity bit.
If the device is not mechanized to check parity, the device
controller drives the parity check (PC) I ine true. Thi s
causes the MIOP to ignore the parity information supplied
by the device controller. During an order-in service cycle,
the operational status byte from the device controller is set
into bi ts IO through 17 for subsequent storage in the sub-
channel registers ~y means of the H-re.gister, and the C-
register and adder. During a data-in service cycle, the
input data in the I-register is transmitted to the M-register
for subsequent writing into core memory.
During an output operation (data out or order out), the
I-register receives the data or order from core memory by
means of
the M-register and 1MB buffers, and sends it to
the O-register where it is available to the data lines and
thus the device controller. Figure 3-43 shows the processing
of output data. The I-register is cleared by signal IXO.
3-21 O-Register
The O-register (see figure 3-12) is a nine-bit register made
up of buffer latches 00 through 07, and OP. The 0-
register is used only during output operations and during the
termination phase of input operations. During an order-out
service cycle, bits 00 through 07 receive the order from
the I-register and transmit it to the device controller by
means of the data lines. The parity bit (OP) is not used in
this case. During a data-out service cycle, bits 00 through
07 receive the byte of data from the I-register. If the eight
bits of data in the I-register are an even number, signal
IEVEN will be true and will cause parity bit OP to be set.
The data byte set on the data lines (DAO through DA7), and
the data parity line (DAP) will, therefore, have odd parity.
FUNCTION CODE (FNCO-FNC2)
,
FUNCTION CODE
DECODING LOGIC
SERVICE CAlL (SC) I
I FNT
F-REGISTER FORMAT
BIT
POSITION
o - AIO
1 - ASC
2 - HIO
3 - SIO
4 - TIO
NFNT !
), -I _--1....-------,.
5 - TDV
~g~2 51 F-REGISTER
, ,
t
FXO
I
CLEAR F
Figure 3-9. F-Register Inputs
901515A. 309
3-11

3-12
SDS 901515
M-REGISTER (MEMORY DATA)
INTERRUPT ____ OXTORD ___ ~
STATUS
CLEAR HO-H2
PH6Dl T1 r<TORD OF 7 + NTORD EH)
BITS 5 6 7
H-REGISTER
r-:(BKWD ORD)
I t CLEAR H3-H7
~--~~~I H~O
HJXOFJ
I .
I",.,!", "..I,I
HXJP1
HXJMl
Y T T OF/IS REGISTER
I PH13Dl TO HJXOF
JXH rI A-REGISTER
W (DEVICE ADDRESS)
4 5 6 7
J-REGISTER
Fi gure 3-10. H- and J -Regi ster Inputs
1MB BUFFERS
I ,DATA LINES}
IXMB (DAO-DA7) FROM DEVICE
j
DATA PARITY CONTROLLER
IXDA (DAP)
1 IxbA
~I ------------~----~~--~I~
+
IXO
I
CLEAR I
Fi gure 3-11. I-Register Inputs
901515A. 310
901515A. 311

SDS 901515 Paragraph
3-22
CLEAR 0 AND OP
I
Of
0
I EVEN
I
I, 1jt t:~ (ORDOUr + our NCMD)
BC2
ZBC NBCO
'------ZBC BCl + ORDIN 13 BC3 + ORDIN 14 BC5
+ ORDIN 13 EH BC5
901515A.312
Fi gure 3-12. O-Register Inputs
During the termination phase of both input and output
operations, the terminal order is assembled in bits 00
through 04 of the O-regi ster. Bits 05 through 07 and
OP are not used. The O-register is cleared by signal OXO.
3-22 S-Register
The S-register (see figure 3-13) consists of 17 buffer latches,
S15 through S31. Th is register drives the 17 address lines
to core memory. Bit S31 is the LSB of the word address and
bi t S15 is the MSB. Duri ng a CP U function, when the
MIOP must read core memory location X'20', it clears the
S-register and brings up signal SX20. This signal forces a
one into the sixth LSB (S26), therefore specifying location
X'20'. When the MIOP is required to respond to a CPU
function by writing into location X'20' and X' 21
1,
it first
specifies location X'20' as before, and stores
the first word.
Then, to store
the second word, the MIOP forces a one into
the LSB (S31). With S31 and S26 true and the rest of the
S-register bits false, location X' 21
1 will be
written into
when the next memory request is made.
During an order-out service cycle, the MIOP first clears the
S-register and then transfers the command doubleword ad-
dress to bits S15 through S30, leaving bit S31 (the LSB) false.
When a memory request is made, the first word of the com-
mand doubleword is read out of memory. After the MIOP
processes the first word, it forces bit S31 true and makes
another memory request. The second word of the command
doubleword, stored in an odd-numbered memory location,
is therefore read out of memory.
During a data-in or data-out service cycle, the byte address
MSB's from the BA-register are transferred into bits S15
through S30. The LSB of the word address, which is the third
LSB of the total byte address, is stored in the OF-register.
It is transferred to bit S31 by means of the J-register, where
it is updated after every fourth byte has been processed, as
shown in figure 3-46. (See paragraph 3-12.)
3-13