Scientific data systems 8271 User manual

TeCHNICAL MANUAL
MULTIPLEXING
INPUT/OUTPUTPROCESSOR
MODELS
8271/8471 AND 8272/8472
SCIENTIFIC CATA SYSTEMS

TECHNICAL MANUAL
MULTIPLEXING
I'NPUT jOUTPUT PROCESSOR
MODELS 8271/8471 AND 8272/8472
May 1968
SDS 901515A
$5.25
SCIENTIFIC DATA SYSTEMS. 1649 Seventeenth Street. Santa Monica, Calif .• [phone]
<9
1968, Scientific Data Systems, Inc.

Effective Pages
SDS 901515
I LIST OF EFFECTIVE PAGES
I
I
Total number of pages is 156, as follows:
A
Page No.
Issue
Title. • • • • • . . • . • • . . • . • • . •• Original
A .•..••••.•.••.••••..• Original
i thru iv. • • • • • • • • • • . . • . • • .• Original
1-1 thru 1-2 • • . . . • . . • .• • • • •• Original
2-1 thru 2-2 ••..••.•.• '. . . • •• Origina I
3 -1 thru 3-142 •••.•.•..•.•.. Orig ina I
4-1 thru 4-4 • • . • . . . • . • . . • . •• Original
Page No. Issue

Section
II
III
SDS 901515
CONTENTS
Title
GENERAL DESCRIPTION
1 -1
1-2
1-3
1-4
Introduction •.•••.••.•...•..•.•..•....••..•••.•....•..•...•.•...
Physica I Description •.••.•.••••.....•.•.••..••••••.•.•.•..•••. 0 •••
FunctionaI Description ••.•••••.••• 0 •••• 0 ••••••••••••••••• 0 ••• 0 •••••
Specifications and Leading Particulars •••..•••.......•••..•••.•..••.•..•.
OPERATION AND PROGRAMMING •• 0 0 •••••••• 0 0 ••••• 0 ••••••••••••• 0 •• 0 ••••• 0
2-1
General
PRINCIPLES OF OPERATION 0 0 ••••••••••••••••••••••• 0 •• 0 0 ••• 0 • 0 ••••••••••••
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Introduction 0 0 ••••••••••••••• 0 ••••••••• 0 0 0 •••••••••••••••••••••
Genera I Principles of Operation ••.••.••.•.•.•.•...••••••••••••..•......
Genera I ••...••...•••.•..••...•...•...•••••.••••••.••......
Overa II Operation ....••....•••••••••.••..•••••..•.•.•.•••••....
Interrupt Ca lis .••.••.•• 0 •••••••••••• 0 •••••••••••••••••••••
Chaining ..•...•••..... 0 ••••••••••••••• 0 •••••••••••••• 0 ••
Detailed Principles of Operation •••.•..••••.•.••..••••.••.•.... 0 0 • 0 0 0 0 •
MIOP Registers 0 0 0 0 •••• 0 0 • 0 0 0 0 0 •• 0 0 0 0 • 0 00 •• 0 0 • 0 ••• 0 •• 0 0 • 0 0 ••• 0
A-Register. 0 • 0 0 •• 0 0 • 0 0 0 0 0 0 •••• 0 •• 0 • 0 •••• 0 • 0 0 0 •• 0 •• 0 0 • 0 0 • 0
C-Register 0 0 0 0 •• 0 • 0 •••• 0 •• 0 •• 0 0 • 0 0 • 0 •• 0 • 0 •••••••••• 0 •••••
CA-Register ••••••••••.•.. 0 •••• 0 •••• 0 ••••••••• 0 •••••••• 0 ••
BA-Register .• 0 •••••••••• 0 0 •••••• 0 ••• 0 • 0 0 ••••••••••••••• 0 •
BC -Register .• 0 • 0 ••••• 0 ••••••••••••••••••••••••• 0 •••••••••
FS-Register .....•.••.. 0 •••••• 0 •••••• 0 •••••••••• 0 0 ••••••••
OF-Register ........••......•..•.•.. ' ........•.•.•......••.
IS-Register .•......••••........•.••..•.•...•....•..••.•..
F-Register •.....•..•..•..•••.........••.•.........•.•....
H-Register ......•.......•....•..•...........•...........•
J -Register . . . . • . . . . . . • . • . . • • . . . • . . • . . . . . . • . . • . . . . . . . . . . . .
I-Register
.•.........••.•..•..••..•.••..•..••......•..•..
O-Register .•....•...••.•..•.....•.••.••••.••.....•....•..
S-Register • . . . . • . . . . . . . . • • • • . . . . • • . • • • • . . • . • • • • . . • • . . . . . .
M-Register
......••...•..•.••....•.•.••.•••..••...•..•...•
W-Register ...•.•..•..••••.••..•....••.•...••.•..........•
Adder ....•••••..••••••.••..•.......•...•...••.............
Typica I I/O Operation Starting With an SIO Instruction ....•................
I/O System Interface Connections ...••.....•...•.. ~ ..•..•..•........
MIOP Interface Signa Is ........••.•..............................
MIOP/Memory Interface ....•........•...•.•.••...............
MIOP/CPU Interface ..•.•.....••..•.•...•..••....•.......•..
MIOP /Dev ice Contro II er Interface ••.•...••..•.•..••....•........
Subchannel Addressing ...••••.•.•..••......•..•..•••............
MIOP Timing Signals ...••.........•..•...•...•....•.......•....
Delay Line Operation .......•.•.•.......•.•..................
Phase Latches .•...••••••.•....•....•.•••..................
Phase Sequences ...........•.•...•.......•..•................•
SIO Instruction ....•••.••••....•••..•.•.•.•••••.••.....•.••
HIO, TIO, and TDV Instructions ••..••..•..••.•.•....••.•........
AIO Instruction ..•...•....•...•..........•...••.•..••......
Contents
Page
1-1
1 -1
1-1
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2-1
2-1
3-1
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Contents -Tables-Illustrations
SDS 901515
Section
IV
Table
1 -1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
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3-15
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4-1
4-2
Figure
1-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
ii
CONTENTS (Cont.)
Title·
3-40 Order-Out Service Cyc Ie .••••••••.••••••••••••••••.••..•••.••
3-41 Order-In Service Cycle .•••••••••••..•.•...•••.••••..•...•.••
3-42 Data-Out Service Cycle •••••••.•.•••.••..••.••••••••••••...••
3-43 Data -In Service Cyc Ie •.•••••••.••••.••.••••••..•••••••••••••
3-44 Glossary ••••••••••••••••••.••••.•••••.••••••••••••.•••••••..••
MAINTENANCE AND PARTS LIST •••••••••••••••••••••••••••••••••••••••.••••
4-1 General ••••••.••••••••••••.•••••••.•••.••••••...•••.••••••.••
4-2 Preventive /lkintenance •.••.•.•••••....••.•..•••..••..•••••••.•••••
4-3 ExternaI VisuaI Inspection •.•.••••••••.•••••••••••••••••.•••.••••.
4-4 InternaI VisuaI Inspection ..•••..•••.•.••••••••.•••••..•••.•.••••.
4-5 MIOP Test Programs •..•..•••..••••.•.•.•.•••.•.•.••••••.....•••
4-6 Parts List Table •••.•..•••.••.•••.••.••••••.•.•••••••••.•.••••••.•
TABLES
Title
Genera I Specifications ••.••••••.••••••••••••.•••••.•••••••••••••.•..•••••.
MIOP/Memory Interface Signals •••••.•••••••••••••••.••• ~ ••••••••.•.•.•••••••
MIOP/CPU Interface Signals .•.•.••••.••••••••••••••••••.•••.•.••••••.••••••
Condition Code Settings •••••..••••.••.•.••••.•.••.•••••••••••••••..•••••.•
MIOP/Device Controller Interface. ..••..••••••••••••.•••••••••••••.•••••••••.•
MIOP/Device Controller Interface Line Utilization ••••••.••••••••.•••.••.•.••.•••.•
Data Input/Output Line Definition ••••..••••••••••.••••••••••••••••.••••••••••
Data Order Request and Input/Output Request Line Definitions •••••••••••••••••••....•.•
Function Response Line Definition ..••••••••••••••.•••.••••••••••.••••••••••••
Coding of End Data and End Service Lines During Data In/Out Operations •••••••••••••••.•••
Permitted Next States of End Data and End Service Lines .••.•.•...•....••..••.•...••..
MIOP/Memory Phase Sequence ••••••.•••••.••.•••••••••.••.••.••••.••••••••.
SIO Instruction Phase Sequence .......•.•.•••••.•••••.••••.•.•••.•.•.•....•••
HIO, TIO, and TDV Instruction Phase Sequence ••••.•.••.•••••••••••••••...•.••..•
AIO Instruction Phase Sequence •••••••.••...•••••••••••••.••••••••..•.•..•...
Order-Out Service Cyc Ie Phase Sequence •..•.••••••••••••••.••.••••••.••.•••••.
Order-in Service eyc Ie Phase Sequence •.••••••••••.••••.••••.•••••••..•.•..•...
Data-Out Service Cycle. Phase Sequence .••••••••••••••••••••••.••••••••••••••••
Data-In Service Cyc Ie Phase Sequence •.•.•••...••••.•..•••••••••.••••.•..•••.•
Glossary of MIOP Signals' ........••••••.•••••••••••••••••.•••••.••••..•..•.
Checkout Programs for MIOP ..•••..•.•••••..••••..••.•••••••.••..••••.••.••.
Multiplexing Input/Output Processor, Replaceable Parts ..••.•••..••••.•••••.•..••....
ILLUSTRA nONS
Title
MIOP Basic and Optiona I Subchannel Locations •••••.•.•••••••••••••••••.••••••..•.
I/O System, Simplified Overall Block Diagram ••••••••••.•••••••••.•••.••.•••.••••
Loading Core Memory Location X'20' During an SIO Instruction ••••••••••••••••••.•.••.•
MIOP Block Diagram •.•.•.•.••••.••••••.•.•••.••.•••••.••••.•••••.•••....
A-Register Inputs •......•••.••.•••••••••.•••.•••••••••••••••••••.••••....
C-Register Inputs •••••••••.•••••.••••••••••.•••.••.•••••••••••.••••••.••
BA- and CA-Register Inputs ••.•••••.••••.•••••••••.•.•••••••••.•••••••••••.•
BC- and FS-Register Inputs •.•••.••••••••••••••••••••••••••••••••••••••.•••.
OF- and IS-Register Inputs ••..•••••.••••••••.••••••••••••••••••••••••••..••
F-Register Inputs •.•.•••......••.••.••••.•.••..•.•••.••.•.•.••.•.•..••..
Page
3-68
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4-1
4-1
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Figure
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4-1
SDS 901515 Illustrations
ILLUSTRATIONS (Cont.)
Title
H- and J -Reg ister Inputs ••••....••.••.••••••••••..•.•••••••••••.•.••.••.•..
I-Register Inputs ••••.•••.•....••••.••••••..•••.•.•••••••••••.•...•.•..••
O-Register Inputs .••.•••.•••.••.•....•••••.••••.•.••••••.•••••..•••.•..•
S-Register Inputs ••••••••••••.•••••••••••••..••.••.•••••••••.•.••.••••.•
M-Register Inputs •••••••••.•..••.•..••.•••••••.••.••.•.•..•••.•..•......
W-Register Inputs ••••.••••.••••...•..••••.•.•••.••••••••••...•••••.....•
Adder, Overall Block Diagram •••.••..•.•.•.•.•.••.•••.•.•••••••.•.•••.•.••..
TypicaI I/O Operation, Overa II Sequence Diagram ••.•••..••.••••.••.•••..•.....•..
Typical I/O Operation, Timing Diagram ...•••.....•.•.•.•.•••.•.....••.••••...•
MIOP, Overall Block Diagram •..•.•••••..•••••••••••••••••••.•••••.•••...•..
I/O System Interconnection Diagram •.•.••••••.•.•.••••••.••....•••••••••......
MIOP/Memory Interface Signal Timing Diagram (Port A or B) •••••••••••••••••••••••••••
Setting Memory Data Release Flip-Flop MDR1 •..••••••...•.•.•••.•••••••••.•......
MIOP Fast Access Memory Organization •••••.•••..••••••.•.•••••.•••••••.••....•
Assignment of Subchanne[ Groups •..••.•. " ..•.• " .•.•••••.•.••••••••••••••••..••.
Decoding the Address Register .•••..•••••••.•.••••.••.••••••••••..••..•.•••.•
Decoding SPA5, SPA6, and SPA7 Address Signals to Select One Subchannel in Group Zero .•••••..
Typical FT25 Fast Access Memory Module •.••••.•.•..•••..•..•••••••..•.•••.•.•.•
Delay Line 1 Logic Diagram ••.•.•••••••.•.•.•.•••••.•..•.••••••.•......•.•.
Delay Line 1 Timing Signals ••..•..•.•••.•••.••..•...•.•.••••.••..•..•.•.•..
Delay Line 2 Logic Diagram ...••..•••.•••.•.•••.•••.•.•••.•....••...•..••.•
Delay Line 2 Timing Diagram ••..•.•.•••••••••.....••.•••..•••..••.••.•.....•
Phase Diagram for SIO, HIO, TIO, and TOY Instructions •.•••..•••..••.•..•.•••••.••.•
Data Flow During an" SIO Instruction ..•••.•••.•••.••••.•.••••••••••..••...•..•.
Phase Diagram for an AIO Instruction •.•.•...•.•.•..•....••••.••.•..•..•........
Phase Diagram for an Order-Out Service Cycle .•••••.••.•.••••.•.•••••..•..••.•..•
Processing a Transfer in Channel Command ..•.•••...••.•..••.••.•.••••.•.....••.•
Processing a Command Doubleword ....••••.•..•...•.•.•.•••••••••.•.•..•.•.•..
Termination Phase of an Order-Out Service Cyc Ie ••....•......•.•.•...•.•••....••..
Phase Sequences For an Order-In Service Cycle ..••..•..•..•..•••.•.••.......•....•
Updating Flags and Status During an Order-In Service Cycle •.••.•••.•..•...••..•..•.•..
Updating Interrupt Status During an Order-In Service Cycle .••..•••••.••••••.•..•.•.•..
Phase Sequence Diagram For a Data-Out Service Cycle ..•••••..•••••••••••.•.•.••....
Processing a Data-Out Service Cyc Ie ..••••...••.•.•..•..•.••••••......•........
Processing Data During a Data-Out Service Cycle, Timing Diagram ••....•...•..•.•.......
Phase Sequence Diagram For a Data-In Service Cycle .•...•.•.•.•.•••....•.•.••..•...
Processing Data During a Data-In Service Cyc Ie ....•...•..••..•.•..•••...•.•......
MIOP Module Location Chart .......••..•....•........•.•••...•..•....••.....
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4-2
iii

Related Publications
iv
SDS 901515
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SDS 901S1S Paragraphs
1- 1 to 1-4
SECTION I
GENERAL DESCRIPTION
1-1 INTRODUCTION
This manual describes SDS Multiplexing Input/Output
Processor (MIOP) Models 8471 and 8271 and optional sub-
channels, Models 8472 and 8272. The manual consists of
four sections that provide general information, program-
ming information, a functional description, maintenance
information, and parts lists.
The MIOP provides
independent control of data transfers
between core memory and certain peripheral devices, and
starts, tests, and acknowledges interrupts
pertaining to
certain peripherals under control of a Sigma S or 7 central
processing unit.
Figure 1-1 shows
the physical layout of the basic MIOP,
Models 8471 (Sigma 7) and 8271 (Sigma S), and the
optional subchannels, Models 8472 (Sigma 7) and 8272
(Sigma S).
Technical manuals describing equipment associated with the
MIOP are referred to in the list of Related Publications in
the front matter of this manual.
1-2 PHYSICAL DESCRIPTION
The basic MIOP consists of 98 modules installed in chassis
A,
S, C, and D, and includes eight subchannels. Each
subchannel accommodates
one device controller. Five
fast-access memory modules (FT25) provide eight sub-
channels. Since one fifth of each subchannel is contained
on each of the five FT25
ls, the
FT25
ls must be
installed in
groups
of five. Three additional groups of FT25
ls provide
a
total of 32 subchannels.
1-3 FUNCTIONAL DESCRIPTION
The MIOP contains input and output data storage registers
and buffers, fast-access memory registers for command mani-
pulation, a timing signal generator, and control logic. The
function
of the MIOP is to control and sequence input and
output operations for a number of peripheral devices simul-
taneously, allowing the CPU to concentrate on program
execution. The active devices time-share the hardware in
the MIOP. Any input-output events that require CPU in-
tervention are brought to the attention of the CPU by means
of the interrupt system. The device controllers and devices
are described in other manuals.
1-4 SPECIFICATIONS AND LEADING PARTICULARS
The general specifications for the MIOP are given in
table 1-1.
Table 1-1. General Specifications
Power requirements (supplied
by PTl6
power supply)
Logic signal levels
Data format
Temperature
Nonoperating:
Operating:
Relative humidity (operating)
Altitude
Nonoperati ng:
Operating:
+8Vdc (9.0 amps)
-8Vdc (2.4 amps)
+4Vdc (20 amps)
Total watts:
171
One, +4Vdci Zero,
Ov (low impedance
to ground) .
8-bit byte, 32-bit
word
-40
0C to
60
0C
(-40
0F to 1400
F)
soC to SOOC
(41°F to 122°F)
1 0'/0 to 9S%
20,000 feet maximum
10, 000 feet maximum
1-1

1-2
SDS 901515
I t- .. ....--SLOTS 1 THROUGH 32
-I
CHASSIS A
CHASSIS B
CHASSIS C
r-----------,
I I
CHASSIS D I I
I I
L ________ -.I
SLOT NO. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
FAST ACCESS MEMO
MODULES (FT25)
SUBCHAN NELS 0 - 7
(BASIC lOP)
RV{
SUBCHANNELS 16-23
(OPTIONAL)
SUBCHANNELS 8-15
(OPTIONAL)
SUBCHANNELS 24-32
(OPTIONAL)
• !~ ~ . .
~ .
. ~
~~ .
~ A~
~ . ~ . •
~~ .
Figure 1-1. MIOP Basic and Optional Subchannel Locations
~ ~ . .
..
I
901515A.101

SOS 901515 Paragraph 2-1
SECTION II
OPERATION AND PROGRAMMING
2-1 GENERAL
The MIOP contains no controls or indicators other than
address switches and switch LASTONE, which is closed on
all MIOPs connected to a CPU except the last one. These
switches are contained on the switch comparator module
(LT26) in slot 13 of chassis C. The module contains eight
switches; the three address switches that apply to the MIOP
are S 1-1, S2-1, and S3-1, and the switch that applies to
signal LASTONE
is S 1-2.
In the Sigma 5 and 7 I/O system, the CPU executes instruc-
tions, the MIOP executes commands, and the I/O device
executes orders. For example, the CPU may execute a
start input/output (SIO) instruction to initiate an I/O
operation. During the course of the operation, the MIOP
fetches a command doubleword (command) from the com-
mand list in core memory and stores it (except the order
bits) in its own fast access memory. The command provides
the MIOP with information needed to perform its functions;
commands are, therefore, executed by the MIOP. The
order bits of the command are transmitted to the device.
The order defines the operation to be performed by the
device; the I/O devices, therefore, execute orders.
For a description of I/O instructions, commands, and
orders, see SDS Sigma 7 Computer Reference Manual
900950 and SDS Sigma 5 Computer Reference Manual
900959.
2-1/2-2