Cypress Semiconductor CY7B991 User manual

CY7B991
CY7B992
Programmable Skew Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-07138 Rev. *B Revised June 22, 2007
Features
■All output pair skew <100 ps typical (250 maximum)
■3.75 to 80 MHz output operation
■User selectable output functions
❐Selectable skew to 18 ns
❐Inverted and non-inverted
❐Operation at 1⁄2 and 1⁄4 input frequency
❐Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
■Zero input to output delay
■50% duty cycle outputs
■Outputs drive 50Ωterminated lines
■Low operating current
■32-pin PLCC/LCC package
■Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
TheCY7B991 and CY7B992ProgrammableSkewClockBuffers
(PSCB)offeruserselectablecontroloversystemclockfunctions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor-
mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
missionlinedelayeffects.When this “zerodelay”capability ofthe
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
Logic Block Diagram
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL) SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 2 of 19
Pin Configuration
Pin Definitions
Signal Name IO Description
REF IReferencefrequencyinput.Thisinputsuppliesthefrequencyandtimingagainstwhichallfunctional
variations are measured.
FB IPLL feedback input (typically connected to one of the eight outputs).
FS IThree level frequency range select. See Table 1.
1F0, 1F1 IThree level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 IThree level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 I Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 IThree level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST IThree level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.
1Q0, 1Q1 OOutput pair 1. See Table 2.
2Q0, 2Q1 OOutput pair 2. See Table 2.
3Q0, 3Q1 OOutput pair 3. See Table 2.
4Q0, 4Q1 OOutput pair 4. See Table 2.
VCCN PWR Power supply for output drivers.
VCCQ PWR Power supply for internal circuitry.
GND PWR Ground.
1234323130
17161514 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F0 FS V REF GND TEST 2F1
FB
2Q1 2Q0
CCQ
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3Q1 3Q0
CCN
V
CCN
V
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B991
CY7B992
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 3 of 19
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
Skew Select Matrix
Theskewselect matrixcontainsfourindependentsections.Each
section has two low skew, high fanout drivers (xQ0, xQ1), and
two corresponding three level function select (xF0, xF1) inputs.
Table 2 showsthenine possibleoutputfunctionsfor eachsection
as determined by the function select inputs. All times are
measured withrespectto the REF inputassumingthattheoutput
connected to the FB input has 0tUselected.
Table 1. Frequency Range Select and tUCalculation[1]
FS[2, 3] fNOM (MHz)
where N =
Approximate
Frequency(MHz)At
Which tU= 1.0 ns
Min Max
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 80 16 62.5
tU1
fNOM N×
------------------------
=
Table 2. Programmable Skew Configurations[1]
Function Selects Output Functions
1F1,2F1,
3F1, 4F1 1F0,2F0, 3F0, 4F0 1Q0,1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
LOW LOW –4tUDivide by 2 Divide by 2
LOW MID –3tU–6tU–6tU
LOW HIGH –2tU–4tU–4tU
MID LOW –1tU–2tU–2tU
MID MID 0tU0tU0tU
MID HIGH +1tU+2tU+2tU
HIGH LOW +2tU+4tU+4tU
HIGH MID +3tU+6tU+6tU
HIGH HIGH +4tUDivideby4 Inverted
Notes
1. For all tri-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V.
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 4 of 19
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in “Skew Select
Matrix” on page 3. For testing purposes, any of the three level
inputs can have a removable jumper to ground, or be tied LOW
through a 100Ωresistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
t
0– 6t U
t
0– 5t U
t
0– 4t U
t
0– 3t U
t
0– 2t U
t
0– 1t U
t
0
t
0+1t U
t
0
t
0
t
0
t
0
t
0
+2t U +3t U +4t U +5t U +6t U
FBInput
REFInput
– 6t U
– 4t U
– 3t U
– 2t U
– 1t U
0tU
+1t U
+2t U
+3t U
+4t U
+6t U
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 5 of 19
Maximum Ratings
Operating outside these boundaries affectsthe performance and
life of the device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................64 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Note
5. Indicates case temperature.
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Industrial –40°C to +85°C5V ±10%
Military[5] –55°C to +125°C 5V ±10%
Military[5] –55°C to +125°C 5V ±10%
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 6 of 19
Electrical Characteristics
Over the Operating Range[6]
CY7B991 CY7B992
Parameter Description Test Conditions Min Max Min Max Unit
VOH Output HIGH Voltage VCC = Min IOH = –16 mA 2.4 V
VCC = Min, IOH =–40 mA VCC–0.75
VOL Output LOW Voltage VCC = Min, IOL = 46 mA 0.45 V
VCC = Min, IOL = 46 mA 0.45
VIH Input HIGH Voltage
(REF and FB inputs only) 2.0 VCC VCC – 1.35 VCC V
VIL Input LOW Voltage
(REF and FB inputs only) –0.5 0.8 –0.5 1.35 V
VIHH Three Level Input HIGH
Voltage (Test, FS, xFn)[10] Min ≤VCC ≤Max VCC – 0.85 VCC VCC – 0.85 VCC V
VIMM Three Level Input MID
Voltage (Test, FS, xFn)[10] Min ≤VCC ≤Max VCC/2 – 500 mV VCC/2 + 500 mV VCC/2 – 500 mV VCC/2 + 500 mV V
VILL Three Level Input LOW
Voltage (Test, FS, xFn)[10] Min ≤VCC ≤ Maximum 0.0 0.85 0.0 0.85 V
IIH InputHIGHLeakageCurrent
(REF and FB inputs only) VCC = Max, VIN = Max. 10 10 μA
IIL Input LOW Leakage Current
(REF and FB inputs only) VCC = Max, VIN = 0.4V –500 –500 μA
IIHH Input HIGH Current
(Test, FS, xFn) VIN = VCC 200 200 μA
IIMM Input MID Current
(Test, FS, xFn) VIN = VCC/2 –50 50 –50 50 μA
IILL Input LOW Current
(Test, FS, xFn) VIN = GND –200 –200 μA
IOS Output Short Circuit
Current[8] VCC = Max, VOUT = GND (25°C only) –250 N/A mA
ICCQ Operating Current Used by
Internal Circuitry VCCN=VCCQ=Max, All Input
Selects Open
Com’l 85 85 mA
Mil/Ind 90 90
ICCN Output Buffer Current per
Output Pair[9] VCCN = VCCQ = Max, IOUT = 0 mA
Input Selects Open, fMAX
14 19 mA
PD Power Dissipation per
Output Pair[10] VCCN = VCCQ = Max, IOUT = 0 mA
Input Selects Open, fMAX
78 104[11] mW
Notes
6. For more information see “Group A Subgroup Testing” on page 17.
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all datasheet limits are achieved.
8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must
not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pairis approximated by the following expression that includes device current plus load current:
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F <C.
10.Total power dissipation per output pair can be approximated by the following expression that includes devicepower dissipation plus power dissipation due tothe load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
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CY7B992
Document Number: 38-07138 Rev. *B Page 7 of 19
Capacitance
CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 5.0V 10 pF
AC Test Loads and Waveforms
TTL AC Test Load (CY7B991) TTL Input Test Waveform (CY7B991)
5V
R1
R2
CL
R1
R2
CL
CMOS AC Test Load (CY7B992)
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
≤1ns ≤1ns
2.0V
0.8V
Vth =1.5V
80%
Vth =V
CC/2
20%
0.0V
≤3ns ≤3ns
80%
20%
Vth =V
CC/2
CMOS Input Test Waveform (CY7B992)
VCC
R1=130
R2=91
CL=50pF(C
L=30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
R1=100
R2=100
CL=50pF(C
L
(Includes fixture and probe capacitance)
VCC
=30 pF for –2 and –5 devices)
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Document Number: 38-07138 Rev. *B Page 8 of 19
Switching Characteristics Over the Operating Range[2, 13]
CY7B991–2[14] CY7B992–2[14]
Parameter Description Min Typ Max Min Typ Max Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2 , 3] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Pulse Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.05 0.20 0.05 0.20 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18,19] 0.1 0.25 0.1 0.25 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19] 0.25 0.5 0.25 0.5 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19] 0.3 0.5 0.3 0.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19] 0.25 0.5 0.25 0.5 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19] 0.5 0.9 0.5 0.7 ns
tDEV Device-to-Device Skew[14, 21] 0.75 0.75 ns
tPD Propagation Delay, REF Rise to FB Rise –0.25 0.0 +0.25 –0.25 0.0 +0.25 ns
tODCV Output Duty Cycle Variation[22] –0.65 0.0 +0.65 –0.5 0.0 +0.5 ns
tPWH Output HIGH Time Deviation from 50%[23, 24] 2.0 3.0 ns
tPWL Output LOW Time Deviation from 50%[23, 24] 1.5 3.0 ns
tORISE Output Rise Time[23, 25] 0.15 1.0 1.2 0.5 2.0 2.5 ns
tOFALL Output Fall Time[23, 25] 0.15 1.0 1.2 0.5 2.0 2.5 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
Notes
12.CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
13.Test measurementlevels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
14.Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
15.Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
16.SKEW is definedas the time between theearliest and the latest output transition among all outputs for which the same tU delay is selected when all areloaded
with 50 pF and terminated with 50Ωto 2.06V (CY7B991) or VCC/2 (CY7B992).
17.tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18.tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19.CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
20.There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
Divide-by-2 or Divide-by-4 mode).
21.tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
22.tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23.Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ωto
2.06V (CY7B991) or VCC/2 (CY7B992).
24.tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
25.tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992.
26.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits.
This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B Page 9 of 19
Switching Characteristics
Over the Operating Range[2, 13] (continued)
CY7B991–5 CY7B992–5
Parameter Description Min Typ Max Min Typ Max Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2 , 3] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Pulse Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18] 0.25 0.5 0.25 0.5 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19] 0.6 0.7 0.6 0.7 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19] 0.5 1.0 0.6 1.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19] 0.5 0.7 0.5 0.7 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19] 0.5 1.0 0.6 1.7 ns
tDEV Device-to-Device Skew[14, 21] 1.25 1.25 ns
tPD Propagation Delay, REF Rise to FB Rise –0.5 0.0 +0.5 –0.5 0.0 +0.5 ns
tODCV Output Duty Cycle Variation[22] –1.0 0.0 +1.0 –1.2 0.0 +1.2 ns
tPWH Output HIGH Time Deviation from 50%[23, 24] 2.5 4.0 ns
tPWL Output LOW Time Deviation from 50%[23, 24] 34.0 ns
tORISE Output Rise Time[23, 25] 0.15 1.0 1.5 0.5 2.0 3.5 ns
tOFALL Output Fall Time[23, 25] 0.15 1.0 1.5 0.5 2.0 3.5 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
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Document Number: 38-07138 Rev. *B Page 10 of 19
Switching Characteristics
Over the Operating Range[2, 13] (continued)
CY7B991–7 CY7B992–7
Parameter Description Min Typ Max Min Typ Max Unit
fNOM Operating Clock
Frequency in MHz FS = LOW[1, 2] 15 30 15 30 MHz
FS = MID[1, 2] 25 50 25 50
FS = HIGH[1, 2] 40 80 40 80[15]
tRPWH REF Pulse Width HIGH 5.0 5.0 ns
tRPWL REF Pulse Width LOW 5.0 5.0 ns
tUProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17] 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)[16, 18] 0.3 0.75 0.3 0.75 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19] 0.6 1.0 0.6 1.0 ns
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19] 1.0 1.5 1.0 1.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19] 0.7 1.2 0.7 1.2 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19] 1.2 1.7 1.2 1.7 ns
tDEV Device-to-Device Skew[14, 22] 1.65 1.65 ns
tPD Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 –0.7 0.0 +0.7 ns
tODCV Output Duty Cycle Variation[22] –1.2 0.0 +1.2 –1.5 0.0 +1.5 ns
tPWH Output HIGHTimeDeviation from 50%[23,24] 35.5 ns
tPWL Output LOW Time Deviation from 50%[23, 24] 3.5 5.5 ns
tORISE Output Rise Time[23, 25] 0.15 1.5 2.5 0.5 3.0 5.0 ns
tOFALL Output Fall Time[23, 25] 0.15 1.5 2.5 0.5 3.0 5.0 ns
tLOCK PLL Lock Time[26] 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter RMS[14] 25 25 ps
Peak-to-Peak[14] 200 200 ps
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