Hitachi H8S/2215 Series User manual

Hitachi Single-Chip Microcomputer
H8S/2215 Series
Hardware Manual
ADE-602-217B
Rev. 3.0
10/04/02
Hitachi Ltd.

Rev. 3.0, 10/02, page ii of lviii
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Rev. 3.0, 10/02, page iii of lviii
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the operation
of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.

Rev. 3.0, 10/02, page iv of lviii

Rev. 3.0, 10/02, page v of lviii
Configuration of this Manual
This manual comprises the following items:
1. Precautions in Relation to this Product
2. Configuration of this Manual
3. Overview
4. Table of Contents
5. Summary
6. Description of Functional Modules
• CPU and System-Control Modules
• On-chip Peripheral Modules
The configuration of the functional description of each module differs according to the module.
However, the generic style includes the following items:
i) Features
ii) I/O pins
iii) Description of Registers
iv) Description of Operation
v) Usage: Points for Caution
When designing an application system that includes this LSI, take the points for caution into
account. Each section includes points for caution in relation to the descriptions given, and points
for caution in usage are given, as required, as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
• Product-type codes and external dimensions
• Major revisions or addenda in this version of the manual (only for revised versions)
The history of revisions is a summary of sections that have been revised and sections that have
been added to earlier versions. This does not include all of the revised contents. For details,
confirm by referring to the main description of this manual.
10.Appendix/Appendices

Rev. 3.0, 10/02, page vi of lviii

Rev. 3.0, 10/02, page vii of lviii
Preface
This LSI is a high-performance microcomputer (MCU) made up of the H8S/2000 CPU with
Hitachi's original architecture as its core, and the peripheral functions required to configure a
system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the H8/300,
H8/300L, or H8/300H user to easily utilize the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, a direct memory access controller (DMAC), a bus master
for a data transfer controller (DTC), a 16-bit timer pulse unit (TPU), an 8-bit timer (TMR), a
watchdog timer (WDT), a universal serial bus (USB), two types of serial communication interfaces
(SCIs), an A/D converter, a D/A converter, and I/O ports as on-chip peripheral modules for system
configuration.
A single-power flash memory (F-ZTATTM) version and masked ROM version are available for this
SI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
This manual describes this SI's hardware.
Note: * F-ZTATTM is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2215 Series in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2215 Series to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

Rev. 3.0, 10/02, page viii of lviii
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in Appendix A,
On-Chip I/O Register.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
H8S/2215 Series manuals:
Manual Title ADE No.
H8S/2215 Series Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083
User's manuals for development tools:
Manual Title ADE No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User’s Manual ADE-702-247
H8S, H8/300 Series Simulator Debugger (for Windows) Users Manual ADE-702-085
H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial ADE-702-231
Hitachi Embedded Workshop User's Manual ADE-702-201

Rev. 3.0, 10/02, page ix of lviii
List of Items Revised or Added for This Version
Section Page Description
1.1 Overview
• On-chip memory
• ComPact Package
1
ROM Product Code ROM RAM Remarks
HD64F2215 256 kbytes 16 kbytes SCI boot version
F-ZTAT Version HD64F2215U 256 kbytes 16 kbytes USB boot version
HD6432215A 256 kbytes 16 kbytes In planning
HD6432215B 128 kbytes 16 kbytes 
Masked ROM
Version
HD6432215C 64 kbytes 8 kbytes 
Remarks column amended
(Incorrect) Under development
(Correct) 
1.2 Internal Block
Diagram
Figure 1.1 Internal Block
Diagram
2 Figure amended
Interrupts controller
USB
NMI
FWE*
USPND
USD+
USD-
VBUS
Note added to figure
Note: * The FWE pin is only provided in the flash memory
version.
1.3 Pin Arrangement
Figure 1.2 Pin
Arrangement (TFP-120)
3Figure amended
74 73 72 71 70 69 68 67
XTAL VSS
NMI FWE* MD1 MD0
Note added to figure
Note: * The FWE pin is only provided in the flash memory
version.

Rev. 3.0, 10/02, page x of lviii
Section Page Description
1.3 Pin Arrangement
Figure 1.3 Pin
Arrangement (BP-112)
4Figure replaced
1
A
B
C
D
E
F
G
H
J
K
L
23456789 1110
BP-112
(Top view)
PA1/
A17/TxD2
PA2/
A18/RxD2
P10/
TIOCA0/
A20/VM
P11/
TIOCB0/
A21/VP
PA3/
A19/
SCK2/
SUSPND
P12/
TIOCC0/
TCLKA/
A22/RCV
P13/
TIOCD0/
TCLKB/
A23/VPO
P14/
TIOCA1/
P15/
TIOCB1/
TCLKC/
FSE0
P16/TIO
CA2/
P17/
TIOCB2/
TCLKD/
P97/
AN15/DA1
P96/
AN14/
DA0
P70/
TMRI01/
TMCI01/
P72/
TMO0/
P73/
TMO1/
P35/
SCK1/
PF3///
P74/
P32/
SCK0/
PF0/ /
(Reserve)
PD1/D9
PD4/D12
PD7/D15
VSS
PC3/A3
PC6/A6
PB1/A9
PB4/A12
PB7/A15
(Reserve)
PE6/D6
PD0/D8
PD3/D11
PD6/D14
PC1/A1
PC4/A4
PC7/A7
PB3/A11
PB6/A14
PE3/D3
PE5/D5
PE7/D7
PD5/D13
PC0/A0
PC2/A2
PB0/A8
PB5/A13
PA0/A16
PE0/D0
PE2/D2
PE4/D4
PD2/D10
VCC
PC5/A5
PB2/A10
TMS
TDI
PE1/D1
AVSS
PG4/
TDO
PG3/
TCK
P42/AN2
P43/AN3
PG1/
/
PG2/
PG0
USPND
Vref
P40/AN0
P41/AN1
P71/
MD2
NMI
PLLVCC
DrVCC
VBUS
AVCC
P36
PF5/
XTAL
MD0
DrVSS
USD+
P34/RxD1
P33/TxD1
P30/TxD0
PF2/
PF6/
EXTAL
VSS
MD1
XTAL48
PLLVSS
USD-
(Reserve)
P31/RxD0
PF1/
PF4/
PF7/
VCC
FWE*
EXTAL48
PLLCAP
(Reserve)
Note added
Note: *The FWE pin is only provided in the flash memory
version.
1.5 Pin Functions 11 Table amended
Pin No.
Type Symbol TFP-120 BP-112 I/O Function
System
Control FWE 69 H11 Input Pin for use by flash memory. This pin is only used in the flash memory
version. In the mask ROM version it
should be fixed at 0.
3.4 Memory Map in Each
Operating Mode
Figure 3.1 Memory Map
in Each Operating Mode
for HD64F2215,
HD64F2215U,
and HD6432215A
61 Description amended
Figures 3.1 to 3.3 show the memory map in each operating
mode for HD64F2215, HD64F2215U, HD6432215A,
HD6432215B, and HD6432215C.
5.4.1 External Interrupts
Figure 5.2 Block Diagram
of Interrupts IRQ7 to IRQ0
83 Figure amended
(Incorrect) IRQn input
(Correct) IRQn input

Rev. 3.0, 10/02, page xi of lviii
Section Page Description
7.1 Features
Figure 7.1 Block Diagram
of DMAC
142 Figure amended
Internal interrupts
TGI0A
TGI1A
TGI2A
TXI0
RXI0
TXI1
RXI1
ADI Control logic
7.4.9 DMAC Bus Cycles
(Dual Address Mode) 182, 184 Note added
Note: *TEND output cannot be used with this LSI.
9.1.4 Pin Functions
Table 9.8 P11 Pin
Function
224 Address amended
(Incorrect) Other than (B’1111)
(Correct) Other than (B’1110 to B’1111)
Table 9.9 P10 Pin
Function Address amended
(Incorrect) Other than (B’1111)
(Correct) Other than (B’1101 to B’1111)
9.2.5 Pin Functions
Table 9.13 P33 Pin
Function
227 Pin function amended
TE 0 1
P33DDR 0 1
Pin function P33 input P33 output TxD1 output
Table 9.16 P30 Pin
Function 228 Pin function amended
TE 0 1
P30DDR 0 1
Pin function P30 input P30 output TxD0 output
9.8.3 Port C Register
(PORTC) 244 Note added
Note: *Determined by the states of pins PC7 to PC0.
10.1 Features
Table 10.1 TPU
Functions
265 Channel 0 amended
Item Channel 0 Channel 1 Channel 2
General registers/buffer
registers TGRC_0
TGRD_0 not possible not possible

Rev. 3.0, 10/02, page xii of lviii
Section Page Description
13.3.9 Serial Extended
Mode Register 0
(SEMR_0)
Figure 13.3 Examples of
Base Clock when Average
Transfer Rate is Selected
375 Figure amended
12345678910 123 45 678
11 12 13 14 15 16 17 18 19 20 21 2322
12 345 67 8
242512 5678
12
11
34
14
567
18
8
20 21 22 23 24
1234
2534
8 MHz
Base clock
16 MHz/2 = 8 MHz
8 MHz ×(47/51)= 7.3725 MHz
(average) 7.3725 MHz
1 bit = base clock ×16*
1234567891011121314151617 123456789101112 13141516
18 19 20 21 2322 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1
1234 56789101112131415 16 1234 56789101112131415 16
234567828 29
8 MHz
Base clock
16 MHz/2 = 8 MHz
8 MHz ×(18/25)= 5.76 MHz
(average)
Base clock with 460.784 kbps average transfer rate
Average transfer rate = 7.3725 MHz/16= 460.784 kbps Average error = -0.004% Average transfer rate = 5.76 MHz/8= 720 kbps Average error = ±0%
Base clock with 720 kbps average transfer rate
5.76 MHz
1 bit = base clock ×8*
12 345 67 8
123
2 MHz
1.8431 MHz
1 bit = base clock ×16*
Base clock
16 MHz/8 = 2 MHz
2 MHz ×(47/51)= 1.8431 MHz
(average)
4567891011121314151617
123456789101112 13141516
26 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8
1234567 1234567
18 19 20 21 2322 24 25 27 30 31 32 33 3428 29
1234 65 7 8 9 12 13 14 15 1610 11 1234 65 7 8 9 12 13 14 15 1610 11
When ø = 16 MHz Base clock with 115.196 kbps average transfer rate
Average transfer rate = 1.8431 MHz/16= 115.196 kbps Average error = -0.004%
Note:
*
As the base clock synchronization varies, so does the length of one bit.

Rev. 3.0, 10/02, page xiii of lviii
Section Page Description
Figure 13.4 Example of
Average Transfer Rate
Setting with TPU Clock
Input
374 Newly added
Example for 921.6 kbps when ø = 16 MHz Generation of clock with 923.077 kbps average transfer rate by means of TPU (1) An 8 MHz base clock provided by TPU_1 is multiplied by 12/13 by TPU_2 to generate a 7.3846 MHz base clock (2) By making 1 bit = 8 base clocks, the average transfer rate is made 7.3846 MHz/8 = 923.077 kbps. Sample TPU and SCI settings
TMDR_1 = TMDR_2 = H'C2 [PWM mode 1] TCR_1 = H'20 [TCNT_1 incremented on rising edge of ø/1, TCNT_1 cleared by TGRA_1 compare match] TGRB_1 = H'0000, TGRA_1 = H'0001 TIOR_1 = H'21 [1 output on TGRB_1 compare match, TIOCA1 initial output 0, 0 output on TGRA_1 compare match] TCR_2 = H'2C [TCNT_2 incremented on falling edge of TCLKA (TIOCA1), TCNT_2 cleared by TGRA_2 compare match] TGRB_2 = H'0000, TGRA_2 = H'000C TIOR_2 = H'21 [1 output on TGRB_2 compare match, TIOCA2 initial output 0, 0 output on TGRA_2 compare match] SEMR_0 = H'0C (ABCS = 1, ACS2-0 = B'100)
Main clock: 16 MHz
TIOCA1(TPU_1) output = 8 MHz
TIOCA2 (TPU_2) output
Internal base clock
= 8 MHz x 12/13
= 7.3846 MHz
1 bit = 8 base clocks*
Average transfer rate = 7.3846 MHz/8 = 923.077 kbps
Average error relative to 921.6 kbps = +0.16%
Note: * As the base clock synchronization varies, so does the length of one bit.
1 1
1
2345678910111213 12345678910111213
12345678 12345678
9101112 1
1
234
5
1234 678
56789101112 12345678
8 MHz
7.3846 MHz

Rev. 3.0, 10/02, page xiv of lviii
Section Page Description
13.7 SCI Select Function
Figure 13.24 Example of
Communication Using the
SCI Select Function
406 Added
Note: *The selection signals (SEL_A and SEL_B) of the LSI
must be switched while the serial clock (M_SCK) is high after
the end bit of the transmit data has been send. Note that one
selection signal can be brought low at the same time.
Figure 13.25 Operation of
Communication Using the
SCI Select Function
407 Figure title amended
Added
Note: *The selection signals (SEL_A and SEL_B) of the LSI
must be switched while the serial clock (M_SCK) is high after
the end bit of the transmit data has been send. Note that one
selection signal can be brought low at the same time.
14.3.2 IDCODE Register
(IDCODE) 422 3rd line changed as follows
The HD64F2215, HD64F2215U, HD6432215A,
HD6432215B, and HD6432215C output fixed codes
H’0002200F, H’0003200F, H’001B200F, and H’001C200F,
respectively, from the TDO.
Table 14.3 IDCODE
Register Configuration Code amended
(Incorrect) HD64F2215 code
(Correct) HD64F2215 code, HD64F2215U code
15.1 Features
• Endpoint configuration
selectable
433 Replaced
The FIFO buffer for bulk transfer and isochronous transfer
has a double-buffer configuration
Total 1288-byte FIFO
—EP0s fixed: Control_setup FIFO, 8 bytes
—EP0i fixed: Control_in FIFO, 64 bytes
—EP0o fixed: Control_out FIFO, 64 bytes
—EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes
—EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer
configuration)
—EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer
configuration)
—EPn selectable: Isochronous_in FIFO, variable 0 to 128
bytes x 2 (double-buffer configuration)
—EPn selectable: Isochronous_out FIFO, variable 0 to 128
bytes x 2 (double-buffer configuration)
—EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer
configuration)
—EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer
configuration)
—EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes

Rev. 3.0, 10/02, page xv of lviii
Section Page Description
15.1 Features
• Maximum
Configuration,
InterfaceNumber, and
AlternateSetting
configuration
specifications of this
LSI Configuration
434 Endpoint configuration based on Bluetooth standard 1.0 can
be specified.
Deleted
Newly added
• Maximum Configuration, InterfaceNumber, and
AlternateSetting configuration specifications of this LSI
Configuration 1 ----- InterfaceNumber 0 to 2 -----
AlternateSetting 0 to 7 ----- EP0, EP1 to EP8
Figure 15.1 Block
Diagram of USB 435 Figure amented
1288-byte FIFO
EP3i
EP0o
EP3oEP1i
EP2iEP0s
EP2o
EP5i
EP4i
EP4oEP0i
15.3.1 USB Endpoint
Information Registers 00_0
to 22_4 (UEPIR00_0 to
UEPIR22_4)
438 Explanation added to 23th line as follows
UEPIR is used to set 23 kinds of endpoint (EPINFO data).
• UEPIRnn_0 439 Replaced
•
••
•UEPIRnn_0
Bit Bit Name Initial Value R/W Description
7
to4 D39 –D36 —R/W Endpoint number (4-bit configuration, settable values: 0 to 8)
0000: Control transfer (EP0)
0001 to 1000: Other than Control transfer (EP1 to
EP8)
There are restrictions on settable endpoint
numbers according to the Interface number and
Alternate number to which the endpoint belongs.
Restriction 1: Set different endpoint numbers
under one Alternate.
However, there is no problem with
use of the same endpoint number if
the transfer directions (IN/OUT) are
different. (Ex: Alt0 -- EP1, EP2i,
EP2o)
Restriction 2: Do not set the same endpoint
number under different Interface
numbers. (Ex: Int0 -- Alt0 -- EP1,
EP2, Int1 -- Alt0 -- EP3)
3
2D35 D34 — —R/W R/W Configuration number to which endpoint belongs
(2-bit configuration, settable values: 0, 1)
00: Control transfer
01: Other than Control transfer
1
0D33 D32 — —R/W R/W Interface number to which endpoint belongs (2-bit
configuration, settable values: 0 to 2)
00: Control transfer
00 to 10: Other than Control transfer

Rev. 3.0, 10/02, page xvi of lviii
Section Page Description
15.3.1 USB Endpoint
Information Registers 00_0
to 22_4 (UEPIR00_0 to
UEPIR22_4)
• UEPIRnn_1
Replaced
UEPIRnn_1
Bit Bit Name Initial Value R/W Description
7 to
5D31 –D29 —R/W Alternate number to which endpoint belongs (3-bit configuration, settable values: 0 to 7)
000: Control transfer
001 to 111: Other than Control transfer
4
3D28 D27 — —R/W R/W Endpoint transfer type (2-bit configuration) 00: Control(UEPIR00)
01: Isochronous(UEPIR04 to UEPIR19)
10: Bulk(UEPIR02,UEPIR03,UEPIR20,UEPIR21)
11: Interrupt(UEPIR01,UEPIR22)
2D26 —R/W Endpoint transfer direction (1-bit configuration)
0: out (UEPIR00,03,05,07,09,11,13,15,17,19,21)
1: in (UEPIR01,02,04,06,08,10,12,14,16,18,20,22)
1
0D25 D24 — —R/W R/W Endpoint maximum packet size (D25 to D16 10-bit
configuration)
Control transfer = 64 only (UEPIR00)
Interrupt transfer = 0 to 64 (UEPIR01, UEPIR22)
Bulk transfer = 0 or 64 (UEPIR02, UEPIR03,
UEPIR20, UEPIR21)
Isochronous transfer = 0 to 128 (UEPIR04 to
UEPIR19)
• UEPIRnn_2
440
UEPIRnn_2
Bit Bit Name Initial Value R/W Description
7 to
0D23 –D16 —R/W Endpoint maximum packet size (D25 to D16 10-bit configuration)
Control transfer = 64 only (UEPIR00)Interrupt
transfer = 0 to 64 (UEPIR01, UEPIR22)
Bulk transfer = 0 or 64 (UEPIR02,UEPIR03,
UEPIR20, UEPIR21)
Isochronous transfer = 0 to 128 (UEPIR04 to
UEPIR19)
• UEPIRnn_3 441 Replaced
UEPIRnn_3
Bit Bit Name Initial Value R/W Description
7 to
0D15 –D8 —R/W Endpoint internal address (D15 to D0 16-bit configuration)
Set UEPIR00_3, UEPIR00_4 = H'0000
Set UEPIR01_3, UEPIR01_4 = H'0001
:
Set UEPIR21_3, UEPIR21_4 = H'0015
Set UEPIR22_3, UEPIR22_4 = H'0016
• UEPIRnn_4
UEPIRnn_4
Bit Bit Name Initial Value R/W Description
7 to
0D7 –D0 —R/W Endpoint internal address (D15 to D0 16-bit configuration)
Set UEPIR00_3, UEPIR00_4 = H'0000
Set UEPIR01_3, UEPIR01_4 = H'0001
:
Set UEPIR21_3, UEPIR21_4 = H'0015
Set UEPIR22_3, UEPIR22_4 = H'0016
Table 15.2 EPINFO Data
Settings 444 Note amended
Notes:*5Maximum packet size of Isochronous transfer
must be from 0 to 128.

Rev. 3.0, 10/02, page xvii of lviii
Section Page Description
15.3.11 USB Endpoint
Data Register 0s
(UEDR0s)
457 2nd line changed as follows
(Incorrect) Endpoint0
(Correct) Endpoint0s
15.3.12 USB Endpoint
Data Register 0i (UEDR0i) 9th line changed as follows
(Incorrect) Endpoint0
(Correct) Endpoint0i
15.3.13 USB Endpoint
Data Register 0o
(UEDR0o)
15th line changed as follows
(Incorrect) Endpoint0
(Correct) Endpoint0o
15.3.14 USB Endpoint
Data Register 1i (UEDR1i) 458 2nd line changed as follows
(Incorrect) Endpoint1
(Correct) Endpoint1i
15.3.15 USB Endpoint
Data Register 2i (UEDR2i) 8th line changed as follows
(Incorrect) Endpoint2
(Correct) Endpoint2i
15.3.16 USB Endpoint
Data Register 2o
(UEDR2o)
14th line changed as follows
(Incorrect) Endpoint2
(Correct) Endpoint2o
15.3.17 USB Endpoint
Data Register 3i (UEDR3i) 459 2nd line changed as follows
(Incorrect) Endpoint3
(Correct) Endpoint3i
15.3.18 USB Endpoint
Data Register 3o
(UEDR3o)
9th line changed as follows
(Incorrect) Endpoint3
(Correct) Endpoint3o
15.3.19 USB Endpoint
Data Register 4i (UEDR4i) 15th line changed as follows
(Incorrect) Endpoint4
(Correct) Endpoint4i
15.3.20 USB Endpoint
Data Register 4o
(UEDR4o)
460 2nd line changed as follows
(Incorrect) Endpoint4
(Correct) Endpoint4o
15.3.21 USB Endpoint
Data Register 5i (UEDR5i) 7th line changed as follows
(Incorrect) Endpoint5
(Correct) Endpoint5i
15.3.22 USB Endpoint
Receive Data Size
Register 0o (UESZ0o)
13th line changed as follows
(Incorrect) Endpoint0
(Correct) Endpoint0o

Rev. 3.0, 10/02, page xviii of lviii
Section Page Description
15.3.23 USB Endpoint
Receive Data Size
Register 2o (UESZ2o)
461 2nd line changed as follows
(Incorrect) Endpoint2
(Correct) Endpoint2o
4th line changed as follows
(Incorrect) The FIFO for endpoint 2 out transfer has a dual-
FIFO configuration
(Correct) The FIFO for endpoint 2o (for Bulk_out transfer) has
a dual-FIFO configuration
15.3.24 USB Endpoint
Receive Data Size
Register 3o (UESZ3o)
7th line changed as follows
(Incorrect) Endpoint3
(Correct) Endpoint3o
9th line changed as follows
(Incorrect) The FIFO for endpoint 3 out transfer has a dual-
FIFO configuration.
(Correct) The FIFO for endpoint 3o (for Isochronous_out
transfer) has a dual-FIFO configuration.
15.3.25 USB Endpoint
Receive Data Size
Register 4o (UESZ4o)
12th line changed as follows
(Incorrect) Endpoint4
(Correct) Endpoint4o
14th line changed as follows
(Incorrect) The FIFO for endpoint 4 out transfer has a dual-
FIFO configuration.
(Correct) The FIFO for endpoint 4o (for Bulk_out transfer) has
a dual-FIFO configuration.
15.3.30 USB Interrupt
Enable Register 0 (UIER0) 470 Bit table amended
5 EP1iTRE 0 R/W Enables the EP1iTR interrupt.
Bit Bit Name Initial Value R/W Description
7 BRSTE 0 R/W Enables the BRST interrupt.
6 — 0RReserved
This bit is always read as 0.
4 EP1iTSE 0 R/W Enables the EP1iTS interrupt.
15.3.34 USB Interrupt
Select Register 0 (UISR0) 472 Bit table amended
Bit Bit Name Initial Value R/W Description
7 BRSTS 0 R/W Selects the BRST interrupt output pin.
6 — 0RReserved
This bit is always read as 0.
5 EP1iTRS 0 R/W Selects the EP1iTR interrupt output pin.
4 EP1iTSS 0 R/W Selects the EP1iTS interrupt output pin.
3 EP0oTSS 0 R/W Selects the EP0oTS interrupt output pin.
2 EP0iTRS 0 R/W Selects the EP0iTR interrupt output pin.
1 EP0iTSS 0 R/W Selects the EP0iTS interrupt output pin.
0 SetupTSS 0 R/W Selects the SetupTS interrupt output pin.

Rev. 3.0, 10/02, page xix of lviii
Section Page Description
15.3.42 USB Test
Register 1 (UTSTR1) 479 Bit table amended and Note added
Bit Bit Name Initial Value R/W Description
7
6VBUS UBPM
—*
—*
R
RInternal/External Transceiver Input Signal Monitor Bits VBUS: Monitors VBUS pin
UBPM: Monitors UBPM pin
5 to 3 —0 R Reserved
These bits are always read as 0 and cannot be
modified.
2
1
0
RCV
VP
VM
—*
—*
—*
R
R
R
Internal/External Transceiver Input Signal Monitor Bits
RCV: Monitors the RCV signal of the internal/external
transceiver
VP: Monitors the VP signal of the internal/external
transceiver
VM: Monitors the VM signal of the internal/external
transceiver
Note:*An asterisk indicates an undefined value.
15.3.42 USB Test
Register 1 (UTSTR1)
Table 15.4
Relationship between the
UTSTR1 Settings and Pin
Inputs
480 UTSTR1 Monitor value amended
UTSTR1
Monitor
RCV VP VM
000
0/1 0 0
X00
001
110
X11
X00
001
110
X11
0 0/1 X
0X0/1
0/1 X X
X0/1X
XX0/1
15.3.44 Module Stop
Control Register B
(MSTPCRB)
481 Section title amended

Rev. 3.0, 10/02, page xx of lviii
Section Page Description
15.5.9 Isochronous–Out
Transfer (Dual-FIFO)
(When EP3o is Specified
as Endpoint)
Figure 15.21 EP3o
Isochronous-Out Transfer
Operation
507 Figure amended
Set EP3o normal
receive status to 1
(Set internal EP3o TS to 1)
Switch to FIFO
Receive OUT token
Receive data from the host
Receive data from the host
FIFO B
FIFO A
Receive SOF
USB function
Receive data
error?
Yes
No
Yes
No
Switch to FIFO
Receive SOF
Receive OUT token
Receive data
error?
Set EP3o normal
receive status to 1
(Set Internal EP3o TS to 1 )
Set EP3o abnormal
receive status to 1
(Set Internal EP3o TF to 1)
Set EP3o abnormal
receive status to 1
(Set internal EP3o TF to 1)
B-side UIFR1/EP3oTS, EP3oTF update
A-side UIFR1/EP3oTS, EP3oTF update
15.5.10 Processing of
USB Standard Commands
and Class/Vendor
Commands
508 11th line changed as follows
(Incorrect) EXIROx pin
(Correct) EXIROx