Sega 32X User manual

iiM' SERVICE MANUAL
GENESIS 32X(VA0,VA1) /MEGA DRIVE 32X
NO. 012
ISSUED JUNE. 1995
CONTENTS
1. SPECIFICATIONS 2
2. IDENTIFYING PARTS 3
3. ACCESSORIES 3
4. DISASSEMBLY 4
5. ADJUSTMENT 5
6. BLOCK DIAGRAM 7
7. SCHEMATIC &CIRCUIT BOARD DIAGRAMS 9
8. PARTS SPECIFICATIONS 19
9. EXPLODED VIEW &PARTS LIST 34
9-1. Exploded View 34
9-2. Mechanical Parts List 35
9-3. Electrical Parts List 35
9-4. Accessories/Package List 38
Sega Enterprises, Ltd.

BEFORE REFERRING TO THE SERVICE MANUAL
Since the circuit of the Extension Unit used in the GENESIS 32X has been integrated on the main circuit board, an Extension
Unit is not necessary for the GENESIS 32X(VA1).
This circuit is built into the MEGA DRIVE 32X from the first unit.
1. SPECIFICATIONS
Ratings
Model GENESIS 32X MEGA DRIVE 32X
PAL PAL G/l
Power input Input: AC120V, 60 Hz
Output: DCIOV, 850 mA Input: AC230 V, 50 Hz
Output: DCIO V, 850 mA Input: AC240 V, 50 Hz
Output: DC9 V, 850 mA
Power consumption Approx. 4WApprox. 4WApprox. 4W
Operating environment Temperature: S'C~35‘C
Humidity: 20%RH-80%RH (no condensation)
Dimensions 115(W)X210(L)X 100(H) mm
Specifications
CPU
Master 32bit RISC SH2 23 MHz 20MIPS
Stave 32bit RISC SH2 23 MHz 20MIPS
Memories
RAM 2Mbit (SDRAM)
VRAM 2Mbit
Sound PWM Sound Source (Stereo)
VDP SEGA custom LSI
Display TV
Display capability Color 32,768 colors
VIDEO
Video Output RF
RGB
Slots Cartridge slots
I

2. IDENTIFYING PARTS
Front View Rear View
3. ACCESSORIES
Connector Cable y
Conversion Cable Audlo/Video Cable (Mono)
Spacer for GENESIS II
/MEGA DRIVE II
AC Adaptor Bectromagnetic Shield Plates
Qf]=CUO
Mono Cable Scart
(France only)
Extension Unit
(Only GENESIS 32XVA0)
^=[Z)=oQEi
RF Unit
(PAL version except for France)
-3-

4. DISASSEMBLY
4-1. Top Case Removal (See Fig. 4-1)
I
)
Remove four screws ®and the top case.
4-2. Sub Board Removal
(See Fig. 4-2)
1)Remove ten screws ®attached the top shield case.
2) Remove two screws ©attached the 64-pin
connector.
3) Remove two 40-pin flat cables on the sub board.
4) Remove the sub board showned as arrow.
4-3. Main Board Removal
(See Fig. 4-3, 4-4)
1) Remove four screws ®attached the front case and
rear case on the bottom case and then their
showned as arrow.
2) Remove two screws ®attached the front case and
rear case and main board.
Flg.4>2
-4-

5. ADJUSTMENT
Video Frequency Matching Adjustment
Test equipment and tools for adjustment
1.Regulated power supply (5VDC)
2. Frequency counter (capable of displaying 7digits or more)
3. 10:1 oscilloscope probe
4. Philips screwdriver
5. Non-metal adjustment driver
6. AC adaptor excusively for super 32X
7. One lead for GND and two leads forSV
Connections of test equipment
Adjustment procedure
1.Disconnect the super 32X from the Mega Drive.
2. Remove the top case and top shield case from the super 32X.
3. Plug the AC adaptor into an AC outlet and into the DC jack.
4- Set the regulated power supply to 5V DC and connect itto IC14 pin 1. (The super 32X turns on.)
5. Connect 5V DC to ICl 2pin 31 .(Set to the test mode.)
6. Connect the frequency counter to ICI2 pin 20 and adjust C72 so the frequency is 3.579545 MHz ±lOHr.
-5-

6. BLOCK DIAGRAM

7. SCHEMATIC &CIRCUIT BOARD DIAGRAMS
7-1. Schematic Diagram-1 (Main Section -1/2)

MEMO

7-2. Circuit Board Diagram (Main Board) VAO
ABD

7-3. Schematic Diagram-2 (Main Section -2/2)
©
2
3
S1EIF1GIH

7-4. Schematic Diagram-3 (Sub Section)
15

f-o. uircuit board Diagram-2 (Sub Board)
-18 -

8. PARTS SPECIFICATIONS
ICI/2 CPU
1C HD6417095F2?QFP
Parts No. :315-0922 ICHDB417095F28QFP
Parts No. :315-0922A
ITop View
IDescription
No. I/O Pin Name Function
Dll
2I/O D12 Data bus
3D13
vcci Power suDpIv CSVl
D14 Data bus
6-vssi Power supply /OV)
D15
Data bus
8D16
9I/O D17
10 D18
11 D19
12 VCC2 Power supply fSV)
D20 Data bus —
|
VSS2 Power supply fOVl -\
I/O
D21
Data bus
16 D22
17 D23
“VCC3 Power supply (5V|
I/O D24 Data bus
“VSS3 Power supply (OV)
21
I/O D25
Data bus
22 D26
23 D27
VCC4 Power supply f5V>
26 D28 Data bus
27
28 I/O
D29
D30 Data bus
29 D3I
I/O
AO
Address bus
31 A1
32 A2
-VSSS Power supply (OVl
34 A3
Address bus
35 A4
36 A5
37 A6
38 A7
39 A8
VCC5 Power supply /5V1 1
-19 -
No. I/O Pin Name Function
A9 Address bus
VSS6 Power supply f5V)
AID
44 All
45 VO A12 Address bus
46 A13
47 AM
-VCC6 Power supply {5V)
49 I/O A15 Address bus
-VSS7 Power supp.y (OV)
A16
52 I/O A17 Address bus
53 AI8
“VCC7 Power supply (5V1
I/O A19 Address bus
VSS8 Power supply (0V>
A20
58 I/O A21 Address bus
59 A22
-VCC8 Power supply fSV)
61 I/O A23 Address bus
62 ~VSS9 Power supply fOV)
63
I/O
A24
Address bus
64 A2S
65 A26
66 0DACKO DMACO acknowledee
VCC9 Power supply (SV)
68 DACKl UMACl acknowledjte
vssio Power supply /OVl
DREOO DMACO rctuest
DREOl DMACl request
Cso Chip select 0
0r.<51 Chip select 1
CS2 Chip select 2
0S3 Oiip select 3
76 I/O RS Bus cycle start
I/O RD/WR Read write
VSSll Power supply (OV)
RAS.^ RAS for DRAM/SDRAM/CE for PSRAM
cas.Oe CAS for SDRAM/OE for PSRAM
CaShh. noMini WP.3 Each memory most significant byte select signal
CASHL nOMlJL WF.2 Each memory 2nd byte select signal
(JASLH. DWMLIJ. WF.1 Each memory 3rd byte select signal
VCCIO Power supply fSV)
CASLL. DOMLL. WRO ba^ memory least signiHcant byte select signal
86 VSS12 Power supply (OVl
RD Read pulse
CKE SDRAM clock enable control
WAIT Hardware wail request.
BEN Reserve
VSS13 Power supply (0V>
BACK. BRLS Bus right permission in slave mode./Bus right acknowledge in master mode
BREO. BGR Bus right reouest in slave mode./Bus right acknowledge in master mode
WDTOVF Watch dog timer quiput.
FTOB Free-running timer output B.
VCCll Power supply f5V|
FTOA Free-running timer output A.
VSS14 Power supply (OV)
FTI Free-running timer input.
FTCI tree-running timer clock input.
RXD Serial data input.
TXD Serial data output.
I/O SCK Serial clock input/outpui.

7-2. Circuit Board Diagram (Main Board) VA1
2
3
L
5
C\j D
12

No. I/O Pin Name Function
_VCC(PLLU2 Power supply /5V) of built-in PLL
105 1MDO Operation mode pin
_VSS (PLL) 15 Power supply (OV) of built-in PLL
IMDl Operation mode pin
108 0CAPl
CAP2 External capacitor connection pin for PLL
109
110 1MD2 Operation mode pin
111 0rKPACKN Clock pause acknowledge output.
112 1CKPRRON Qock pause reouest input.
_VCC13 Power supply f5Vl
114 IN.C Not connectes.
_VSS16 Power supply (OV)
116 0N.C Not connectes.
117 1MD3 Operation mode pin
118 I/O CKIO System clock input/ouiput.
119 IMD4 Operation mode pin
120 MD5
_VSS17 Power supply (OV)
122 IRES Reset
123 -VCC14 Power supply (5V)
124 0IVETF interrupt vector fetch cycle
125 1NMI Non-mask^le interrupt request.
126 1R13
External interrupt factor input.
127 IRU
128 IRLl
129 IRLO
130 I/O DO Data bus
131 D1
132 -VCC15 Power supply (5V)
133 I/O D2 Data bus
134 -VSS18 Power supply (OV)
135
I/O
D3
136 D4
137 D5
138 D6
139 -VCC16 Power supply (5V)
140 I/O D7 Data bus
141 -VSS19 fhjwer supply (OV)
142
I/O
D8
Data bus
143 D9
144 DIO
-21 -

Block Diagram
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1
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-22 -

ICS 2Mbit SDRAM
IC UPD45021 61 G5-A1 2TSOP
Parts No. :315-0910-12
Top View
m
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Description
No. I/O Pin Name Function
35 ICLK CLK is the master clock input pin. The other inputs signals are referenced at CLK
rising edge.
18 1CS ^low Stan the command input cycle. When CS is high, all input are not
referenced. But even if ^is high, internal operations i.e. bank active or burst are
not changed.
15
1
WE RAS CAS WE have the same names with conventional DRAM. But these pins
have deferent definitions with conventional ones. All of these pins only define
16 Cas
17 RAS
21
1
AO Row address(AX0-AX6, AX8) is determined by A0-A8 input signal level at the
rising edge CLK signal at the bank active command cycle (state of AX7 is not
applicable).
Column address (AY0-AY7) is deteimined by A0-A7 input signal level at aread or
22 A1
23 A2
24 A3 write command cycle. The column address will be used as the bum access sian
27 A4 AS define precharge mode,
—Precharge command cycle:
A8 sLow: Both bank precharged.
AS =High: One bank prechartged (depends on state of A9)
—Read/wtite command cycle:
A8 sHigh: Precharge cycle is started automatically following the end of data
transfer in burst mode.
28 A5
29 A6
30 A7
20 A8
19 A9 A9 is bank select signal (BS). In command cycle, A9«iow select bank Aand
A9=High select bank B.
34 CKE
CKE determine next CLK is valid or not. If CKE is high next CLK rising edge is
valid. Bui if CKE is low, next CLK is invalid. If CUC rising edge is invalid,
internal clock is not asserted and uPD4504161 becomes halt operation. And when
fi PD450216I dose not in burst mode and CKE is negated, iU PD4502161 enter
power down mode.
During power down mode CKE must keep tow level.
36 DQMU EIQMU control Upper byte and DQMLcontrols Lower byte input/ouiput buffers.
In read mode, DQMU, DQMLcontrol output buffer impedance like conventional
SE. if DQMU E)QML is High, output buffers bMome high impedance. If DQMU,
DQML is Low, output buffers become low impedance. And when device in write
mode, DQMU, E)QML control word mask. If DQMU, DQML is High input data is
not written to memory cell. If DQMU, DQML is Low input data is written to
memory cell.
14 DQML
-23 -

No. I/O Pin Name Function
2DQO
3DQl
5D02
6D03
8D04
9D05
11 DQ6
12
I/O
EX37
39 DQ8 J/0 pins are the same as conventional DRAM.
40 DQ9
42 DQIO
43 DQll
45 DQ12
46 D013
48 DQ14
49 D015
1
7
13
Power supply of internal circuits.
25 Vcc
38
44
4
10
26
Power supply of internal circuits.
41 Vss
47
50
31.32 -GND Ground pins
-24 -

IC4
!C CUSTOM CHIP SCA MARS l/F
Parts No.: 315-5818A
1C CUSTOM CHIP G/A MARS 1^
Parts No. :315-5818
Top View 132 89
133T
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178
Dischption
n- 1
1^
1
1
{
No. I/O Pin Name No. I/O Pin Name No. I/O Pin Name No. I/O Pin Name
1-VDD 45 -GND 89 -VDD 133 -GND
20CHO 46 -GND 90 I/O VD8 134 -GND
30CHI 47 1SHAIO 91 I/O VD6 135 I/O ADO
40OVA19 48 1SHAH 92 I/O VDl 136 I/O ADI
5oOVA20 49 ISHA12 93 wVD9 137 I/O AD2
61OVA21 50 1SHA13 94 VO VD5 138 I/O AD3
7ICART 51 ISHA14 95 I/O VD2 139 I/O AD4
8I/O KILL 52 ISHA15 96 I/O VDIO 140 I/O ADS
9I/O SHD15 53 ISHA16 97 1« VD4 141 1/0 AD6
10 i/n SHD14 54 ISHA17 98 I/O VD3 142 1/0 AD7
11 I/O SHD13 55 0WAIT 99 I/O VDll 143 lAJ ADS
12 I/O SHD12 56 1RD 100 1MRES 144 I/O AD9
13 I/O SHDll 57 1DQMLL 101 IVA19 145 1/0 /»lD10
14 I/O SHDIO 58 IDOMLU 102 1VA20 146 I/O ADll
15 1/0 SHD9 59 IRDXWR 103 1VA21 147 I/O AD12
16 I/O SHD8 60 1BS 104 1VA22 148 I/O AD13
17 I/O SHD7 61 ICS2 105 1VA23 149 I/O AD14
18 I/O SHD6 62 ICSl 106 ICASO 150 I/O AD15
19 I/O SHD5 63 1CSOS 107 ICEO 151 0SEL
20 I/O SHD4 64 1CSOM 108 1AS 152 ICHPLL
21 I/O SHD3 65 0DREQl 109 0DTACK 153 BURNl
22 -VDD 66 0DREOO 110 -VDD 154 0OCEO
23 _GND 67 IVA18 111 -GND 155 0OASEL
24 I/O SHD2 68 IVA17 112 VCLK 156 0OCAS2
25 I/O SHDl 69 VA16 113 CAS2 157 oOCASO
26 I/O SHDO 70 VAIS 114 I/O VD15 158 oOLWR
27 0SIPLl 71 VA14 115 I/O VD14 159 I/O RDO
28 0SIRL2 72 VA13 116 I/O VD13 160 1/0 RDl
29 0SIRU 73 VA12 117 1/0 VD12 161 I/O RD2
30 0MIRLl 74 VAll 118 ASEL 162 WJ RD3
31 0MIRL2 75 VAIO 119 VRES 163 I/O RD4
32 0MIRU 76 VA9 120 LWR 164 I/O RD5
33 oCKIO 77 VA8 121 UWR 165 lAJ RD6
34 0SHRES 78 VA7 122 HINT 166 1/0 RD7
35 ISHAl 79 VA6 123 VINT 167 WJ RD8
36 ISHA2 80 VA5 124 VACK 168 1/0 RD9
37 ISHA3 81 VA4 125 0ACCS 169 WJ RDIO
38 1SHA4 82 VA3 126 0DIR 170 1/0 RDll
39 ISHA5 83 VA2 127 0RW 171 I/O RD12
40 ISHA6 84 VAl 128 0OUWR 172 1/0 RD13
41 1SHA7 85 I/O VD7 129 -AVDD 173 I/O RD14
42 ISHA8 86 lAD VDO 130 -AGND 174 I/O RD15
43 ISHA9 87 -GND 131 0C23 175 -GND
44 VDD 88 -GND 132 -VDD 176 GND
-25 -

ICS ADDRESS SELECTOR
1C CUSTOM CHIP MARS ADSE
Parts No. :315-5805
Top View
Description
No. I/O Pin Name No. I/O Pin Name No. I/O Pin Name No. I/O Pin Name
0RA4 21 IVA9 41 SHA2 61 0RA22
20RA3 22 1VA8 42 SHA3 62 0RA21
30RA2 23 1VA7 43 SHA4 63 0RA20
40RAl 24 1VA6 44 SHA5 64 0RA19
-GND 25 IVA5 45 SHA6 65 0RA18
6VA23 26 1VA4 46 SHA7 66 0RA17
VA22 27 IVA3 47 SHA8 67 0RAM
0VA21 28 1VA2 48 SHA9 68 0RAIS
OVA20 29 IVAl 49 SHAIO 69 0RAM
10 0VA19 30 ISHA2! SO SHAH 70 0RAM
11 VA18 31 1SHA20 51 SHA12 71 -GND
12 -GND 32 1CKIO 52 SHA13 72 -VDD
13 VA17 33 -GND 53 -GND 73 0RAM
14 VA16 34 -VDD 54 1SHAM 74 oRAll
15 IVA15 35 IBREQ 55 1SHA15 75 0RAIO
16 IVA14 36 IIBACK 56 1SHAM 76 0RA9
17 IVA13 37 0OBACK 57 ISHA17 77 0RA6
18 1VA12 38 ISHA19 58 ISEL 78 0RA7
19 IVAll 39 ISHA18 59 -GND 79 0RA6
20 1VAIO 40 ISHAl 60 0RA23 80 0RA5
-26 -