Sharp Compet 17 User manual

Contents
Section Page
Title & Contents (this page) 1
Notes, Gate Identification & Signal Names 2
Block Diagram 3
Timing 4
Keyboard & P-Cycle Generator 5
Control (Major Operation Flags) 6
Control (F, J & G Flags) 7
Control (State Matrix) 8
Control (Outputs) 9
Registers 10
Arithmetic 11
Decimal Point Counters 12
Display 13
Power Supply 14
Timing Diagram 15
IC Pinouts & Gate Construction 16
Physical Layout and Connectors 17
Sharp Compet 17
Calculator
Sharp Compet 17 Calculator
Section: Title and Contents
Page: 1 Rendition: 2020 May 20
This schematic has been derived through
reverse engineering.
This is not the manufacter’s schematic, nor
is it based on the manufacturer’s schematic.

Notes
♦Gate symbols and signal names are presented in accordance with:
logic 1 = GND
logic 0 = V–24
♦The symol
N cp
denotes a physical connector pin, where c =connector and p =pin. Solid black end is the male side of
the connector. White end is the female side of the connector.
♦connection between different sections.
connection limited to same section.
Arrows indicate direction of signal or energy flow.
♦The symbol without an additional label denotes VDD (–24V).
♦Capacitance in microfarads unless otherwise indicated.
♦This schematic includes the user memory which is not present in the Compet 17 model. Components marked with “§”
are not present in the Compet 17.
♦These drawings based on a Model CS-17C unit with Serial No. 810591T.
Log
♦2000 Jul: Initial drawing / bhilpert.
♦2004 Oct: Signals on the remote connector (NR) elaborated further.
Switches and notes about single-cycle control of P added.
♦2017 May: Format updates. Question of pins on IC 5-6 noted.
Gate Identification
Gates and logic elements are identified by symbols of the following form:
Gate ID Description
1- n inverter in µPD1 IC
2- n 2 by 2 AND–OR gate in µPD2 IC
3- n 4-input AND gate in µPD3 IC
4- n flip-flop in µPD4 IC
5- n 4-bit shift register in µPD5 IC
6- n 8-bit shift register in µPD6 IC
7- n MOSFET in µPD7 IC
M- n MOSFET discrete
Discrete gates have no distinguishing identifier but their inputs are identified with a label indicating the location of the
diode which implements it:
Label Description
g . p diode in TDA001 or TDA002 package g at pin p
d n discrete diode
See the IC Pinouts and Gate Construction page for more about the integrated circuits.
See the Physical Layout and Connectors page for more about IC and gate location.
Sharp Compet 17 Calculator
Section: Notes
Page: 2 Rendition: 2020 May 20
Signal Names
Section Signal Description
Timing Ø… Master timing.
Ø1 Master clock, data capture phase.
Ø2 Master clock, output transition phase.
Ø3 Master clock, a third phase used by some flip-flops.
ØB… Bit timing.
ØD… Digit timing (4 bits constitutes a digit).
ØnB1+3 Used for triggering digit timing and display latch.
Øn(D16•B8•1) Capture pulse at the end of each full number cycle.
Keyboard K… The keyboard and numeral encoder.
PIndicates a number cycle during which processing occurs.
Control S…, C… The state machine.
CMultiply or divide operation pending.
DDivide operation pending.
F, G, J, M, S Assorted state flags.
S… Assorted internal state signals.
IDLE 1 during display and simple operations, 0 during multi-cycle operations.
CX… Outputs from control to the X register.
CW… “W register.
CM… “M register.
CPX… “ PX decimal point counter.
CPW… “PW decimal point counter.
CPY… “PY digit counter.
X Register X… The operand being displayed. Arithmetic is also incorporated in this register.
XC1,2,4,8 BCD numerals on their way to the display.
CARRY Carry indication to control.
W Register WThe second operand.
M Register MThe user memory.
PX Counter PX Ring counter to hold the place of the decimal point for the X operand.
PXI Signal to the display to turn on the decimal point at the appropriate time.
PW Counter PW Ring counter to hold the place of the decimal point for the W operand.
PY Counter PY Ring counter used during multiply and divide operations.
♦A lowercase “n” in a symbol name indicates the logical NOT operation.
♦The character “ • ” in a symbol name indicates the logical AND operation.
♦The character “+” in a symbol name indicates the logical OR operation.
P-Cycles and Manual Control of Operations
Two switches can be plugged into the remote connector (NR) to provide the ability to single-step through the
major state cycles of an operation. See the Keyboard page for wiring of the switches.
A P-cycle is a full number cycle during which processing occurs and is indicated by the P signal. Major state
transitions occur at the end of a P-cycle. Simple user operations such as numeral entry generate a single P-cycle
without sending IDLE to 0. More complex operations requiring multiple number cycles generate a first P-cycle
and send IDLE to 0. Multiple P-cycles are subsequently generated until the operation is complete, at which time
IDLE returns to 1.
Enabling the MANUAL switch disables the automatic generation of P-cycles for multi-cycle operations. In this
mode, once a multi-cycle operation has been initiated, each press of the STEP pushbutton generates a single
P-cycle, so the operation can be stepped through one P-cycle at a time.

KCLR, KCE,
KAS, KS, KMD, KD,
KRC, KDP,
KMC, KMR,
KMAS, KMS
V–24
M Register
(user memory, 48 bits)
W Register
(2nd operand, 48 bits)
X Register
(displayed operand, 48 bits)
12 Nixie Displays
Sharp Compet 17 Calculator
Section: Block Diagram
Page: 3 Rendition: 2020 May 20
PY
Ring Counter
PW
Ring Counter
PXI
Ø1
Ø2
ØB n
bit timing
ØD n
digit timing
Display Latch
(4 bits)
VCL
Keyboard
Control
CARRY
Arithmetic
(BCD
serial adder, 4
bits)
C
Flag
D
Flag
M
Flag
S
Flag
F
Flag
J
Flag
G
Flag
State
Sequencing
S1
S6
CX…
CA…
CB…
X Outputs
1-of-10
Decoder
and Drivers
Timing
Numeral
Encoder
K0…K9
KNUM
M
W
X
KNDP
Decimal
Point
Driver
logic supplies
display supplies
V+90D
V+90
V+190
Power Supply
000987654321.
Decimal Point (PX)
Ring Counter
Ø3
XC1
XC2
XC4
XC8
W
X
CSUB
CTC
Arithmetic
Outputs
CSUM
CWW
CWX
CWØ
KMC
CMX
CMØ
M Outputs
W Outputs
P Cycle
Generator
P
PX
CPYPX
CPW…
CPX…
PW
PY
PY Outputs
PW
Outputs
PX Outputs
IDLE

Ø1
10
2
1-1
2SA549
50K
100
pF
2SC458
2SC458
2SC458
5K
NL14
ØB2
ØB8
ØB1
NL23
Sharp Compet 17 Calculator
Section: Timing
Page: 4 Rendition: 2020 May 20
1K
2K
2K
100pF
100pF
70K
200K
Ø2
5K
2SA549
40K
200
pF
2SA549
50K
200
pF
Ø3
NL10
ØnB8
NL8
ØnB4
ØB4
9
3
1-1
NL21
NL19
1K
3K
NL12
1K
Ø2
Ø1
5-5
D1
ØT
7
6
ØC
8
11
1
1-1
Q1
4
Q2
3
Q3
2
Q4
1
ØnB1+3
ØnB4
5-1
D1
ØT
7
6
ØC
8
7
5
1-1
Q1
4
Q2
3
Q3
2
Q4
1
ØnB1+3
ØnB4
5-2
D1
ØT
7
6
ØC
8
Q1
4
B
Q2
3
B
Q3
2
B
Q4
1
B
ØnB1+3
ØnB4
5-3
D1
ØT
7
6
ØC
8
Q1
4
B
Q2
3
B
Q3
2
B
Q4
1
B
ØnB1+3
ØnB4
5-4
D1
ØT
7
6
ØC
8
Q1
4
Q2
3
Q3
2
Q4
1
ØnD2
ØnD3
NL40
ØnD4
NL38
ØnD5
NL42
ØnD6
ØnD7
NL44
ØnD8
ØnD9
ØnD10
ØnD11
NL11
ØnD12
NL9
ØnD13
NL7
NL17
8
4
1-1
2SC458
1K
ØnB1+3
100K
Ø3
B
B
B
B
2SC458
15K
NL5
ØnD1
NL15
ØnD2
ØnD3
ØnD4
ØnD5
ØnD6
ØnD7
ØnD8
ØnD9
ØnD10
ØnD11
ØnD12
ØnD13
7
5
1-2
ØD1416
NL6
ØnD16
NL16
10
2
1-6
ØD1
ØnD1
9
3
1-6
ØD11
ØnD11
8
4
1-6
ØD12
ØnD12
7
5
1-6
ØnD13
ØD13
2SC458
5K
Øn(D16•B8•1)
(CPC)
Ø1
ØnB8
ØnD16
NK39
01
01
01
02
02
02
05
05
05
05
04
04
04
04
03
03
03
03
03
C
C
D
D
C
D
C
C
C
C
S
V
D
C
D
D
D
D
E
d
c
NR39
NK12
NR12
NK7
NR7

KRC
KMC
KMR
0
1
×
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
M–
M+
2
=
DP
C
NK23
NK26
NK33
NK34
NK29
NK30
NK28
NK13
NK14
NK15
NK16
NK17
NK18
NK19
NK20
NK21
NK22
Sharp Compet 17 Calculator
Section: Keyboard & P-Cycle Generator
Page: 5 Rendition: 2020 May 20
ØB1
0
KDP
1
3
5
7
9
2
3
6
7
4
5
6
7
8
9
100K
2-12
3
4
1
2
5
ØB2
ØB4
2-12
9
8
11
10
7
ØB8
KNP
KEQ
KS
KD
KCLR
KMAS
D
KMS
8
4
1-7
D
94
KNDP
0.001
2K
0.5W
2
3
4
0
6
ØnD1
ØnD3
ØnD4
ØnD5
ØnD7
DPØD
NK43
NK3
NK1
NK6
NK4
NK2
8
4
1-4
CE
NK25
KCE
÷
MR
NK32
NK24
NK9
NK31
–
RC
MC
KMD
KCE
KEQ
KMD
KRC
KMC
KMR
KNDP
95
95
95
95
96
96
96
96
94
94
94
93
93
93
92
92
92
KNUM
3
1
Ø2
4-6
D
Q
ØT
2
10
5
ØC
11
Ø3
ØR
1
7
5
1-7
KCLR
E
D
Øn(D16•B8•1)
7-12
2
Ø2
4-6
D
Q
ØT
3
9
ØC
Ø3
ØR
E
Øn(D16•B8•1)
4
1
7-12
5
Ø2
4-6
D
Q
ØT
4
8
5
ØC
7
Ø3
ØR
1
E
Øn(D16•B8•1)
nP
P
0.047
100K
E
E
NK40
E
D
D
D
D
D
D
IDLE
300K
VCL
98.4
98.3
98.2
98.1
91.1
91.2
91.3
91.4
97.1
97.2
97.3
97.4
d45
d30
d29
d46
d31
d26
d27
d28
d42
d33
d32
§
§
§
§
§
§
§
§
§
§
§
NR40
NK35
NK27
IDLE
nDPØD
PTRIGGER
PMANUAL
STEP
NR35
NR27
MANUAL
Controller / Monitor Unit
(see Notes page)
NORMAL
BUSY
NR38
IDLE
NR42
NR10
NR23
NR25
NR33
NR34
NR29
NR30
NR26
NR24
NR9
NR31
NR32
NR3
NR1
NR6
NR4
NR2
NR43
NR13
NR14
NR15
NR16
NR17
NR18
NR19
NR20
NR21
NR22
NR28
2N4401
100K
NR39
Ø3
NR12
ØB1
NR3
ØnD1 (via diode)
NR40
P
NR44
X
TEST
POINTS
NR7
Ø1
150K
GND
VDD (–24V)

KMD•S
KMD
Sharp Compet 17 Calculator
Section: Control (Major Operation Flags)
Page: 6 Rendition: 2020 May 20
×
÷
NK37
NK36
50K
50K
100
100
C458
C458
C458
5K
CPA
Øn(D16•B8•1)
nP
11
1
1-5
E
C458
5K
CPA’
E
Øn(D16•B8•1)
nP
D
7-13
2
3
1
MUL•M•nS
7-13
5
MUL•nM•nS
E
E
nM
nS
nM
S
Ø2
4-3
D
Q
ØT
3
9
5
ØC
7
Ø3
ØR
1
M
H
CPA’
9
3
1-3
nM
D
M-4
Ø2
4-3
D
Q
ØT
2
10
5
ØC
11
Ø3
ØR
1
S
H
CPA’
10
2
1-3
nS
D
M-3
E
M
S
E
E
E
nC
nD
nC
D
C
nD
Ø2
4-7
D
Q
ØT
3
9
5
ØC
7
Ø3
ØR
1
C
E
CPA’
10
2
1-7
nC
D
M-10
K
Ø2
4-7
D
Q
ØT
4
8
ØC
Ø3
ØR
D
D
CPA’
9
3
1-7
nD
D
M-9
K
E
C
D
KMD
KD
7-14
10
9
11
KEQ
7-14
5
4
1
KEQ•C•nD
7-14
7
8
KEQ•nC•D
7-14
2
3
KEQ•nC•nD
8
4
1-3
D
KEQ•C•nD
4
7
5
1-3
D
7-12
10
9
KNP•(nM+nS)
KNP
7-13
10
9
KS•nC•nD
KS
11
KMD
KCLR
S2•nF•J•nM(K)
67.4
S2•nF•J•nM(K)
KCLR
67
67.1
67.2
67.3
68.4
68
68.1
68.2
68.3
25.2
KRC
KEQ
KNP•(nM+nS)
25
25.3
25.4
14.4
S2•F•J
25.1
KNDP•M•S
M-8
KMR
16.1
KCLR
KMD•S
KMAS
16
16.2
16.3
16.4
S2•nF•J•nM
17.1
S2•nF•J•nM
KMS
17
17.3
17.4
17.2
27.3
KRC
KMD•S
KEQ
27
27.1
27.4
27.2
KCLR
M-7
nS
1
KCE
36.4
65
42.4
45.4
48.4
55.4
65.1
65.2
65.3
65.4
d13
S1•nF•J•M
S6•nF•J
S5•F•J
S1•F•J
SCd
S2•nF•J•M
S2•F•nJ
S2•nF•J•nM
KEQ
KCLR
D2
D1
d34
d35
§
d18
§
K
d41
d43
KMD•S
KMD•S
7-11
nM+nS
d8
d23
3
2
KNDP
d5
d24
KCE'
KNDP•M•S
KNDP•M•S•nC•nD+KCLR+KMD•S
§
§
nM+nS
D
C+D
KEQ•C•D
KEQ•C•D
S
S
5
7-11
4
1
KCLR
(Note possibility of backflow from
KNDP•M•S•nC•nD+KCLR+KMD•S
to KNDP•M•S )

Ø2
4-2
D
Q
ØT
3
9
ØC
Ø3
ØR
11
1
1-4
nJ
CPA’
2-9
11
10
9
8
DPØD
7
2-5
11
10
8
9
ØD11
7
E
ØD1
S2•nF•nJ
2-8
11
10
9
8
S1•nJ
7
E
S4•nF•nJ
2-5
4
3
2
1
PX
5
SCb
2-9
4
3
2
1
S5•F•nJ
PXI
5
X
S6•F•nJ
SCa
XC1
J
D
E
Ø2
4-3
D
Q
ØT
4
8
5
ØC
7
Ø3
ØR
1
F
H
CPA’
E
nF+nJ
E
nF+J
E
F+nJ
E
F+J
E
Ø2
4-2
D
Q
ØT
2
10
ØC
11
Ø3
ØR
E
Ø1
M-1
3-3
2
3
4
1
ØD12
ØB8
CARRY
ØD1
E
K
5
H
Ø2
4-2
D
Q
ØT
4
8
5
ØC
7
Ø3
ØR
1
E
Ø1
3-3
11
10
8
9
ØnD16
ØB8
W
E
7
2-8
4
3
1
2
Øn(D16•B8•1)
5
PX
9
3
1-4
nG
G
D
G
nG
7
5
1-4
nF
D
nF
nJ
nF
J
F
nJ
F
J
M-5
E
KCLR
7-12
7
8
11
KNP•F
nF
nF
nF
J
J
Ø1
15.1
S3
KEQ•nC•D
S6•nF•nJ
23
15.2
15.3
15.4
KDP
S4•nF•nJ
S1•nF•J•M
13.4
23.1
23.2
S6•nF•J
23.3
S5•nF•J
KEQ•C•D
S1•nF•J•nM
23.4
33.1
58.2
MUL•M•nS
d6
MUL•nM•nS
22.1
S6•F•J
S4•F•J
SCa
22
22.2
22.3
22.4
KEQ
S2•F•J
S2•F•nJ
26.1
26.2
26.3
KCE'
26.4
KRC
37.1
SCk
26
d4
S1•F•J
S1•nF•J•M
13.3
SCe
K
S2•nF•nJ
S3
38.1
d15
24.2
K
SCm
S6•nF•J
32.4
42.2
d36
d20
Sharp Compet 17 Calculator
Section: Control (F, J & G Flags)
Page: 7 Rendition: 2020 May 20
§
§
§
KNP

E
E
nM
M
E
K
NK11
NK5
Sharp Compet 17 Calculator
Section: Control (State Matrix)
Page: 8 Rendition: 2020 May 20
d21
d22
§
§
Ø2
4-4
D
Q
ØT
4
8
5
ØC
7
Ø3
ØR
1
E
CPA
7-6
nF+nJ
5
4
1
S4•F•J
7-6
nF+J
2
3
7-6
F+nJ
7
8
11
S4•nF•J
7-6
F+J
10
9
S4•nF•nJ
Ø2
4-4
D
Q
ØT
3
9
ØC
Ø3
ØR
E
CPA
7-7
5
4
1
7-7
2
3
7-7
7
8
11
7-7
10
9
Ø2
4-4
D
Q
ØT
2
10
ØC
11
Ø3
ØR
E
CPA
7-8
5
4
1
7-8
2
3
7-8
7
8
11
7-8
10
9
Ø2
4-5
D
Q
ØT
4
8
5
ØC
7
Ø3
ØR
1
E
CPA
7-9
J
2
3
1
S1•nJ
7-9
5
4
7-9
10
9
11
7-9
7
8
S1•nF•J•nM
7-11
10
9
11
7-11
7
8
S2•nF•J•nM
Ø2
4-5
D
Q
ØT
3
9
ØC
11
Ø3
ØR
E
CPA
7-10
5
4
1
7-10
2
3
7-10
7
8
11
7-10
10
9
Ø2
4-5
D
Q
ØT
2
10
ØC
Ø3
ØR
E
CPA
S3
H
IDLE to P generator
KEQ•nC•D
KEQ•C•D
S4•F•J
12.1
12
12.3
12.4
12.2
K
K
S2•F•nJ
K
K
S2•nF•J•M
KEQ•nC•nD
d16
d44
K
S6•nF•J
38.3
42.1
K
K
K
K
K
§
K
KEQ•C•nD
C+D
S2•nF•J•nM(K)
S4•F•nJ
S5•F•J
S5•nF•J
S5•nF•nJ
S5•F•nJ
S6•F•J
S6•nF•J
S6•nF•nJ
S6•F•nJ
S2•F•J
S2•nF•J•M
S2•nF•nJ
S2•F•nJ
S1•F•J
S1•nF•J•M
2SA549
50K
2SC641
NK38
NR38
IDLE to keyboard
NR11
NR5

M-6
nF
11
11.1
11.2
11.3
11.4
S6•nF•J
S4•nF•J
S1•F•J
S6•F•J
7-5
S
S1•nF•J•M
7
8
11
300K
VCL
13.1
10
2
1-4
D
CSUB
44.3
SCa
S2•nF•nJ
SCf
52
52.1
52.2
52.3
KEQ•C•D
SCd
KCE'
52.4
55.1
64.3
SCc
31.1
54
44.4
49.4
54.1
54.2
54.3
54.4
64.2
KMC
KMR
K
SCk
CPXDPØD
d19
d25
31.3
SCa
SCg
51
49.3
51.1
24.3
SCe
KNP•(nM+nS)
S6•nF•J
51.2
51.3
51.4
SCb
53.1
MUL•nM•nS
KCE'
SCf
53.2
53.3
53.4
S2•F•J
64.4
SCc
CXØnD11
21.1
S6•F•J
S4•nF•J
21
21.3
21.4
21.2
S6•F•nJ
CBW
SCm
33.4
62
55.3
62.1
62.2
62.3
62.4
64.1
24.1
SCe
KEQ•C•D
SCd
SCb
KCE'
SCf
KNP•F
SCc
CPXØnD13
S2•F•J
K
SCk
S1•nF•J•M
36.3
37.3
14.2
CAM
SCm
S6•nF•J
K
SCg
S1•F•J
48.2
49.2
42.3
CBX
43.1
SCh
SCf
43
43.3
43.4
43.2
MUL•nM•nS
CAW
K
CPXD1
S2•F•nJ
KCE'
47.3
d12
CPXØD13
56.1
SCf
S4•F•J
56
56.2
56.3
56.4
S5•F•J
CPXPW
SCh
KNDP•M•S•nC•nD+KCLR+KMD•S
K
MUL•nM•nS
SCf
44.2
d10
35.1
CWX
45.2
S2•F•nJ
S4•F•J
S5•F•J
57
57.1
57.2
57.3
SCf
35.3
KNDP•M•S•nC•nD+KCLR+KMD•S
CPWØnG
57.4
SCh
KNDP•M•S•nC•nD+KCLR+KMD•S
K
S5•F•J
SCf
44.1
45.1
35.4
CPWPX
CXØD11
SCm
SCf
SCg
MUL•nM•nS
S2•nF•nJ
KCE'
S2•F•J
SCc
SCm
K
SCg
S1•F•J
48.1
49.1
32.1
CTC
K
CWW
SCm
MUL•M•nS
31.2
58.3
35.2
SCh
KNDP•M•S•nC•nD+KCLR+KMD•S
66
66.1
66.2
66.3
SCf
32.2
SCm
CWØ
66.4
MUL•nM•nS
K
M-2
G
S6•nF•J
D1
G
D2
13.2
SCk
S1•nF•J•M
K
14.3
37.2
d17
S2•F•J
CMØ
KMC
24.4
SCa
SCm
SCe
41
31.4
41.1
41.2
nP
KNP•(nM+nS)
SCb
41.3
41.4
45.3
S5•F•J
CAX
S3
K
MUL•M•nS
S2•F•nJ
47.4
58.1
38.2
CPWPW
63
63.1
63.2
63.3
63.4
S6•nF•nJ
S6•nF•J
nP
CSUM
SCm
32.3
K
CMX
S2•F•J
S1•nF•J•M
14.1
36.2
61
61.1
61.2
61.3
61.4
nP
SCb
KNP•F
CPXPX
KEQ•C•D
33.3
S1•nJ
K
CPYPX
KEQ•C•D
33.2
d2
S3
K
CPWØG
SCd
55.2
§
CBWG
S4•nF•J
CPWPY
S4•F•J
CPWDPØD
S1•F•J
CPXD13
S3
CXD12
S2•F•nJ
Sharp Compet 17 Calculator
Section: Control (Outputs)
Page: 9 Rendition: 2020 May 20
§
§
§
§
§
§
§
§
§
§
§
§
SCa
46.1
46.2
46.3
46.4
MUL•M•nS
S1•F•J
S5•F•J
SCk
37.4
SCc
SCd
S3
S4•F•J
38.4
d11
SCe
S2•F•nJ
S1•nJ
47.1
d3
34.1
S5•nF•J
KRC
34.2
34.3
34.4
S1•nF•J•nM
SCf
KEQ•nC•D
SCg
S1•nF•J•M
KS•nC•nD
36.1
d9
SCh
S1•F•J
MUL•M•nS
48.3
58.4
S6•nF•nJ
d1
K
SCb
d7
K
§
§
S4•F•nJ
S5•nF•nJ
S5•F•nJ

Sharp Compet 17 Calculator
Section: Registers
Page: 10 Rendition: 2020 May 20
2SC458
5K
ØD1416
Ø1
82
XØ
CXØnD11
2-7
9
8
11
10
7
CXØD11
8
4
1-5
ØnD11
ØD11
nP
81
2SC458
5K
ØD1416
Ø1
ØD13
nP
Ø2
6-9
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-9
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-8
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-8
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-7
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-7
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
X
E
3-1
ØD12
P
11
10
8
9
7
E
KNUM
Sum
WØ
(CPW)
Ø2
6-3
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-3
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-2
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-2
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-1
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-1
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
W
E
CWW
2-1
3
4
1
2
CWX
X
5
?
E
2SC458
5K
4
5
7-5
MØ
(CPM)
Ø2
6-6
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-6
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-5
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-5
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
Ø2
6-4
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-4
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
M
E
2-4
4
3
1
2
KMC
X
5
?
3
2
7-5
D
?
K
CMX
1
10
2
1-5
D
CWØ
CMØ
E
E
NK44
E
E
D
81
81
81
CXD12
J
CAX
2-2
10
11
8
9
P
CAW
2-2
4
3
2
1
CAM
W
M
5
7
E
E
3-2
CBX
nG
3
2
1
4
3-2
CBW
W
10
11
8
9
5
7
E
E
P
ØD13
G
K
CBWG
Serial
Adder
B In
A In
d38
d37
d14
d39
47.2
d47
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
P
82
82
XØ
(CPX)
NR44

Sharp Compet 17 Calculator
Section: Arithmetic
Page: 11 Rendition: 2020 May 20
E
E
Ø2
4-1
D
Q
ØT
2
10
5
ØC
11
Ø3
ØR
1
d
E
2-3
8
9
10
11
7
ØnD16
E
E
Ø2
4-1
D
Q
ØT
3
9
5
ØC
7
Ø3
ØR
1
E
2-3
3
4
1
2
5
E
Ø1
ØB2
ØB1
Ø2
5-6
D
ØT
7
6
ØC
8
Q4
1
D
Q3
2
D
Q2
3
D
Q1
4
D
XC4
XC3
XC2
XC1
3-1
ØB8
CTC
4
1
3
2
5
E
E
CARRY
H
7-3
11
7,9
8,10
H
Ø2
4-1
D
Q
ØT
4
8
ØC
Ø3
ØR
E
2-1
9
8
10
11
7
E
Ø1
ØnB8
H
7-4
1
3,5
2,4
CSUB
Six Generator
Tens-Carry
Detector
Carry
Latch
Operand
Adder
CSUB
7-3
1
2,4
3,5
7-2
11
8,10
7,9
7-2
1
2,4
3,5
Normalisation
Adder
Sum
H
8
7-4
E
9
10
7
11
Ø1
XØ
11
1
1-6
D
CSUM
ØnD1
A In
B In
Normalisation
Carry Latch
! ! ! Check pin numbers and ordering on IC 5-6 outputs
- might be reversed / 2017-05.

Sharp Compet 17 Calculator
Section: Decimal Point Counters
Page: 12 Rendition: 2020 May 20
Ø2
6-12
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-12
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
CPXPX
2-11
2
1
4
3
P
5
E
PX
E
CPXPW
2-10
3
4
1
2
CPXD1
ØD1
5
CPXD13
2-10
11
10
9
8
CPXDPØD
DPØD
7
E
2SC458
5K
cpx
ØnB8
Ø1
Ø2
4-7
D
Q
ØT
2
10
5
ØC
11
Ø3
ØR
1
CPXØnD13
2-7
1
2
3
4
5
CPXØD13
7
5
1-5
ØnD13
ØD13
nP
11
1
1-7
nPXI
NL35
NK8
PW
ØD13
Ø2
6-11
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-11
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
E
PW
E
CPWPW
2-6
3
4
1
2
CPWPX
PX
5
CPWPY
2-6
11
10
9
8
CPWDPØD
DPØD
7
PY
2SC458
5K
cpw
CPWØG
2-11
9
8
11
10
7
CPWØnG
9
3
1-5
G
nG
2SC458
5K
ØnB8
Ø1
83
nP
cpy
Ø2
6-10
DA1
QA8
ØT
8
9
3
ØC
4
Ø3
ØR
2
Ø2
6-10
DB1
QB8
ØT
6
7
ØC
Ø3
ØR
PX
2-4
9
8
11
10
CPYPX
7
E
PY
E
11
1
1-3
D
83
83
84
84
84
PXI
E
E
E
D
E
E
D
E
D
NR8

n2
nPXI
8
7
7-1
Sharp Compet 17 Calculator
Section: Display
Page: 13 Rendition: 2020 May 20
110K
V+90D
2SC857
DIGITS 11 to 1 (LSD)
NL35
n2
2
V+190
30K
3K
0.1
250V
V+90
10K
2N4888
ØnD13
DIGIT 12 (MSD)
0
1
2
3
4
5
6
7
8
9
.
Hitachi
CD81
1
n1
110K
2SC857
2SC458
15K
110K
2SC857
110K
2SC857
110K
2SC857
110K
2SC857
110K
2SC857
110K
2SC857
110K
2SC857
110K
2SC857
10K
2SC458
10K
10K
2SC458
10K
10K
2SC458
10K
10K
2SC458
10K
9
3
1-2
XC2
NL2
9
10
7-1
n4
4
10
2
1-2
XC3
NL1
3
2
7-1
n8
8
11
1
1-2
XC4
NL3
4
5
7-1
8
4
1-2
XC1
NL4
10K
2SC458
10K
2SC857
1K
n4
n8
2
n4
n2
4
2
4
1S84
ØnB1+3
6
2SC458
40K
2SC458
ØnD1
ØnB1+3
110K
2SC458
20K
20K
50K
200pF
Ø3
40K
11
ØnD1
ØnB1+3
b
b
1
B
B
A
A
A
A
B
B
a
a
a
a
V+90D
V+90D
V+90D
V+90D
V+90D
V+90D
V+90D
V+90D
V+90D
V+90D

Sharp Compet 17 Calculator
Section: Power Supply
Page: 14 Rendition: 2020 May 20
0.1
250V
30K
+74V
30K
NP4
NP1
+200V
115VAC
18W
POWER
black
white
300
50V
300
0.5
AMP.
0.1
red
black
?
AMP.
100K
2SC857
2SD175
10
315V
yellow
µPD2
µPD3
6
12
12
µPD1
6
12
µPD4
6
12
µPD5
5
10
µPD6
5
10
6
µPD7
6
12
470pF
470pF
red
blue
20
35V
1K
1W
10
315V
NM11
NM10
NM6
NM5
NM3
NP2
(VDD)
0.047
250V
3K
1K
NL29
NL30
–17V
NL27
NL28
NL31
NL32
brown
grey
white
9
10
9
7-5
7
8
7-13
Unused Elements
§
NK42
µPD7
6
12
ØnB1+3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-1
3-2
3-3
1-1
1-2
1-3
1-4
1-5
1-6
1-7
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
6-1
6-2
6-3
6-7
6-8
6-9
6-4
6-5
6-6
6-10
6-11
6-12
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-1
NR42
NK10
NR10
192mA
16mA
VCL
V+90
V+190
V+90D
–24V

ØD1416
Øn(D16•B8•1)
0µS
40
600
Sharp Compet 17 Calculator
Section: Timing Diagram
Page: 15 Rendition: 2020 May 20
(47.6 KHz) Ø1
Ø2
Ø3
(11.9 KHz) ØB1
ØB2
ØB4
ØB8
(744 Hz) ØnD1
ØnD2
ØnD16
16
1
PXI
80
120
160
200
240
280
320
360
400
440
480
520
560
2
3
4
5
6
7
8
9
10
11
12
13
14
X
One full number cycle
in registers
Digit being displayed
ØD n
1
(LSD)
2
3
4
5
6
7
8
9
10
11
12
(MSD)
ØnB1+3
600
640
0µS
15
16
X and PXI with
000987654321.
in the display.
logic 0
(–24V)
logic 1
(0V, GND)

NR 1ØnD3 17 key 4 30 KEQ NL XC3 1 2 XC2
2ØnD7 31 KMC § XC4 3 4 XC1
3ØnD1 18 key 5 32 KMR § ØnD16 5 6 T
4ØnD5 19 key 6 33 KMS § ØnD13 7 8 ØnB8
5 K 20 key 7 34 KMAS § ØnD12 910 Ø3
6ØnD4 21 key 8 35 PMANUAL ØnD11 11 12 Ø2
7Ø1 22 key 9 36 — — 13 14 Ø1
8nPXI 23 KCLR 37 —ØnD1 15 16 ØnD1
9 key RC 24 KMD 38 IDLE ØB1 17 18 —
10 VDD 25 KCE 39 Ø3 ØB2 19 20 —
11 K 26 KD 40 PØB4 21 22 —
12 ØB1 27 PTRIGGER 41 —ØB8 23 24 —
13 key 0 28 KDP 42 GND —25 26 —
14 key 1 43 nDPØD GND 27 28 GND
15 key 2 29 KS 44 XVCL 29 30 VCL
16 key 3 45 —VDD 31 32 VDD
—33 34 —
nPXI 35 36 —
—37 38 ØnD4
—39 40 ØnD3
—41 42 ØnD5
—43 44 ØnD7
NK ØnD3 1 2 ØnD7
ØnD1 3 4 ØnD5
K 5 6 ØnD4
Ø1 7 8 nPXI
KRC 910 VDD
K 11 12 ØB1
key 0 13 14 key 1
key 2 15 16 key 3
key 4 17 18 key 5
key 6 19 20 key 7
key 8 21 22 key 9
KCLR 23 24 KMD
KCE 25 26 KD
PTRIGGER 27 28 KDP
KS 29 30 KEQ
§ KMC 31 32 KMR §
§ KMS 33 34 KMAS §
PMANUAL 35 36 lamp *
lamp ÷ 37 38 IDLE
Ø3 39 40 P
— 41 42 GND
nDPØD 43 44 X
Sharp Compet 17 Calculator
Section: IC Pinouts and Gate Construction
Page: 16 Rendition: 2020 May 20
E
C
B
C
D2
G
D1
0
1
2
3
4
5
TDA001
470K
TDA002
0
1
2
3
4
0
1
2
3
4
5
NEC
V380
10
9
8
7
6
1
2
3
4
5
µPD1
GND
–24V
GND
µPD5
–24V
GND
D1
In
ØC
ØT
Q3
Out
Q1
Out
4-bit Shift Register
µPD2
–24V
GND
µPD4
–24V
GND
6
5
4
3
2
1
7
8
9
10
11
12
10
9
8
7
6
1
2
3
4
5
µPD6
–24V
GND
Dual 8-bit Shift Register
µPD7
GND
6
5
4
3
2
1
7
8
9
10
11
12
Q4
Out
Q2
Out
GND
6
5
4
3
2
1
7
8
9
10
11
12
ØR
ØT
ØC
6
5
4
3
2
1
7
8
9
10
11
12
QA8
Out
DA1
In
QB8
Out
DB1
In
ØC
D
ØT
ØR
Q
ØC
D
ØT
ØR
Q
ØC
D
ØT
ØR
Q
–24V
–24V
6
5
4
3
2
1
7
8
9
10
11
12
µPD3
Discrete Gate Construction
Most OR and some AND gates are constructed from discrete diodes and
resistors. More complex logic elements are contained in integrated circuits. The
internal construction of discrete gates is shown in the following diagrams. A
wire–OR or wire–AND construction is indicated by the input line traversing the
width of the gate.
AND Gate OR Gate OR Gate
with ‘wired’input
The diodes and resistors may be individual components or contained in
TDA001 and TDA002 packages.
Most gate outputs have load resistors ( R ) connected from the output to one
side of the power supply. To reduce clutter these resistors are indicated in the
schematic by one of the following letters ( r ) in a box near the output.
Symbol ( r )Resistance ( R )
A 15K to VDD
B20K to VDD
C30K to VDD
D50K to VDD
E100K to VDD
H150K to VDD
J300K to VDD
K300K to VCL
nn 470K to VCL, internal to TDA002 unit nn
a40K to GND
b60K to GND
c100K to GND
d300K to GND
Occasionally individual MOSFET transistors or MOSFETs contained in µPD7
ICs are used as AND gates. The gate of these transistors functions as an
inverted input. Because the MOSFET is a bidirectional device, a diode is usually
required on the other input or the output to prevent ‘backflow’of the signal.
Special mention must be made of the unusual use of a µPD7 for the 4-bit
display latch. Controlling pin 6 allows it to function as a sample-and-hold latch,
presumably relying on inter-electrode capacitance to hold the state between
digit updates (see Display).
R
r
r
r
R
R
NEC V380 or
1/4 of µPD7
C
D2
G
D1
The µPD Integrated Circuit Family
♦Based on supply voltage, circuit impedances and logic density, IC technology is presumed to be early MOS.
♦Gate symbols are presented in accordance with:
logic 1 = 0V, GND
logic 0 = –24V
♦Outputs are open-collector, closing to GND (logic 1) and requiring external pull-down resistor to –24V (logic 0).
♦Inferred for flip-flops:
The flip-flops in this logic family appear to be Master/Slave D-type flip-flops with the clocks for the master and slave sections
kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while all
outputs are changed synchronously by a single clock signal.
ØC = Capture Input (master section clock)
ØT = Transition Input (slave section clock)
The state of the D input is captured when ØC is logic 0 (–24V).
The Q output is set in accordance with the captured state when ØT goes to logic 0.

NR 1ØnD3 17 key 4 30 KEQ NL XC3 1 2 XC2
2ØnD7 31 KMC § XC4 3 4 XC1
3ØnD1 18 key 5 32 KMR § ØnD16 5 6 T
4ØnD5 19 key 6 33 KMS § ØnD13 7 8 ØnB8
5 K 20 key 7 34 KMAS § ØnD12 910 Ø3
6ØnD4 21 key 8 35 PMANUAL ØnD11 11 12 Ø2
7Ø1 22 key 9 36 — — 13 14 Ø1
8nPXI 23 KCLR 37 —ØnD1 15 16 ØnD1
9 key RC 24 KMD 38 IDLE ØB1 17 18 —
10 VDD 25 KCE 39 Ø3 ØB2 19 20 —
11 K 26 KD 40 PØB4 21 22 —
12 ØB1 27 PTRIGGER 41 —ØB8 23 24 —
13 key 0 28 KDP 42 GND —25 26 —
14 key 1 43 nDPØD GND 27 28 GND
15 key 2 29 KS 44 XVCL 29 30 VCL
16 key 3 45 —VDD 31 32 VDD
—33 34 —
nPXI 35 36 —
—37 38 ØnD4
—39 40 ØnD3
—41 42 ØnD5
—43 44 ØnD7
NK ØnD3 1 2 ØnD7
ØnD1 3 4 ØnD5
K 5 6 ØnD4
Ø1 7 8 nPXI
KRC 910 VDD
K 11 12 ØB1
key 0 13 14 key 1
key 2 15 16 key 3
key 4 17 18 key 5
key 6 19 20 key 7
key 8 21 22 key 9
KCLR 23 24 KMD
KCE 25 26 KD
PTRIGGER 27 28 KDP
KS 29 30 KEQ
§ KMC 31 32 KMR §
§ KMS 33 34 KMAS §
PMANUAL 35 36 lamp *
lamp ÷ 37 38 IDLE
Ø3 39 40 P
— 41 42 GND
nDPØD 43 44 X
Display Board
(component side view)
NP01
NP06
1-1
5-5
5-4
5-3
5-2
5-1
1-2
7-1
Sharp Compet 17 Calculator
Section: Physical Layout and Connectors
Page: 17 Rendition: 2020 May 20
03
04
05
01
• Italicised expressions are connections with no signal
name in the schematic.
• ØnDx signals on the NK and NR connectors have a
diode between the connector and the actual signal.
See the Keyboard page.
• The NK and NR connector pins are numerically
correlated.
02
Digit 1
(LSD)
Digit 12
(MSD)
Logic Board
(component side view)
component side:
solder side:
NK43
NK44
NK01
NK02
6-1
6-4
6-7
6-2
6-5
6-8
6-3
6-6
6-9
2-1
2-3
4-1
3-1
7-2
7-3
7-4
2-2
3-2
A8
2-4
3-3
2-8
6-10
2-5
2-9
6-11
2-6
2-10
6-12
2-7
2-11
4-2
1-4
1-3
11
12
15
16
17
21
22
23
24
25
26
27
31
32
33
34
35
38
41
42
43
44
45
46
47
48
49
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
67
7-5
13
14
36
37
92
93
94
8
2
7-6
7-7
7-8
7-9
7-10
7-11
4-3
4-4
4-5
1-5
1-6
7-12
4-6
7-13
7-14
1-7
4-7
2-12
8
1
8
3
8
4
9
1
9
5
9
6
NL43
NL44
NL01
NL02
M-1
M-3
M-4
M-5
M-6
M-7
M-2
M-9
M-10
9
7
9
8
M-8
17
26
18
46
19
8
9
27
25
30
31
29
33
45
32
34
35
36
23
24
20
21
22
16
1
2
3
4
5
6
7
10
11
12
13
14
39
40
15
37
38
41
42
43
44
47
28