Sharp Zaurus SL-5500 User manual

qSERVICE MANUAL
CONTENTS
Parts marked with "!" are important for maintaining the safety of the set. be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
SHARP CORPORATION This document has been published to be used
for after sales service only.
The contents are subject to change without
once.
CODE : 00ZSL5500SM/E
Personal Mobile Tool
MODEL SL-5500
CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CHAPTER 2. HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . 4
CHAPTER 3. DISASSEMBLY AND ASSEMBLY . . . . . . . . . . . . . . . 31
CHAPTER 4. NOTES FOR SERVICING . . . . . . . . . . . . . . . . . . . . . 47
CHAPTER 5. DIAGNOSTICS AND CHECK ITEMS. . . . . . . . . . . . . 50
CHAPTER 6. TROUBLE SHOOTING. . . . . . . . . . . . . . . . . . . . . . . . 60
CHAPTER 7. CIRCUIT DIAGRAM & PARTS LAYOUT . . . . . . . . . . 63
PARTS GUIDE

PC-UM10M
SL-5500 SPECIFICATIONS
– 1 –
CHAPTER 1. SPECIFICATIONS
SL-5500, a Sharp Linux/Java based multimedia PDA, implements Linux 2.4.x (Embedix by Lineo Inc.) as its operating system, Qt/Embedded and Qt
Palmtop Environment (both by Trolltech) for its Linux application platform, and further implements PersonalJava environment (Jeode by Insignia
Solutions) to execute PersonalJava applications.
By implementing both Linux and Java, which are open and standard platform, anyone may develop application software for the SL-5500 by using
existing and easily available tools.
1. PRODUCT SPECIFICATIONS
1-1. BASIC SPECIFICATIONS
The following table provides a brief overview of SL-5500 hardware specifications.
1-2. FUNCTIONAL SPECIFICATIONS
The following table provides a brief overview of SL-5500 functional specifications.
CPU StrongARM (SA-1110, 206 MHz)
Platform Linux 2.4 (Embedix) / PersonalJava (Jeode)
Display Reflective TFT LCD with Front light (Touch-sensitive panel supported)
3.5" with 240 x 320 pixels, 65,536 colors
Memory ROM: 16MB FLASH for OS, Applications, Driver, etc.
RAM: 64MB SDRAM
Input Device Touch panel, Type-writer keyboard
Character Input QWERTY Keyboard with a slide cover, Software keyboard, hand-writing,
Pick board (similar to cellular phone input)
Internet Mail POP3 / IMAP4 / SMTP
File attachment capability
WWW Browser Opera (HTML4.0, JavaScript1.3, CSS1, cookie)
Media Player
(Multimedia Files) MPEG1 (Movie: MPEG1 compliant)
MP3 (Audio: MP3 compliant)
Palmtop (Launcher) Tab bar: on the top of the screen containing Applications, Games, Jeode (PersonalJava runtime environment),
Settings, and Documents.
Launch bar: on the bottom with invoked application icons, migrated with Console, that provides Time, Battery
monitor, and volume control.
Applications Todo List, Calendar, Address Book, Text Editor, Image Viewer, Calculator, City Time, Clock, Help Browser,
Media Player, Opera Browser, E-Mail, System info, Voice Recorder, Hancom Presenter, Hancom Sheet,
Hancom Word
PC Synchronization PC synchronization with Qtopia Desktop

PC-UM10M
SL-5500 SPECIFICATIONS
– 2 –
1-3. COMMON SPECIFICATIONS
The following table provides a brief overview of SL-5500 common hardware specifications.
1-4. INTERFACE SPECIFICATIONS
The following table provides a brief overview of SL-5500 hardware interface specifications.
Power Supply AC Adapter (bundled): 5.0V DC
Replaceable Lithium-ion battery (bundled): 3.7V DC
Memory backup battery (Built-in): 3.0V DC
Battery life When the power of the SL-5500 is turned on at a temperature of under 25°C (75°F), with no peripheral
device (including the CF memory card) connected, after the rechargeable battery (EA-BL06) is fully
charged.
• approx. 10 hours (when you display the Day view mode screen of the Calendar application continu-
ously with the frontlight turned off.)
• approx. 1 hour (when you play the mpeg 1 file continuously with the frontlight at its brightest level
turned on.)
Data storage time When the power of the SL-5500 is turned off at a temperature of under 25°C (75°F) after the brand-new
battery is fully charged.
• approx. 10 days
When the operating battery is exhausted and the power can not be turned on.
• approx. 1 day
When the operating battery is not inserted after the rechargeable back-up battery is fully charged.
• approx. 5 minutes
Number of charging and discharg-
ing of the operating battery life Approx. 500 times. Note: The Battery life and storage time may vary depending on the usage.
Power Consumption 2.5 W (with battery)
6.2 W (with AC adapter)
Temperature Range For operation: 0°C to 40°C (32°F to 104°F)
For charging battery: 5°C to 35°C (37°F to 99°F)
Dimensions
(when the slide cover is closed) Excluding the display protection cover
Approx. 74 (W) x 138 (D) x 18 (H) mm
Approx. 2.9 (W) x 5.4 (D) x 0.7 (H) inches
Including the display protection cover (excluding protruding parts)
Approx. 74 (W) x 138 (D) x 21 (H) mm
Approx. 2.9 (W) x 5.4 (D) x 0.8 (H) inches
Weight Excluding display protection cover: Approx. 194 g (6.8 oz)
Including display protection cover: Approx. 212 g (7.5 oz)
Above values include battery, stylus, and CF Slot Protection Card
Bundled Accessories Docking Station (USB direct coupled cable)
AC adapter (P/N: EA-70, for IN 100-240 VAC) and Power Cord
Lithium-Ion Battery (P/N: EA-BL06)
Stylus, Display Protection Cover, CF Slot Protection Card
Card Slot CF type ΙΙ x 1 (Compact Flash)
SD card x 1 (no copyright protection feature)
I/O Port Infrared (115.2 kbps, Link Distance 5 ~ 20cm)
Serial port (Proprietary 16-pin)
Serial/USB I/F (via docking station) port
Sound Stereo Headphone Jack including Audio input (Mono)
Buzzer

PC-UM10M
SL-5500 SPECIFICATIONS
– 3 –
2. PART NAMES
Front
Back
Rear
Dockng Station
Slide Cover
SHARP I/O PORT
AC Adapter Jack
Keyboard
LED indicator
Calendar key
Cancel key (On/Off key)
Select key
Display
Cursor key
OK key
EMail key
Menu Popup key
(Front light key)
HOME key
Address Book key
Display
Protection
cover
Eyelets for the Handstrap
Battery Compartment Lid
FULL RESET button
Battery Replacement Switch
Stylus
CF Card Slot
CFSlot Protection Card
Stereo Headphone Jack
IR port
SD card slot
Connection
Terminal
(inside)
SYNC
button SHARP I/O PORT
AC Adapter
Jack
USB Cable

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 4 –
CHAPTER 2. HARDWARE DESCRIPTION
1-1. BLOCK DIAGRAM
Touch control
TC35143AF
+
ADC
64pin QFP
INVERTER
CF slot
New GA
MCP mode
I MMU
D MMU
RTC
Timer
GPIO
FRONT LIGHT KEY Board
SDRAM
R:G:B
Headphone
DAC
Sounder
5V
3.3V
1.8V
SSPmode
CLK
BATTERY
Remote Controller
Temp
IRDA
adapter TypeB
Serial
SD CARD
USB Function UART
CS0
AMP
ANALOG OUT
LCD Power circuit
IC COMADJ
CMOS level
Adapter
JTAG
TFT LCD
240 x 320
QVGA
Touch
Screen 206MHz
3.68MHz Osc/PLL
32kHz Osc
Interrupt controller
Powe
Management
Reset
controller
(GPIO10-13)
RS-232
USB
Func
EXPAND connecter
16pin
Serial1 (UART) Serial4
(MCP/SSP) Serial0
(USB) Serial3
(UART) Serial2
(IRDA)
ARM
SA-1 core
I cache
(16k byte)
D cache
(8k byte)
+ mini cache Peripheral
Bridge
LCDC
DMA
Memory &
PCMCIA
control
JTAG
&
Misc Test
SA1110(Strong_ARM)
256pin BGA
DAC
M62332
AUDIO DAC-VR
LCD
timing
control
72pin
QFP
CS4
PWM control
DAC control
Key control
GPIO
Audio CLK
DAC control
SPI
ROM add.decode
128PIN
QFP
16bit bus
16bit bus
32bit bus
CS4
CF Buffer
144PIN
TQFP
IrDA1.2
32bit bus
32bit bus
256Mb
SDRAM x 2 64Mb
FLASH
64Mb
FLASH
POWER
circuit
Main_Batt
Li-ion
(3.7V) B/U_Batt
Charger
circuit

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 5 –
1-2. DETAILED OF BLOCK DIAGRAM
HR_TFT
240*320
RXD3
TXD3
Serial ch3(UART) USB FUNCTION
Adapter
16pin
Docking Station
SERIAL(CMOS-level)
TC35143
CPU
SA1110
206MHz
256pin FBGA
Add Data WE OE
A[10:24]
D[0:15]
D[16:31]
D[0:15]
D[16:31]
SDRAM
FLASH
SDRAM
FLASH
SDCS_0
SDCAS
SDRAS
SDCLK_1
SDCKE_1
DQM_0
DQM_1
DQM_2
DQM_3
PWREN
VPEN
BYTE#
MCS00B
SDCS_0
SDCAS
SDRAS
SDCLK_1
SDCKE_1
DQM_0
DQM_1
DQM_2
DQM_3
nPOE
nPWE
nPIOR
nPIOW
nPCE1/2
PSKTSEL
nPREG
nPWAIT
nIOS16
nPOE
nPWE
nPIOR
nPIOW
nPCE1/2
PSKTSEL
nPREG
nPWAIT
nIOS16
CS0
CS1
CS2
CS3
CS4
CS5
CS4
GA(SCOOP)
L_DD[0:7]
L_DD[8:15]
L_FCLK
L_LCLK
L_PCLK
L_BIAS
GP[2:9]
TXD_C(SIBDOUT)
SCLK_C(SIBCLK)
Serial ch4
RXD_C(SIBDIN)
SFRM_C(SIBSCLK)
ADD[0:25]
DATA[0:31]
RDY
RD/WE#
Memory control
LCD control
PC card control
VS
HS
DCLK
ENAB
(from GA)TFTRESET
R:G:B[6:6:6:]
QDCLK
LP
SPL
CLS
SPS
(from LOCOMO-GPIO7)LCD MOD
TABLET
TSMY/TSMX/
TSPY/TSPX
PANEL
control
LZ9GG314
LCD
Power
circuit
REV/REVV0
OE#
WE#
Main_Batt
SW B/U_Batt
Main_Batt_SW_ON
B/U_Batt_SW_ON
Tablet
Remote controller (KEY)
AIN3
AIN2
AIN1
ANALOG_OUT
VBO2P
FLPWM(from GA)
F/L VR(from GA GPIO9)
CF slot
ADSYNC(from GA)
SW
3VEN
5VEN
CF_IRQ(to CPU GP21)
CF_DETECT(to CPU GP22)
CS4
GA_INT (to CPU GP25)
KSTRB#_B
KI#_B
HS_OUT
DCLK TFTRST(to TFT control)
D[0:15]
A[2:7/23:25]
22.579M18.432M 24.567M
CS0
FROMB_IN
(from CPU GP27)32kOUT
(from PWR circuit)BATT. FAULT
PWREN
KEY
ON
GP11(RXD)
GP10(TXD)
GP13(SFRM)
GP12(SCLK)
DAC(PCM1741)
SSP(TI mode)
R
L
Jack
Headphone
GP19
nRESETIN
nREMOCON_INT
(to CPU GP15)
AMP
NJM2172
R
L
UDC-
UDC+
Serial ch0(USB)
RXD2
TXD2
IrDA1.2
SHDN(IO3/TC35143)
Serial ch2
LEDPWM0(CHARGE)
LEDPWM1(Communication)
Front_Light
to CPU GP0
MCS[0:3]
MCS[0:3]
RTS/CTS/DTR/DSR
WAKEUP(to CPU GP24)
PWR+ / -
GP0
GP1
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP18
GP19
GP20
GP21
GP22
GP23
GP24
GP25
GP26
GP27
ON_KEY
AC_IN
STEREO_TXD
SD_#INT
STEREO_SCLK
STEREO_SFRM
CF_IRQ
nREMOCON_INT
TC35143_RESET
/MIC_ON
nREMOCON_1k_ON
STEREO_64FS
CO
9.21MHz
CF_DETECT
TC35143_IRQ
WAKEUP(16pin)
GA_INT
MainBatt.LOW
32kOUT
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
RTS
CTS
DTR
DSR
LCD_VSHA_ON
LCD_VSHD_ON
LCD_VEE_ON
LCD_MOD
DAC_ON
F/L_VR
DAC_SDATA
DAC_SCK
DAC_SLOAD
nSD_DETECT
nSD_WP
SD_VCC_ON
GA(LOCOMO)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
PCB ver1
TABLET_CHECK
FLPWM
IR_ON
AMP_ON
PCB ver2
Sounder bias
MAIN_BATT_SW_ON
B/U_BATT_SW_ON
TEMP_ON
SW
nREMOCON_1k_ON
(from CPU GP18)
VCC
AIN3
(to TC35143)
SW
MCLK DAC_SDATA
DAC_SCK
DAC_SLOAD LRCLK SCK
SW
DAC_ON
(from LOCOMO)
SD_#INT
GP21(MCP_CLK)
NU
EVR(from
M62332)
STEREO_64FS
(from LOCOMO-CPS)PS
CPS (to TFT panel)
SW
SW
MUTE(from CF
buffer)
SW
TMS
TCK
TDI
TDO
JTAG
TRST
Sounder
(from TC35143)Analog OUT
(from TC35143)Sounder bias
SW
VCC3
D+_1.5k_on(from SCOOP PA19)
DAC
(M62332FP)
(from LOCOMO)SCL
(from LOCOMO)SDA
COMADJ
EVR(to AUDIO AMP)
(from GA-GPIO4)VSHA_ON
(from GA-GPIO5)VSHD_ON
(from GA-GPIO6)VEE_ON VSHA
VSHD
+15V
-15V
-12V
SIBSCLK
SIBDOUT
SIBCLK
SIBDIN
SIBSCLK
SIBDOUT
(from GA) CLK9M
SIBDIN
IRQ(to CPU GP23)
RESET(from CPU GP16)
IRQ
RESET
**
MIC_INPUTVBIN2N
ADSYNC
SW TEMP(to Batt-pack)
TEMP_ON
AIN0
SD_DO
SD_DI
SD_CLK
SD_CS
SW
SD_WP(to GA GPIO14)
nSD_DETECT(to GA GPIO13)
SD_VCC_ON
(to GA GPIO15)
SD card slot
SD_#INT(to CPU GP11)
VCC3
NU
NU
NU
NU
NU
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to SDRAM
to LOCOMO
to LOCOMO
SCOOP
to SCOOP
to SCOOP
to SCOOP
to SCOOP
to SCOOP
to SCOOP
to SCOOP
from SCOOP
from SCOOP
from GA(CLK9M)
to TC35143(SIBDIN)
from TC35143(SIBDOUT)
to TC35143(SIBSCLK)
AMPMIC_INPUT
SW
AVCC3
/MIC_ON
AVCC3
A[2:23]
CS
#RST
WP
VPP
VCC3
PS(to LCDmodule)
MCS00B(to FROM)
VCC
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
CHRG_ON
DIAG_ENTRY
DIAG_ENTRY
MUTE_L
MUTE_R
5V_ON
AMP_ON2
VPEN_ON2
D+_1.5k_ON
DCLK
HS
HS_OUT
CK
D
Q
F/F PA20
PA21
PA22
PXTAL
PEXTAL
3.6864M 32.768K
TXTAL
TEXTAL
nRESET_OUT
BATT_FAULT
VDD_FAULT
PWREN
nRESET_IN
ROMSEL FROM_B
(from LOCOMO)
from PWR circuit
from PWR circuit
NU
to FROM,LOCOMO
D[0:15]
A[0:10/23:25]

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 6 –
2. DESCRIPTION OF LSI
2-1. CPU (SA-1110)
(1) GENERAL DESCRIPTION
The Intel StrongARM* SA-1110 Microprocessor (SA-1110) is a highly
integrated communications microcontroller that incorporates a 32-bit
StrongARM RISC processor core, system support logic, multiple comu-
nication channels, an LCD controller, a memory and PCMCIA controller,
and general-purpose I/O ports.
(2) FEATURES
• High Performance
– 150 Dhrystone 2.1 MIPS @ 133MHz
– 235 Dhrystone 2.1 MIPS @ 206MHz
• Low power (normal mode)*
– <240mW @ 1.55V/133MHz
– <400mW @ 1.75V/206MHz
• Integrated clock generation
– Internal phase-locked loop (PPL)
– 3.686MHz oscillator
– 32.768kHz oscillator
• Power-management features
– Normal (full-on) mode
– Idle (power-down) mode
– Sleep (power-down) mode
• Big and little endian operating modes
• 3.3V I/O interface
• 256-pin mini-BGA package (mBGA)
• 32-way set-associative caches
– 16Kbyte instruction cache
– 8Kbyte write-back data cache
• 32-entry memory-management units
– Maps 4Kbyte, 8Kbyte, or 1Mbyte
• Write buffer
– 8-entry, between 1 and 16bytes each
• Read buffer
– 4-entry, 1, 4, or 8 words
• Memory bus
– Interfaces to ROM, synchronous mask ROM (SMROM), Flash,
SRAM, SRAM-like variable latency I/O, DRAM, and synchronous
DRAM (SDRAM)
– Supports two PCMCIA sockets
*Power dissipation, particularly in idle mode, is strongly dependent on
the details of the system design.
(3) SYSTEM CONFIGURATION
(3)-1. BLOCK DIAGRAM
(3)-2. SA-1110 FUNCTIONAL DIAGRAM
OSC
3.686
MHz
OSC
32.768
KHz
PLL1
PLL2
RTC
OS Timer
General-
Purpose I/O
Interrupt
Controller
Power
Management
Reset
Controller
JTAG
and
Misc
Test
IMMU
DMMU Dcache
(8 Kbytes)
Minicache
Write
Buffer
ARM*
SA-1
Core
Memory and
PCMCIA
Control Module
Bridge DMA
Controller
Serial
Channel 0
UDC
Icache
(8 Kbytes)
Instructions
PC
Addr
Load/Store Data
Read
Buffer
System Bus
LCD
Controller
Peripheral Bus
Serial
Channel 1
GPCLK/UART
Serial
Channel 2
IrDA
Serial
Channel 3
UART
Serial
Channel 4
CODEC
*Other brands and names are the property of their respective owners.
Intel
StrongARM*
SA-1110
Microprocessor
*Other brands and names are the property of their respective owners.
Intel
StrongARM*
SA-1110
[256-pins]
UDC-
UDC+
RXD_1
TXD_1
TXD_C
RXD_C
PEXTAL
PXTAL
TEXTAL
TXTAL
nRESET
nRESET_OUT
SMROM_EN
ROM_SEL
TCK
TDI
TDO
TMS
nTRST
TESTCLK
TCK_BYP
PWR_EN
VDD_FAULT
BATT_FAULT
SCLK_C
SFRM_C
L_DD(7:0)
L_FCLK
L_LCLK
L_PCLK
L_BIAS
GP(27:0)
nCAS/DQM(3:0)
nRAS/nSDCS(3:0)
nOE
nWE
nCS(5:0)
RDY
nSDRAS
nSDCAS
SDCKE<1:0>
SDCLK<2:0>
RD/nWR
nPOE
nPWE
nPIOR
nPIOW
nPCE<2:1>
PSKTSEL
nPREG
nPWAIT
nIOIS16
VDD
VDDX
VSS/VSSX
Serial
Channel 0
(USB)
Serial
Channel 1 RXD_2
TXD_2
RXD_3
TXD_3
Serial
Channel 2
(IrDA)
Serial
Channel 3
(UART)
Serial
Channel 4
(CODEC)
Power
Management
Clocks,Reset
and Test
JTAG
LCD
Control
GPIO Ports
Memory
Control
Transceiver
Control
PCMCIA
Bus
Signals
Supply
D<31:0> Data Bus
A<25:0> Address
Bus

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 7 –
(4) SIGNAL DESCRIPTION
(4)-1. SIGNAL DESCRIPTION
The following table describes the signals.
Key to Signal Types: n:Active low signal
IC:Input, CMOS threshold
ICOCZ:Input, CMOS threshold, output CMOS levels, tristatable
OCZ:Output, CMOS levels, tristatable
Name Type Description
A 25:0 OCZ Memory address bus. This bus signals the address requested for memory accesses.
Bits 24..10 carry the 15-bit DRAM address. The static memory devices and the expansion bus receive
address bits 25..0.
D 31:0 ICOCZ Memory data bus. Bits 15..0 are used for 16-bit data busses.
nCS 5:0 OCZ Static chip selects. These signals are chip selects to static memory devices such as ROM and Flash.
They are Individually programmable in the memory configuration registers. Bits 5..3 can be used with vari-
able latency I/O devices.
RDY IC Static data ready signal for nCS 5:3. This signal should be connected to the data ready output pins of vari-
able latency I/O devices that require variable data latencies. Devices selected by nCS 5:3 can share the
RDY pin if they drive it high prior to tristating and a weak external pull-up is present.
nOE OCZ Memory output enable. This signal should be connected to the output enables of memory devices to con-
trol their data bus drivers.
nWE OCZ Memory write enable. This signal should be connected to the write enables of memory devices. This sig-
nal is used in conjunction with nCAS 3:0 to perform byte writes.
nRAS 3:0/nSDCS 3:0 OCZ DRAM RAS or SDRAM CS for banks 0 through 3. These signals should be connected to the row address
strobe (RAS) pins for asynchronous DRAM or the chip select (CS) pins for SDRAM.
nCAS 3:0/DQM 3:0 OCZ DRAM CAS or SDRAM DQM for data banks 0 through 3. These signals should be connected to the col-
umn address strobe (CAS) pins for asynchronous DRAM or the data output mask enables (DQM) for
SDRAM.
nSDRAS OCZ SDRAM RAS. This signal should be connected to the row address strobe (RAS) pins for all banks of
SDRAM.
nSDCAS OCZ SDRAM CAS. This signal should be connected to the column address strobe (CAS) pins for all banks of
SDRAM.
SDCKE 1:0
OCZ SDRAM and/or SMROM clock enables.
SDCKE 0 should be connected to the clock enable (CKE) pins of SMROM.
SDCKE 0 is asserted upon any rest (including sleep-exit) if static memory bank 0 (boot space) is config-
ured for synchronous mask ROM (SMROM_EN = 1);otherwise it is deasserted upon reset.
SDCKE 1 should be connected to the clock enable pins of SDRAM. They are deasserted (held low) during
sleep. SDCKE 1 always is deasserted upon reset.
The memory controller provides control register bits for deassertion of each SDCKE pin. However,
SDCKE 0 cannot be deasserted via program if SMROM_EN = 1.
CDCLK 2:0 OCZ SDRAM and/or SMROM clock.
SDCLK 0 should be connected to the clock (CLK) pins of SMROM.
SDCLK 1 and SDCLK 2 should be connected to the clock pins of SDRAM in bank pairs 0/1 and 2/3,
respectively. They are driven by either the internal memory controller clock (CPU clock divided by 2) or the
memory controller clock divided by 2 (CPU clock divided by 4).
All SDCLK pins are held low during sleep mode and start running at CPU clock divide by 4 upon any reset
(including sleep-exit).
The memory controller provides control register bits for clock division and disable of each SDCLK pin.
However, SDCLK 0 cannot be disabled via program if static memory bank 0 (boot space) is configured for
synchronous mask ROM (SMROM_EN = 1).
RD/nWR OCZ Read/write direction control for memory and PCMCIA data bus (D 31:0). This signal is applicable to all
memory bus and PCMCIA transfers.
For reads (RD/nWR = 1), system-level bus transceivers or directly connected memory devices should
drive D 31:0.
For writes (RD/nWR = 0), the SA-1110 will drive D 31:0.
nPOE OCZ PCMCIA output enable. This signal is an output and is used to perform reads from memory and attribute
space.
nPWE OCZ PCMCIA write enable. This signal is an output and is used to perform writes to memory and attribute
space.

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 8 –
nPIOW OCZ PCMCIA I/O write. This signal is an output and is used to perform write transactions to the PCMCIA I/O
space.
nPIOR OCZ PCMCIA I/O read. This signal is an output and is used to perform read transactions from the PCMCIA I/O
space.
nPCE 2:1 OCZ PCMCIA card enable. These signals are output and are used to select a PCMCIA card. nPCE 2 enables
the high-byte lane and nPCE 1 enables the low-byte lane.
nIOIS16 IC I/O Select 16. This signal is an input and is an acknowledgment from the PCMCIA card that it can perform
16-bit I/O data transfers.
nPWAIT IC PCMCIA wait. This signal is an input and is driven low by the PCMCIA card to extend the duration of
transfers to/from the SA-1110.
PSKTSEL OCZ PCMCIA socket select. This signal is an output and used by external steering logic to route control,
address, and data signals to one of the PCMCIA sockets. When PSKTSEL is low, socket zero is selected.
When PSKTSEL is high, socket one is selected. This signal has the same timing as the address lines.
nPREG OCZ PCMCIA register select. This signal is an output and indicates that, on a memory transaction, the target
address is attribute space. This signal has the same timing as address.
L_DD 7:0 OCZ LCD controller display data.
L_FCLK OCZ LCD frame clock.
L_LCLK OCZ LCD line clock.
L_PCLK OCZ LCD pixel clock.
L_BIAS OCZ LCD ac bias drive.
TXD_C OCZ CODEC transmit.
RXD_C IC CODEC receive.
SCLK_C OCZ CODEC clock.
SFRM_C OCZ CODEC frame signal
UDC+ ICOCZ Serial port zero bidirectional, differential signalling pin (UDC).
UDC ICOCZ Serial port zero bidirectional, differential signalling pin (UDC).
TXD_1 OCZ Serial port one transmit pin (UART).
RXD_1 IC Serial port one receive pin (UART).
TXD_2 OCZ Serial port two transmit pin (IrDA).
RXD_2 IC Serial port two receive pin (IrDA).
TXD_3 OCZ Serial port three transmit pin (UART).
RXD_3 IC Serial port three receive pin (UART).
GP 27:0 ICOCZ General-purpose input output.
SMROM_EN IC Synchronous mask ROM (SMROM) enable. This pin is used to determine if the boot ROM (static memory
bank 0) is asynchronous or synchronous. If asynchronous, boot ROM is selected (SMROM_EN = 0) and
its width is determined by the state of the ROM_SEL pin. SMROM is supported only on 32-bit data bus-
ses.
ROM_SEL IC ROM select. This pin is used to configure the ROM width. It is either grounded or pulled high. If ROM_SEL
is grounded, the ROM width is 16 bits. If ROM_SEL is pulled up, the ROM width is 32 bits.
PXTAL IC Input connection for 3.686-MHz crystal (non-CMOS threshold).
PEXTAL OCZ Output connection for 3.686-MHz crystal (non-CMOS level).
TXTAL IC Input connection for 32.768-kHz crystal (non-CMOS threshold).
TEXTAL OCZ Output connection for 32.768-kHz crystal (non-CMOS level).
PWR_EN OCZ Power enable. Active high. PWR_EN enables the external VDD power supply. Deasserting it signals the
power supply that the system is going into sleep mode and that the VDD power supply should be
removed.
BATT_FAULT IC Battery fault. Signals the SA-1110 that the main power source is going away (battery is low or has been
removed from the system). The assertion of BATT_FAULT causes the SA-1110 to enter sleep mode. The
SA-1110 will not recognize a wake-up event while this signal is asserted.
VDD_FAULT IC VDD fault. Signals the SA-1110 that the main power supply is going out of regulation (shorted card is
inserted). VDD_FAULT will cause the SA-1110 to enter sleep mode. VDD_FAULT is ignored after a wake-
up event untill the power supply timer completes (approximately 10ms).
nRESET IC Hard reset. This active low signal is a level-sensitive input used to start the processor from a known
address. A low level will cause the current instruction to terminate abnormally, and the on-chip caches,
MMU, and write buffer to be disabled.
When nRESET is driven high, the processor will restart from address 0. nRESET must remain low until
the power supply is stable and the internal 3.686-MHz oscillator has come up to speed. While nRESET is
low, the processor will perform idle cycles.
Name Type Description

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 9 –
2-2. ANALOG FRONT END LSI (TC35143AF)
(1) OUTLINE
TC35143AF is an analog front end LSI suitable for personal digital
assistants (PDA) including HPC. It consists of a V.34 modem tele-phone
line interface, sound interface compatible with the handsfree / handset
system, and touch screen interface. The communication with the host
processor is performed through the SIB (Serial Interface Bus). The LSI
is connectable to a master processor with an SIB interface. Clocks used
inside the TC35143AF are generated from the serial transfer clocks of
the SIB interface. There is no need for any clock oscillator. Sampling
data, control signals and status of each interface block is communicated
with the host processor through the SIB interface.
(2) FEATURES
(2)-1. TELEPHONE LINE INTERFACE
• 16-bit ADC/DAC
• Programmable input amplifier gain (2-stage, in steps of 6dB)
• Full differential telephone line interface
• Analog echo canceller is incorporated
• Programmable sampling frequency (3-stage : 7.2 kHz, 8 kHz, 9.6
kHz)
(2)-2. SOUND INTERFACE
• 14-bit ADC/DAC
• 2 mike input lines, 2 speaker output lines (supports handsfree, hand-
set system)
• Power On/Off function for each block
• Mike input mute switch, speaker input mute switch
• Programmable mike amplifier gain (2 types: 15 stages in steps of
1.5dB and 4 stages in steps of 6dB)
• Programmable speaker output level attenuator (8 stages in steps of
3dB)
• Programmable sampling frequency (4 stages in steps of 8 kHz, about
11.03 kHz, 16 kHz, about 22.05 kHz)
(2)-3. TOUCH SCREEN INTERFACE
• Voltage measurement 10-bit ADC
• Touch starting mode from stand-by state
• Plate applied voltage generation circuit
• General-purpose analog input port (4 inputs)
(2)-4. OTHERS
• Interrupt output port (programmable interrupt factor setting function)
• Multichip connection through SIB interface (SIB clock input fixed to
9.216 MHz)
• General-purpose I/O port (10 ch)
• +3.3V battery power supply
• 64-pin QFP package
(3) SYSTEM BLOCK DIAGRAM
nRESET_OUT OCZ Reset out. This signal is asserted when nRESET is asserted and deasserts when the processor has com-
pleted resetting. nRESET_OUT is also asserted for "soft" reset events (sleep and watchdog).
nTRST IC Test interface reset. Note this pin has an internal pull-down resistor and must be driven high to enable the
JTAG circuitry. If left unconnected, this pin is pulled low and disables JTAG operation.
TDI IC JTAG test interface data input. Note this pin has an internal pull-up resistor.
TDO OCZ JTAG test interface data output. Note this pin does not have an internal pull-up resistor.
TMS IC JTAG test interface mode select. Note this pin has an internal pull-up resistor.
TCK IC JTAG test interface reference clock. This times all the transfers on the JTAG test interface. Note this pin
has an internal pull-down resistor.
TCK_BYP IC Test clock PLL bypass. When TCK_BYP is high, the TESTCLK is used as the core clock in place of the
PLL clock; when low, the internal PLL output is used. This signal has no relation to the JTAG TCK pin.
TESTCLK IC Test clock . TESTCLK is used to provide the core clock when TCK_BYP is high. It should be tied low if
TCK_BYP is low. This pin should be used for test purposes only. An end user should ground this pin.
VDD – Positive supply for the core. Nine pins are allocated to this supply; eight pins are labeled VDD. The ninth
pin, labeled VDDP is dedicated to the PLL supply and should have its own dedicated decoupling capaci-
tor. Also, it should be tied directly to the VDD power plane with the other eight VDD pins.
VDDX – Positive supply for the pins. For a count of VDDX pins. All of the pins allocated to VDDX (labeled VDDX1,
VDDX2, and VDDX3) should be tied directly to the VDDX power plane. VDDX3 should have its own dedi-
cated decoupling capacitor.
VSS – Ground supply. Nine pins are allocated to VSS, including one for the PLL.
VSSX – Ground supply for the I/O pins. "Package and Pinout", for a count of VSSX pins.
Name Type Description
RAM
Battery
3.3V
SCLK TC35143F
SDOUT
SDIN
SSYNC
IRQ M
NCU
Data Bus
Flash
ROM Peripheral
SIB master
processor
Tou ch
Screen

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 10 –
(4) PIN DESCRIPTION
(5) PIN FUNCTION
GPIO0
N.C.
DVSS1
-RST
SSYNC
SDOUT
SCLK
SDIN
IRQ
N.N.
GPIO4
GPIO5
DVDD2
GPIO1
GPIO2
GPIO3
AVDD4
TELOP
AVDD3
N.C.
VREF
MICBIAS
AVSS2
VBIN2N
VBIN2P
VBIN1N
VBIN1P
AVDD2
N.C.
N.C.
AVSS3
TELON
DVDD1 TSMY TSMX TSPY AVSS5 AIN0 CVSS2 AVSS4 TELIN TELIP EXRINT AVDD5 TSPX
GPIO6
ADSYNC
TEST2 TEST1
DVSS2
N.C.
CVSS1
AVDD1 VBO1P
VBO1N
VBO2P
VBO2N
AVSS1
GPIO7 GPIO8 GPIO9
AIN1 AIN2 AIN3
49 3348 32
64 17
116
TOP VIEW
Symbol Pin No. A/D/P I/O DEF Group Deption
SCLK 58 D I – HOST Serial data transfer clock. Serial data is transferred synchronizing with this clock.
SCLK is used as the master clock for TC35143AF. The specification of SCLK is 9.216 MHz,
with duty ratio 50%. Connect to the clock output of SIB master chip.
SSYNC 56 D I HOST This signal provides synchronization for serial data frames. 72kHz clock. 1 frame consists
of 128 bits of serial data. Connect to the synchronizing signal output of SIB master chip.
SDIN 59 D I HOST Serial input data terminal. Serial data input through the SDIN terminal is latched inside at
the falling edge of SCLK. Connect to the data output of SIB master chip.
SDOUT 57 D O HZ HOST Serial output data terminal. Serial data output through SDOUT terminal is output, synchro-
nizing with the rising edge of SCLK. Connect to the data input of SIB masterchip.
IRQ 60 D O L HOST Interrupt output terminal. Interrupt factors output from the control resistor to this terminal
are set. The signal level at the time of interrupt is active high.
RST 55 D I – HOST System reset. This signal is active low.
TSPX 45 A I/O HZ(IN) TSC Interface terminal for touch screen X plate. Open when not in use.
TSMX 43 A I/O HZ(IN) TSC Interface terminal for touch screen X place. Open when not in use.
TSPY 42 A I/O HZ(IN) TSC Interface terminal for touch screen Y plate. Open when not in use.
TSMY 44 A I/O HZ(IN) TSC Interface terminal for touch screen Y plate. Open when not in use.
AIN0 40 A I – ADC ADC input
AIN1 39 A I – ADC ADC input
AIN2 38 A I – ADC ADC input
AIN3 37 A I – ADC ADC input
ADSYNC 5 D I – ADC Synchronizing clock input terminal when putting 10-bit ADC in the external clock synchro-
nizing mode. ADC starts conversion synchronizing with the edge of ADSYNC.Pull down
when not in use.
EXRINT 47 A I – TSC Terminal to which external resistance is connected, for adjusting detection sensitivity in
touch detection mode. Connect a resistance of more than 16kΩbetween AVDD5.
TELOP 28 A O HZ TEL Positive polarity output terminal for telephone line CODEC
TELON 29 A O HZ TEL Negative polarity output terminal for telephone line CODEC
TELIP 33 A I – TEL Positive polarity input terminal for telephone line CODEC. Open when not in use.
TELIN 34 A I – TEL Negative polarity input terminal for telephone line CODEC. Open when not in use.
VBO1P 12 A O HZ VB Positive polarity output terminal 1 for sound CODEC. It is used for the handset speaker.
VBO1N 13 A O HZ VB Negative polarity output terminal 1 for sound CODEC. It is used for the handset speaker.

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 11 –
Note:
• A/D/P mean an Analog terminal, Digital terminal, and Power terminal.
• DEF means reset state. H/L stand for output levels. Hz means high impedance and IN means input state (high impedance).
• Group categories are as follows :
HOST-Host interface, TSC-Touch screen interface, TEL-Telecom CODE, VB-Voice band CODEC, ETC-The other, POW-power supply.
VBO2P 14 A O HZ VB Positive polarity output terminal 2 for sound CODEC. It is used for the external speaker.
VBO2N 15 A O HZ VB Negative polarity output terminal 2 for sound CODEC. It is used for the external speaker.
VB1N1P 19 A I – VB Positive polarity input terminal 1 for sound CODEC. It is used for the hand mike. Open
when not in use.
VBIN1N 20 A I – VB Negative polarity input terminal 1 for sound CODEC. It is used for the hand mike. Open
when not in use.
VBIN2P 21 A I – VB Positive polarity input terminal 2 for sound CODEC. It is used for the external mike. Open
when not in use.
VBIN2N 22 A I – VB Negative polarity input terminal 2 for sound CODEC. It is used for the external mike. Open
when not in use.
MICBIAS 24 A O HZ VB This is a power supply terminal for an electret condenser mphone. Insert a 2-kΩresistance
and more than 10µF electrolytic capacitor in series between this pin and the analog GND.
GPIO0 49 D I/O HZ(IN) GPIO These are general-purpose I/O ports. The selection of input and output and the output level
are set by the control resistor. After resetting, the ports are put in the input mode as a
default state. Pull down when not in use.
GPIO1 50 D I/O HZ(IN) GPIO GPIO
GPIO2 51 D I/O HZ(IN) GPIO GPIO
GPIO3 52 D I/O HZ(IN) GPIO GPIO
GPIO4 62 D I/O HZ(IN) GPIO GPIO
GPIO5 63 D I/O HZ(IN) GPIO GPIO
GPIO6 1 D I/O HZ(IN) GPIO GPIO
GPIO7 2 D I/O HZ(IN) GPIO GPIO
GPIO8 3 D I/O HZ(IN) GPIO GPIO
GPIO9 4 D I/O HZ(IN) GPIO GPIO
TEST1 7 D I – ETC Test pin. Fix to GND.
TEST2 6 D I – ETC Test pin. Fix to GND.
VREF 25 A I/O HZ
(OUT) ETC This pin is an internal analog reference voltage. Insert an electrolytic capacitor of more than 10µF between this pin and analog GND. The attributes of input and output, are deter-
mined by resistor setting.
DVDD1 48 P – – POW This pin is a digital power supply. Fix to +3.3V. Insert a 0.1µF laminated ceramic capacitor
between this pin and the digital VSS of the same number. Insert the capacitor as close to
the pin as possible.
DVDD2 64 P – – POW
AVDD1 11 P – – POW This pin is an analog power supply. Fix to +3.3 V. Insert a 0.1µF laminated ceramic capaci-
tor between this pin and the analog VSS of the same number. Insert the capacitor as close
to the pin as possible.
AVDD2 18 P – – POW
AVDD3 27 P – – POW
AVDD4 32 P – – POW
AVDD5 46 P – – POW
DVSS1 54 P – – POW Connect this pin to the digital GND. The pattern must be designed so that this pin is sepa-
rated from the analog GND.
DVSS2 8 P – – POW
AVSS1 16 P – – POW Connect this pin to the analog GND. The pattern must be designed so that this pin is sepa-
rated from the digital GND.
AVSS2 23 P – – POW
AVSS3 30 P – – POW
AVSS4 35 P – – POW
AVSS5 41 P – – POW
CVSS1 10 P – – POW This is a common GND for the analog and digital sections. Connect this pin to theanalog
GND.
CVSS2 36 P – – POW
N.C. 9, 17,
26,31,
53, 61
– – – – Non-connection pin. Make is open.
Symbol Pin No. A/D/P I/O DEF Group Deption

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 12 –
(6) HARDWARE INTERFACE
2-3. 256Mbit SDRAM (K4S561633C-RL75)
(1) DESCRIPTION
The K4S561633C is 268, 435, 456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4, 196, 304 words by 16 bits, fabricated
with SAMSUNG’s high performance CMOS technology. Synchronous
design allows precise cycle control with the use of system clock and I/O
transactions are possible on every clock cycle. Range of operating fre-
quencies, programmable burst length and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
(2) PIN CONFIGURATION
(3) PIN FUNCTION
2-4. 64Mbit FLASH MEMORY (LF28F640BX)
(1) DESCRIPTION
The LH28F640BX series page-mode dual-work flash memory has the
following features.
• Dual work function
• Settable partition configuration
• Page buffer program
• Data protection function for each block and full-block lock function at
power-on.
• 8-word OTP (One Time Program) block
• Low power consumption
• Parameter block configuration
TELOP
Relay
ON/OFF
TELON
SCLK
SSYNC
SDIN
SDOUT
TELIP
TELIN
VBO1P
VBO1N
VBI1P
VBI1N
VBI2P
VBI2N
IRQ
-RST
TEST1
TEST2
TSPY
TSPX
TSMY
TSMX
VBO2P
VBO2N
DVDD1 to
DVDD2
DVSS1 to
DVSS2 AIN0
AIN1
AIN2
AIN3
AVDD1 to
AVDD2
AVSS1 to
AVSS2
CVSS1 to
CVSS2
VREF GPIO[9:0]
TC35143AF
Hand-set
Microphone
Speaker
Digital
power
supply
Digital
grand
Analog
power
supply
Analog
grand
SIB
I/F
Touch
Screen
Power
Supply
Main Battery
Backup Battery
SIB master processor
System
Analog signal
NCU control
Detection
of telephone
line
54Ball (6 x 9) CSP
123789
A VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE CAS RAS WE
G A12 A11 A9 BA0 BA1 CS
HA8A7A6A0A1A10
J VSS A5 A4 A3 A2 VDD
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0~A12 Address
BA0~BA1 Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L (U) DQM Data Input/Output Mask
DQ0~15 Data Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
123456789
A
B
C
D
E
F
G
H
J

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 13 –
(2) PIN CONFIGURATION
(3) PIN NAMES
2-5. GATE ARRAY SPECIFICATION
(1) GENERAL DESCRIPTION
The LOCOMO-QFP15-128pin G/A (SLA5075H) is a gate array devel-
oped for the SL-5500.
The outlines of built-in functions are described below.
(2) FUNCTION DESCRIPTION
(2)-1. BOOT SWITCHING, MCS DECODER [memc]
(2)-1-1. Outline
This module divides the area of chip select signal connected to cs0_b
and cs1_b pins into mos00_b, mos01_b, mos02_b, mos03_b, mos10_b,
mos11_b, mos12_b, and mos13_b according to the capacity of memory
to be connected.
In addition, the module detects the connection of FROM with from_b. If
FROM is inserted, os0_b is replaced with os1_b and decoded to start
from memory connected to os1_b.
This module is not affected by the state of pwren or battfault.
(2)-1-2. Block diagram
Here is a block diagram of this module.
Symbol Type Name and function
A0-A21 Input Address input: Address input pin 64M: A0-
A21
DQ0-DQ15 Input/
Output Data I/O: This pin outputs data that is writ- ten to CUI (Command User Interface), com-
mand input, memory array, status register,
query code, ID code, and device configura-
tion code read data. When the chip is not
selected or output is disabled, the pin is at
high impedance (High Z). Data is erased or
latched internally while a program is run-
ning.
CE# Input Chip enable: This pin activates device con-
trol logic, input buffer, decoder and sense
amplifier. When CE# is VIH, device is not
selected and power turns to stand-by level.
RST# Input Reset: When RST# is VIL, the inside of
device is automatically reset to prohibit era-
sure and running of the program, thus pro-
tecting data. When RST# is VIH, device is
set to usual operation mode.
After power is turned on, or after power is
restored from the reset mode, device is
automatically set to a synchronous array
read mode.
when power is turned on, RST# needs to be
set to VIL.
OE# Input Output enable: This pin controls the output
terminal of device in reading.
WE# Input Write enable: This pin controls writing to
CUI and memory array. The address and
data are latched at the leading edge of CE#
or WE# whichever comes first.
WP# Input Write protect: When WP# is VIL, The
release of lock bit in the block to which lock-
down bit is set is prohibited. For blocks to
which either lock bit or lock-down bit is not
set, erasure or program operation can be
performed. Lock-down bit can be disabled
by putting WP# in VIH.
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A21 9
A20 10
WE# 11
RST# 12
VPP 13
WP# 14
A19 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
A1648 VCCQ47 GND46 DQ1545 DQ744 DQ1443 DQ642 DQ1341 DQ540 DQ1239 DQ438 VCC37 DQ1136 DQ335 DQ1034 DQ233 DQ932 DQ131 DQ830 DQ029 OE#28 GND27 CE#26 A025
48-LEAD TSOP
STANDARD PINOUT
12mm x 20mm
TOP VIEW
VPP Input Power supply voltage detection pin: VPP is
not a power supply pin. When VPP VPPLK,
it is not possible to execute block erasure,
full-chip erasure, (page buffer) program or
OTP program. Do not try to execute such
operations.
High-speed erasure and high-speed pro-
gram operation can be executed by apply-
ing a voltage of 12V m0.3 V to VPP, and at
this time, VPP acts as a power supply pin.
If VPP voltage is used at 12V m0.3V during
erasure or the running of a program, the
number of rewrites per block is up to 1000.
If 12V m0.3V is applied to VPP pin, it is
required to set up to 80 hours in accumula-
tion. If more than 12V is applied to VPP,
there is a possibility of reducing the number
of rewrites or irreversible destruction.
VCC Supply Device power supply (see delivery specifi-
cation): When VCCVLKO, writing to flash
memory is prohibited. If the system is used
at an invalid VCC voltage (see DC charac-
teristics), malfunction might result. Do not
use the system at such a state.
VCCQ Supply I/O power supply (see delivery specifica-
tion); Power supply for I/O pin
GND Supply Ground: All ground pins need to be con-
nected.
NC This pin is not connected to the internal cir-
cuit. It may be used in open state.
Symbol Type Name and function
memc
from_b mcs*0_b
mcs*1_b
mcs*2_b
mcs*3_b
cs0_b,cs1_b
adr[25:23]
mcsx[1:3] mcsx0
CPU bus Register
Decoder
Decoder

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 14 –
(2)-2. SPI I/F
(2)-2-1. Outline
This module interfaces SD card and MMC in the SPI mode and has the
following features:
• Capable of interfacing multiple SD cards and MMCs. However, since
there is a single spics_b, control is required using GP10 and others.
• spidi needs a pull-up resistance outside.
• Clock synchronous type serial port and data length can be selected
between 8 and 16 bits.
The data length set forth in this specification is called unit.
• Double buffers for transmission and reception (no FIFO) make it pos-
sible to perform transmission and reception continuously.
• In transmission and reception, it is possible to select whether data
alignment (transmission and reception synchronized in the unit of
“unit”) is carried out or not can be selected.
• Clock frequency can be selected from among 15 bands (24.576MHz -
2.304MHz and 384 kHz - 288 KHz).
• There are 4 interrupts including reception data read enable, transmis-
sion data write enable, transmission end, and reception end. They
can be separately allowed or prohibited.
• When this module is not in use, clock can be stopped to reduce
power consumption.
• MSB/LSB first can be selected.
• Transmission and reception bit can be freely reversed.
• Test can be performed by looping back the status of spido to spidi,
without suing any jig.
• The timing between transmission and reception data and clock can
be set. The status of spido can be set after data is transmitted or
received or while data is only received.
• This module is not affected by pwren, but when battfault is at L, it is
reset.
(2)-2-2. Block diagram
Here is a block diagram of this module.
(2)-3. FRONT LIGHT CONTROL
(2)-3-1. Outline
• This module outputs the pulse modulation output signal for controlling
the front light DUTY. It has the following features:
• Front light DUTY control pulse modulation output (Cycle and DUTY
can be changed)
• Fixed output at PWREN and internal Enbit
• Inverted output at INVbit is possible
• When BATTFAULT pin input level is Low, the register of this module is
initialized.
(2)-3-2. Block diagram
(2)-4. LED CONTROLLER
(2)-4-1. Outline
This module outputs the pulse modulation output signal for LED light
emission to the LEDPWM0, 1 pins. It has the following features:
• Outputs the pulse modulation output signal for LED light emission to
the LEDPWM0, 1 pins. Cycle and DUTY can be separately changed.
• When the BATTFAULT pin input level is at Low, the register of this
module is initialized.
(2)-4-2. Block diagram
(2)-5. TOSHIBA ANALOG FRONT END LSI OSCILLATION
CIRCUIT
(2)-5-1. Outline
This module outputs 9.216MHz clock signal to Toshiba analog end LSI
(TC35143AF). It has the following features:
• Outputs 9.216MHz clock signal from LCK9M pin.
• The registers of this module are initializedwhen BATTFAULTpin input
level is at LOW.
• This module is not affected by pwren pin input.
• Capable of monitoring the same signal as that from CLK9M pin using
the status register (04h) bit1 (clk9m).
(2)-5-2. Block diagram (Here is a circuit image.)
spimod
spictl
spiint
clkgen
GPIO
spitxd
spirxd
spitsd
spirsd
DI
DOWP CD
CS
SCLK
spics_b (2)
spiif
interrupt
24.576MHz
22.5792MHz
18.432MHz
LoCoMo
spiclk
spics_b
spidi
spido
Oscillation
control
moduel
CPU bus
PWB
Transmission and
reception control
Register
SD card
/ MMC
#2
SD cards
/ MMC
#1
Power
supply
INVENHSYEN
BPDF
8-0
BPWF
7-0
HSYS signal
(touch panel
control)
rtc32k
input pin
CPU bus
Internal flpwn
signal
Register setting
Initialize
pwren input pin
flpwm output pin
battfault input pin
Inversion
function
LEDPWM1LEDPWM0
CLK32K Internal ledpwm signal
Register setting
CPU bus Initialize
ledpwm0 output pin
ledpwm1 output pin
battfault input pin
CLK9MENXON Initialize
Xout 18m
output pin
Xin 18m
input pin
CPU bus
1/2
dividing
circuit
Register settings
to Xout 18 (18.432 MHz)
SPI/CLK32K block
Internal status register
bit 1(CLK9M)
CLK9M output pin
battfault input pin
SPI block
XON signal
CLK32K block
XON signal

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 15 –
(2)-6. PCM AUDIO INTERFACE
(2)-6-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• This module is not affected by pwren pin input.
• Converts audio data from Ti Audio Format generated by the SSP of
the CPU into Standard Data Format.
(2)-6-2. Block diagram
(2)-7. AUDIO CLOCK
(2)-7-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• When pwren pin input level is at LOW, the output of mclk and clk64fs
pins becomes LOW regardless of the register settings.
• Capable of monitoring the same signal as those from MCLK /
CLK64FS pins using the status register (04h) bit 0 (MCLK) / bit0
(CLK64FS).
(2)-7-2. Block diagram
(2)-8. GENERAL-PURPOSE 8-bit 2ch DAC CONTROL
SIGNAL
(2)-8-1. Outline
• The registers of this module are initialized when BATTFAULT pin input
level is at LOW.
• The operation of this module does not depend upon the input level of
the pwren pin.
Buffer of each pin:
SCL OUTPUT N-CH Open Drain 5-V withstand voltage, 2mA
SDA INPUT 5-V withstand voltage, 2mA (not a feed-through current
prevention
buffer)
(2)-8-2. Block diagram
(2)-9. TFT-RELATED SIGNAL
(2)-9-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input lever is at LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-9-2. Block diagram
(2)-10. INTERRUPT CONTROLLER
(2)-10-1. Outline
• The registers of this module are initialized when batterfault pin input
level is LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-10-2. Block diagram (Here is a circuit image.)
LRCENSCENLRCINVLRCEVELRCRSTSCINV
TiAudio Format
Standard Data Format
Initialize
sclk
pin
sfrm
pin
CPU bus
lrclk
Reset
lrclk
Leading
and trailing
sclk
Inversion
Register settings
dacsck
output pin
lrclk
output pin
battfault
input pin
lrclk
Inversion
XSELXON XEN CLKSEL
[2:0] MCLKEN CLK64FS EN
3
Xout24m output pin
Xin24m input pin
Xout22m output pin
Xin22m input pin
CPU bus
Dividing
circuits
Register settings
Initialize
Internal status register
bit10(MCLK)
MCLK
output pin
Internal register
bit*(CLK64FS)
CLK64FS
output pin
battfault
input pin
48KHz System
44.1KHz System
F/F
F/F
F/F
F/F
3.3~
5.0V
2ch
1ch
CPU
bus
Register settings
Initialize
DAC power supply ON
sda
Input pin
scl
output pin
battfault
input pin
sda
I/O pin
scl
input pin
Power supply
ON/OFF
General-purpose
8-bit DAC
(Mitsubishi
M62332FP)
LCD
COMADJ
Backlight
voltage
light
control
DO
DI SDA
SDAOEB
SCLOEB
CPS[3:0] CPSOUT CPSEN TFTC
RST
F/F
DO
CK
DCLK_PA20
HS_PA21 PA22
Scoop
(PCMCIA GA)
VCC3
RGB[5:6:5] FNAB VS HS
DCLK
CPU(SA1110)
LCDC
HS PSPS
REM
hs pin
dclk pin
CPU
bus
CPS generation circuit
Delay amount
setting CPS inversion
Register settings
Initialize
cps
output pin
tftreset
output pin
battfault
input pin
TFT panel
controller
TFT panel
Intact
SPIIS
LTIS
GPIOIS
KIS
KIE
GPIOIELTIESPIIE INTB
SPI
interrupt
Long-hour
timer
interrupt
GPIO
interrupt
Key
interrupt
CPU bus
Interrupt
status
Interrupt source allowed Interrupt status
of entire GA
int_b
pin

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 16 –
(3) PIN CONFIGURATION
LoCoMo 128 pin diagram (SLA 50000 series (SLA5075H))
Note 1: Oscillation frequency
Nos. 2 and 3 pins (xin18m, xout 18m): 18.432MHz (ceramic oscillator)
Nos. 82 and 83 pins (xin24m, xout24m):24.567MHz (ceramic oscillator)
Nos. 98 and 99 pins (xin22m, xout22m):22.5792MHz (ceramic oscillator) Correct matching is required.
Note 2: Nos. 11-27 pins (data [15:0] data bus): Bus cycle 30MHz
Nos. 72-82 pins (adr [7:2], [25:23] address bus): Bus cycle 30MHz
1 gnd
2 I xin18m
3 O xout18m
4 vdd3
5Idclk
6Ihs
7 O cps
8 O tftreset
9 O clk9m
10 gnd
11 I/O data0
12 I/O data1
13 I/O data2
14 I/O data3
15 I/O data4
16 I/O data5
17 I/O data6
18 I/O data7
19 vdd3
20 I/O data8
21 I/O data9
22 I/O data10
23 I/O data11
24 I/O data12
25 I/O data13
26 I/O data14
27 I/O data15
28 gnd
29 I/O gpio0
30 I/O gpio1
31 I/O gpio2
32 I/O gpio3
96Oledpwm0 95Oledpwm1 94Ospics_b 93Ospiclk 92Ispidi 91Ospido 90Otimeout 89Oclk64fs 88Osda 87Oscl 86Olrclk 85Odacsck 84vdd3 83Oxout24m 82Ixin24m 81gnd 80Iadr2 79Iadr3 78Iadr4 77Iadr5 76Iadr6 75Iadr7 74Iadr23 73Iadr24 72Iadr25 71vdd3 70Iki15_b 69Iki14_b 68Iki13_b 67Iki12_b 66Iki11_b 65Iki10_b
12
8
Oadstart 12
7
Ioe_b 12
6
Iwe_b 12
5
Ics_b 12
4
gnd 12
3
Ireset_b 122Itest 121Oint_b 12
0
Ipwren 11
9
Irtc32k 11
8
Ibattfault 11
7
Ics0_b 11
6
Ics1_b 11
5
vdd3 11
4
Omcs00_b 11
3
Omcs01_b 112Omcs02_b 111Omcs03_b 11
0
Omcs10_b 10
9
Omcs11_b 10
8
Omcs12_b 10
7
Omcs13_b 10
6
gnd 10
5
Omclk 10
4
Ifrom_b 10
3
Oflpwm 102Isfrm 101Isclk 10
0
vdd3 99Oxout22m 98Ixin22m 97gnd
50
I/O gpio4
I/O gpio5 I/O gpio6 I/O gpio7 I/O gpio8 I/O gpio9 I/O gpio10 I/O gpio11 I/O gpio12 I/O gpio13 I/O gpio14 I/O gpio15
vdd3
O kstrb0_b O kstrb1_b O kstrb2_b O kstrb3_b
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 O kstrb4_b 51 O kstrb5_b 52 O kstrb6_b 53 O kstrb7_b 54 gnd 55 ki0_b 56 I ki1_b 57 I ki2_b 58 I ki3_b 59 I ki4_b 60 I ki5_b 61 I ki6_b 62 I ki7_b 63 I ki8_b 64 I ki9_b
I
(LoCoMo)
QFP15-128 pin
(14 x 14 x 1.4 mm)
3.3V D1 battery
Approx. 12,000 gates
No RAM/PLL
No scan

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 17 –
(4) PIN FUNCTION
(4)-1. PIN DESCRIPTION BY FUNCTION (128-PIN SPECIFICATION)
Function Pin name Pin No. Q'ty I/O Buffer Description Connected to
SA1110
interface
(Variable
Latency I/O)
BATTFAULT 1 IN IBC Battery voltage detection input Detection circuit
PWREN 1 IN IBC CPU status input (L: HALT, H: Operate)
RESET_B 1 IN IBH Reset input CPU (SA1110)
RTC32K 1 IN IBO RTC 32 kHz clock signal input CPU (SA1110)
CS_B 1 IN IBO Chip selection signal for GA CPU (SA1110)
WE_B 1 IN IBO Write enable signal for GA CPU (SA1110)
OE_B 1 IN IBO Output enable signal for GA CPU (SA1110)
ADR[25:23] 3 IN IBO Address bus CPU (SA1110)
ADR[7:2] 6 IN IBO Address bus CPU (SA1110)
DATA[15:0] 16 IN/OUT BA2T Data bus CPU (SA1110)
Subtotal 32
Interrupt control INT_B 1 OUT OB1T INT (including interrupt key) output signal CPU
(SA1110 interrupt)
BOOT drive
switching
circuit and
decode
CS[1:0]_B 2 IN IBO CS signal for FROM/MROM signal CPU (SA1110)
MCS0[3:0]_B 4 OUT OB1T MCS signal 0 for FROM/MROM decode signal FROM/MROM
MCS1[3:0]_B 4 OUT OB1T MCS signal 1 for FROM/MROM decode signal FROM/MROM
FROM_B 1 IN IBOP2 FROM_Board detection pin FROM/MROM
Subtotal 11
Key port circuit KSTRB[7:0] 8 OUT TB1HT Key strobe signal KEY_BOARD
KI_B[15:0] 16 IN IBH Key input signal
(external pull-up resistance is required) KEY_BOARD
Subtotal 24
Serial output
circuit for
general-purpose
8-bit 2ch DAC
control
SCL 1 OUT OD1T Serial clock signal DAC
SDA 1 IN/OUT BG1 Serial data DAC
Subtotal 2
TFT_C reset TFTRESET 1 OUT OB1T TFT_C reset signal
TFT PS control CPS 1 OUT OB1T TFT power save CPS output signal TFT panel
AD_START
output circuit for
tablet control
ADSTART 1 OUT IBO Tablet incorporation START signal Toshiba TC35143AF
HS 1 IN IBO LCD horizontal synchronous signal CPU
(SA1110-I, CDC)
DCLK 1 IN IBO LCD data transfer clock signal CPU
(SA1110-I, CDC)
Subtotal 3
PWM output
port TIMEOUT 1 OUT OB2T Battery charger protection timer Charger circuit
LEDPWM0 1 OUT OB2T For charger indicator Charger circuit
LEDPWM1 1 OUT OB2T For communication error blinking Charger circuit
FLPWM 1 OUT OB1T F/L Duty light control signal (0-100%) output F/L inverter circuit
Subtotal 4
Audio
MCLK/SCK32
output port
XIN22M 1 IN LIN 44.1 KHz system base clock input
(22.5792 MHz) Oscillation circuit 1 (OSC4C)
XOUT22M 1 OUT LOT 44.1 KHz system base clock output
(22.5792 MHz) Oscillation circuit 1 (OSC4C)
XIN24M 1 IN LIN 48 KHz system base clock input (MHz) Oscillation circuit 2
(OSC4C)
XOUT24M 1 OUT LOT 48 KHz system base clock output
(22.5792 MHz) Oscillation circuit 2 (OSC4C)
CLK64FS 1 OUT OB2T Audio 64 fs output (SCLK x2) CPU (GPI0)
MCLK 1 OUT OB2T Audio MCLK clock output Audio DAC
Subtotal 6

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 18 –
<Description buffers>
PCM audio
TIAudo
output-SDF
conversion
circuit
SFRM 1 IN IBO Audio serial data start signal CPU (SA1110)
LRCLK 1 OUT OB1T Audio serial data right and left identification
signal Audio stereo DAC
SCLK 1 IN IBO Audio serial data clock signal CPU (SA1110)
DACSCK 1 OUT OB1T Audio serial clock-SCLK inversion Audio stereo DAC
Subtotal 4
SD_CARD SPI
control circuit SPICS_B 1 OUT TB1T SD_CARD CS signal SD_CARD connector
SPICLK 1 OUT TB2T SD_CARD clock signal SD_CARD connector
SPIDI 1 IN IBO SD_CARD data input signal SD_CARD connector
SPIDO 1 OUT TB2T SD_CARD data output signal SD_CARD connector
Subtotal 4
SD_CARD/
TC35143 AF
clock output
XIN18M 1 IN LIN SD_CARD/Toshiba TC35143AF base clock
signal input (18.432 MHz) Oscillation circuit (OSC4C)
XOUT18M 1 IN LOT SD_CARD/Toshiba TC35143AF base clock
signal input Oscillation circuit (OSC4C)
CLK9M 1 OUT OB2T Clock signal output (9.216 MHz) Toshiba TC35143AF,
CPU
Subtotal 3
GPIO port GPIO[15,12:3, 0] 16 I/O BA1T General-purpose I/O port (CMOS input +
Feed-through current prevention type)
GPIO[14:13, 2:1] 4 I/O BH1T General-purpose I/O port (Schmidt input)
TEST circuit TEST 1 IN ITST1 Test mode selection signal input –
Power supply
(3.3 V) VDD3 7
GND 8
TOTAL_PIN 128 QFP15 (14 x 14 x 1.4mm)
Function Pin name Pin No. Q'ty I/O Buffer Description Connected to
IBC : Input buffer
IBH : Schmidt trigger input buffer
IBO : OR type gated input buffer
IBOP2 : OR type gated input buffer + 100 K pull-up
OB1T : Output buffer (IOL=2mA, with test function)
OB2T : Output buffer IOL=6mA, with test function)
TB1HT : 3-state output buffer with buss hold circuit (IOL=2mA, with test function)
OD1T : Open drain output buffer (IOL=2mA, with test function)
TB1T : Try state output buffer (IOL=2mA, with test function)
TB2T : Try state output buffer (IOL=6mA, with test function)
BG1 : 5-V withstand voltage output buffer (IOL=2mA, with test function)
BH1T : Schmidt trigger I/O buffer (IOL=2mA, with test function)
BA1T : AND type gated I/O buffer (IOL=2mA, with test function)
BA2T : AND type gated I/O buffer (IOL=6mA, with test function)
LIN : TRANSPARENT input buffer (for clock oscillation)
LOT : TRANSPARENT output buffer (for clock oscillation)
ITST1 : Test mode input buffer (with pull-down)

PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 19 –
2-6. TIMING CONTROL IC (LZ9GG314)
(1) FEATURES
The LZ9GG314 is a timing control IC for TFT-LCD modules.
Applicable model: Modules using QVGA pixel digital driver
(1) Generates, by inputting the clock signal, horizontal synchronous
signal, and vertical synchronous signal, the following signals which
synchronize with them:
1) Source driver drive signals: CLK, SPL, SPR, LP, PS
2) Gate driver drive signals: CLS, SPS
3) Signal for generating common electrode drive signal: REV
4) Base signal generation signal: REVV0
(2) Capable of inverting the display screen upside down and horizon-
tally.
(2) PIN CONFIGURATION DIAGRAM
(3) SIGNAL DESCRIPTION
Pin
No. Signal name Description I/O
1 DCLK Data clock signal input pin I
2 TESTI Test input pin. Usually set to H I
3 R0 Red data signal input pin I
4 R1 Red data signal input pin I
5 R2 Red data signal input pin I
6 R3 Red data signal input pin I
7 R4 Red data signal input pin I
8 R5 Red data signal input pin (MSB) –
9 GND Grounding power supply pin –
10 VDD Power supply input pin I
11 G0 Green data signal input pin I
12 G1 Green data signal input pin I
13 G2 Green data signal input pin I
14 G3 Green data signal input pin I
15 G4 Green data signal input pin I
16 G5 Green data signal input pin (MSB) I
17 TESTI Test input pin. Usually set to H I
18 B0 Blue data signal input pin (LSB) I
19 B1 Blue data signal input pin I
20 B2 Blue data signal input pin I
21 B3 Blue data signal input pin I
54 37
118
55 36
72 19
OR4
OR3
OR2
OR1
OR0
GND
CLS
SPS
VDD
GND
UBL
VRVE
N.C.
N.C.
TV
TESTI
HS
VS
LP
SPL
LBR
SPR
PS
REVV0
REV
RESET
GND
VDD
ENAB
HRVE
B2
B1
DCLK
TESTI
B5
B4
B3
G5
VDD
G0 G1
GND
G2 G3 G4
0G5
TESTI
R0 R1 R2 R3 R4 R5
OB1
TESTI
B0
OR5
GND
OG0 OG1 OG2 OG3 OG4
GND
CLK
L Z 9 G G 3 1
OB2 OB3 OB4 OB5
GND
VDD
OB0
22 B4 Blue data signal input pin I
23 B5 Blue data signal input pin (MSB) I
24 TESTI Test input pin. Usually set to H I
25 HRVE Right and left inversion setting pin. Usually set
to H. Set to L for inversion. I
26 ENAB Horizontal display position signal input pin I
27 VDD Power supply input pin –
28 GND Grounding power supply pin –
29 RESET Initialization reset signal input pin. Give the sig-
nal which changes L level to H level and holds it
when power is turned on
I
30 REV Common electrode generation signal output pin O
31 REVV0 Base voltage generation signal output pin O
32 PS Source driver control signal output pin O
33 SPR Source driver start signal output pin. (High
impedance other than when it is used for right
and left inversion and ordinary display.)
O
34 LBR Right and left inversion display control signal
output pin O
HRVE When set to H: H level output
When set to L: L level output
35 SPL Source driver start signal output pin
(High impedance other than when it is used for
right and left inversion and ordinary display.)
O
36 LP Source driver data transfer signal output pin O
37 CLK Source driver clock signal output pin O
38 GND Grounding power supply pin –
39 OB5 Source driver blue data signal output pin (MSB) O
40 OB4 Source driver blue data signal output pin O
41 OB3 Source driver blue data signal output pin O
42 OB2 Source driver blue data signal output pin O
43 OB1 Source driver blue data signal output pin O
44 OB0 Source driver blue data signal output pin (LSB) O
45 VDD Power supply input pin –
46 GND Grounding power supply pin –
47 OG5 Source driver green signal output pin (MSB) O
48 OG4 Source driver green signal output pin O
49 OG3 Source driver green signal output pin O
50 OG2 Source driver green signal output pin O
51 OG1 Source driver green signal output pin O
52 OG0 Source driver green signal output pin (LSB) O
53 GND Grounding power supply pin –
54 OR5 Source driver red data signal output pin (MSB) O
55 OR4 Source driver red data signal output pin O
56 OR3 Source driver red data signal output pin O
57 OR2 Source driver red data signal output pin O
58 OR1 Source driver red data signal output pin O
59 OR0 Source driver red data signal output pin (LSB) O
60 GND Grounding power supply pin –
61 CLS Gate driver clock signal output pin O
62 SPS Gate driver start signal output pin O
63 VDD Power supply input pin –
Pin
No. Signal name Description I/O