Sharp QD-101MM User manual

SHARP CORPORATION
SZ545QD-101MM
SERVICEMANUAL
CONTENTS
1. INTRODUCTION .........................................................................1
2. SPECIFICATIONS.......................................................................2
3. ADJUSTMENT OF PWB.............................................................5
4. CIRCUIT DESCRIPTION.............................................................8
5. TROUBLESHOOTING CHART.................................................21
6. CIRCUIT DIAGRAM & PWB.....................................................38
7. REPLACEMENT PARTS LIST.................................................54
8. ASSEMBLY DRAWINGS .........................................................60
9. INFORMATION..........................................................................64
QD-101MM
• In the interests of user-safety the set should be restored to it's
original condition and only parts identical to those specified be
used.
TFT DISPLAY UNIT
MODEL QD-101MM

1
1. INTRODUCTION
The QD-101MM is a liquid crystal display monitor.
Itemploysahighcontrast,highresponse,10.4-inchTFTliquidcrystaldisplaypanel,whichcan
generateamaximumof16,000,000differentcolors. Itoffersacomputergraphicscreenwhich
responds in real time.
Moreover, the built-in composite video circuit and audio circuit can receive video signals of
VCR, laser disc.
Theircontrols andimagescan beadjustedwiththemain-body's buttonsreferringto themenu
screen.
This monitor also has a speaker to monitor audio signal.
In addition, an external control terminal has been provided to facilitate control of the display
unit's functions.
The power source is an external AC adaptor that provides 12V DC to display monitor unit.
This unit can be used with the following models and signals.
1.Personal computers
1) IBM, PC/XT, PC/AT, PS/2, PS/1, PS/55, Think Pad 700
2) Apple, MACII, MAC+/SE, MACIIcx, MACIIci, MACIIsi, MAC LC,
Power Book 160/180, Quadra
3) AT&T, PC6300WGS
4) SHARP, AX286/386
2.Video adaptors and signals
1) IBM, MDA(720X350)
2) IBM, CGA(640X200)
3) IBM, EGA(640X350)
4) IBM, MCGA(640X400, 640X480)
5) IBM, VGA(640X350, 640X400, 640X480, 720X400)
6) Apple, MACII Video Card (640X480)
7) Apple, MAC LC (640X480, 512X384)
8) Hercules, Graphic Card/Plus/Incolor Card (720X348, 720X350)
9) Composite video signals (PAL/NTSC/SECAM)

2
2. SPECIFICATIONS
1.SPECIFICATIONS OF MAIN BODY
1.Display unit :10.4-inch TFT color LCD
(Amolphous silicone active matrix type : a Si TFT)
2.Display color :Approx.16,000,000 colors
3.Display area :211.2(W)X158.4(H)mm
4.Number of pixels :640X(RGB)X480 pixels (pixel = R+G+B dots)
5.Input video signal :TTL level R,G,B,r,g,b, Hsync, Vsync
TTL level R,G,B,I,Hsync, Vsync
TTL level Video, I, Hsync, Vsync
Analog IBM PS/2 type VGA signal
Analog Apple Macintosh II video card signal
Composite / S video signal (NTSC/PAL/SECAM)
6. Input connector :15-pin computer signal input connector (1)
Composite video input connector (1)
S-terminal video signal input connector(1)
Audio input connector (1)
12V DC input socket (1)
7. Switches and others :Power switch
MENU button (1), SELECT button (1),
UP button(1), DOWN button (1), RESET button (1)
8. Adjustment :Color adjustment, Brightness adjustment, Tint adjustment
Contrast adjustment, Audio level adjustment
Image horizontal/vertical position adjustment
Phase adjustment, Frequency adjustment
9. Functions Software reset
Freeze function
Input video signal auto-discrimination function
Menu screen control
Built-in speaker(1W)X1
10. Outside dimensions :280(W)X208(H)X47(D) [mm]
(11.0(W)X8.2(H)X1.9(D) [inches])
11. Weight :Approx. 1.3kg (main body alone)
(Approx.2.86lbs(main body alone))
12. Backlight :Fluorescent lamp
(cold-cathode Fluorescent X1)

3
2.SPECIFICATIONS OF INTERFACE
2.1.Computer signal input section
Signal layout
Connector :Mini D-Sub 15-pin connector
JST EKHEY-15S-IF3P14-143
(applicable plug housing : JST KEC-15P)
Test 1 :When connecting to Apple Macintosh computer, this terminal must be
grounded.
Test 2 :This terminal must be grounded when inputting analog-type computer
signals.
Leave this terminal open(N.C.) when inputting digital computer signals.
2.2.Composite video signal input section
Connector :Pin jack (EIAJ RC-6703A)
2.3.Audio signal input section
Connector :Pin jack (EIAJ RC-6703A)
2.4.Power input section
Input pin :HEC0470-01-640 [Hoshiden Co., Ltd.] or equivalent
Center pin +
AC adaptor :Accessory AC adaptor DADP-2004PAZZ
Input voltage :DC12V (when main body is loaded)
2.5.S-terminal video signal input section
Signal layout : 1.GND
2.GND
3.Y signal
4.C signal
Pin No. Analog Signal Digital Signal
1 Analog Red N.C.
2 Analog Green Digital Green
3 Analog Blue Digital Blue
4 N.C. Digital Secondary Red(r)
5 N.C. Digital Red
6 Analog Red Return Digital Red Return(GND)
7 Analog Green Return Digital Green Return(GND)
8 Analog Blue Return Digital Blue Return(GND)
9 Test 1(Macintosh) N.C.
10 Test 2(GND) Test 2(N.C.)
11 GND GND
12 N.C. Digital Secondary Green(g,I)
13 Hsync/Csync Hsync
14 Vsync Vsync
15 N.C. Digital Secondary Blue(b.Video)
12345
678910
1112131415
1
2
3
4

4
3.SPECIFICATIONS OF ENVIRONMENT
Basically, these environment specifications apply to the main body and its accessories.
Item Specification Remark
Power
Type Single-phase 2-wire type, 1 ground line
Special AC adaptor accessory is
used.
Frequency 50 / 60 Hz
Input voltage AC 100~240V
Output voltage DC 11.5 ~ 13.8V
Operation Operating temperature 0 ~ 35 °C
Without dew condensation.
Absolute humidity shall be less
than 35 °C / 80 % RH.
Operating humidity 20 ~ 80 %RH
Storage Storage temperature -20 ~ 60 °C
Storage humidity 20 ~ 80 %RH

5
3. ADJUSTMENT OF PWB
The QD-101MM has a Main printed-wiring board (PWB) that needs to be adjusted.
The following paragraphs describe how to adjust the Main PWB. Correct adjustments are
essentialfortheunittooperateproperly. Afterrepairormaintenance,itisnecessarytoreadjust
them. Before adjusting the control block, be sure to verify that the power supply block is
adjusted, and then adjust the control block.
1. ADJUSTMENT OF POWER SUPPLY BLOCK
There are two power voltage adjusting points: VR1 for VCPU, VR2 for VLCD.
1) Connect the AC adaptor connector plug to J1.
Verify that the output of AC adaptor approximates 12V.
2) Before turning on the power switch, check the conductive pattern on the rear of the
PWB for defects or foreign material that may short the conductive paths.
3) Turn on the power switch SW1 to verify that the LED lights.
4) VCPU adjustment
Connect the + lead of DC voltmeter to TP203, and the - lead to TP206.
While turning VR1 with a flat-tipped screwdriver, observe the voltmeter.
Adjust the voltage to 5.15±0.05V.
5) VCC voltage check
Connect the + lead of the DC voltmeter to TP202. Verify the voltage of 4.90 to 5.15V.
6) VLCD adjustment
Connect the + lead of the DC voltmeter to TP200.
While turning VR2 with a flat-tipped screwdriver, observe the voltmeter.
Adjust the voltage to 5.05±0.05V.
7) +10V voltage check
Connect the + lead of the DC voltmeter to TP204. Verify the voltage of 10±0.5V.
2.ADJUSTMENT OF CONTROL BLOCK
2.1.Offset adjustment of computer signal input amplifier
1) Turn off the power, and connect TP10 and TP303 to the DC voltmeter.
(Connect the earth terminal of the probe to TP10.)
2) Input the signal of Fig. 1-B to J2.
3)Turnonthepower. ObservingtheDCvoltmeter,adjusttheTP303levelto1.15±0.05V
by turning VR303 with the flat-tipped screwdriver.
2.2.Gain adjustment of computer signal input amplifier
1) Turn off the power, and connect TP303 and TP300 to an oscilloscope.
(Connect the earth terminal of the probe to TP10.)
2) Input the signal of Fig. 1-C to J2.
3) Turn on the power. Observing the oscilloscope, adjust the TP303 level to be equal
to TP300 level by turning VR300 with the flat-tipped screwdriver.
(Output voltage is approx.3.8V at TP300.)
4) Turn off the power, and reconnect the probe from TP303 to TP304.
5) Turn on the power. Observing the oscilloscope, adjust the TP304 level to be equal
to TP300 level by turning VR301 with the flat-tipped screwdriver.
6) Turn off the power, and reconnect the probe from T304 to TP305.

6
7) Turn on the power. Observing the oscilloscope, adjust the TP305 level to be equal
to TP300 level by turning VR302 with the flat-tipped screwdriver.
2.3.VCO adjustment
1) Connect the + lead of the DC voltmeter to TP207, and the - lead to TP10.
2) Input the video timing of Fig. 1-A to J2.
3) After turning on the power, leave it as it is for approx. 3 minutes.
Then turn L200 with ceramic driver to adjust the voltage of TP207 to 2.5±0.2V. (*1)
4) Input the video timing of Fig. 1-B or C to J2 .
5) Then turn L201 with ceramic driver to adjust the voltage of TP207 to 4.1±0.05V. (*2)
(*1) Since the voltage of TP207 varies depending on the material of the driver used,
keep the driver away from the core when checking the voltage.
(*2) It is factory-adjusted at the timing of PC9801 640X400 at shipment.
2.4.Audio speaker level adjustment
1) Input the 1KHz, 500mV(RMS) sine wave from an oscillator to the audio signal input
terminalCN502.(The audiosignal levelshould beadjustedwhenpowerswitchofQD-
101MM is on.)
2) Set the volume level to maximum and the audio mute switch to off.
3)ConnectaneffectivevaluetypeACvoltmetertoTP502andadjustthevoltageofTP504
to 2.85V(RMS) by turning VR501 with the flat-tipped screw driver.
Video
Video
Hsync
Vsync
95 64 113 640dot
1H=912dot=63.696047µs
25 3 34 200H
(1/H=15.699561KHz)
(1/V=59.92Hz)
1V=262H=16.688364ms
Fig. 1-A IBM CGA 200-line 40-character

7
Video
Video
Hsync
Vsync
1H=800dot=31.777557µs
(1/H=31.468881KHz)
(1/V=59.94Hz)
1V=525H=16.683217ms
96
2
0V
0V
Fig. 1-B IBM VGA 480-line Black-solid
Video
Video
Hsync
Vsync
16 96 48 640dot
11 2 32 480H
1H=800dot=31.777557µs
1V=525H=16.683217ms
(1/H=31.468881kHz)
(1/V=59.94Hz)
0V
0.7V
0V
0.7V
Fig. 1-C IBM VGA 480-line

8
4. CIRCUIT DESCRIPTION
1. GENERAL
Circuit will be described in reference to the QD-101MM block diagram in Fig. 2.
Composite video signal which enters via pin jack connector is converted into the digital RGB
inthe compositevideoinputcircuitby thecontrol signalfrom theI2C buscontroller. Thesignal
then enters the signal selector circuit.
Computeranalogsignalentersviathe15-pinconnectorandisprocessedthroughthecomputer
analoginput circuitand theA/D conversioncircuit.Thesignalisthenconvertedintothedigital
RGB signal and enters the signal selector circuit.
Digitalvideosignal from IBMPC EGA orCGA enters viathe 15-pin connectoris input intothe
signal selector circuit.
The signal selected in the signal selector circuit is written into the field memory. The writing
operation into the field memory is controlled by signals which are generated in the IC100 by
HSYNC. VSYNC. Since the LCD control is asynchronous with the computer signal, FRCK.
FRRS is generated in the IC100, and is read out at their timings.
Theaudiocontrolcircuitcontrolstheaudiosignalinputfromtheaudioinputterminal,according
tothecontrolsignalfromIC100.IC400(MPU)controlsIC100,IC107(I2Cbuscontroller) bythe
keyoperation fromSW PWB. Sincecontroldatafromthe keyis storedintoEEPROM,theset
data is memorized even if the power is turned off.
2. COMPUTER SIGNAL INPUT CIRCUIT
Inadditiontocompositevideosignal,QD-101MMcanreceivethecomputeranalogRGBsignal
and the computer digital RGB signals of MDA, CGA, EGA. These signals enter each input
circuitviathe 15-pinconnector(J2), pinjack (CN600), andS-terminal(CN601). After they are
converted into the digital signals, they are input to the signal selector or directly to the signal
selector circuit.
Refer to MAIN CIRCUIT No.3.
2.1.Computer digital signal input circuit
Thecomputer digitalsignalisinputto Pins2,3,4,5, 12and15ofJ2, andisdirectlysentto the
signal selector.
EGA outputs the video signal at the 6-bit TTL level. (R, G, B, r, g, b)
CGA outputs the video signal at the 4-bit TTL level. (R, G, B ,I)
MDA outputs the video signal at the 2-bit TTL level. (Mono, Video, I)
As basic, the pins of J2 output the following signals.
Table 1
x:Don`t care or N.C.
Signal Connector J2's Pin Number
12 15 4 2 5 3 14 13 11
EGA g b r G R B Vsync Hsync GND
CGA I x x G R B Vsync Hsync GND
MDA I MONO x x x x Vsync Hsync GND

9
SW CIRCUIT
E PROM
IC107
I C BUS CONTROLLER
A/D CONVERSION CIRCUIT
COMPUTER ANALOG INPUT CIRCUIT
PLL
CLK
SIGNAL
SELECTOR
FIELD MEMORY
COMPOSITE VIDEO INPUT CIRCUIT
AUDIO COTROL CIRCUIT
IC400
MPU
GATE ARRAY IC100
DATA REGISTER
COLOR CONTROLLER MASK
CONTROLLER MENU
CONTROLLER
LCD CONTROLLER
FIELD MEMORY READ CONTROLLER
VRAM
TFT COLOR LCD UNIT
DC INPUT
POWER SUPPLY
+10V VLCD AVCC DVCC VCPU
SP
AUDIO INPUT
SIGNAL
COMPOSITE
VIDEO SIGNAL
COMPUTER DIGITAL
RGB SIGNAL
COMPUTER ANALOG
RGB SIGNAL
Fig. 2 QD-101MM Block Diagram
FIELD MEMORY WRITE CONTROLLER
PDB
VCOIN
2
2
IC600,601
S-VIDEO
SIGNAL
J2
J2
CN600
CN601
CN502
SP500
IC315~317
IC300~302
IC202,203
IC308~313
IC103~105
IC108,111
J1
IC413,414
OSC1,2
INVERTER PWB
AC HV

10
2.2.Computer analog signal input circuit
IBM computer and APPLE computer output the following analog signals at the load of 75Ω.
The signals are converted into 8-bit digital signals by the A/D converter(IC315~317).
The computer analog signals are given to Pin 21 of the A/D converter, are divided by 256
between the voltages given to Pin 18(VRT) and Pin 24(VRB), and are digitally converted.
The following table shows the reference voltage which is given to the A/D converter.
2.3.Threshold level generation circuit
Inordertoconvert thecomputerandcompositeanalogsignalinto digital,itis necessarytoset
the threshold level on the A/D converter. As shown in Fig. 3, VRT and VRB voltages are set
on the basis of the reference power of ZD1. VRT can be varied by key operation.
Astheadjusting method fromthe main body,the MENU buttonand SELECT buttonare used
to display the contrast adjustment in the screen and to allow the set value to be changed with
UP and DOWN selector buttons.
Fig. 3 Threshold Level Generation Circuit
Table 2
Computer Analog Signal
R G B
IBM 0.7Vp-p 0.7Vp-p 0.7Vp-p
APPLE 0.7Vp-p 1.0Vp-p (Synchronization signal
overlapped) 0.7Vp-p
Table 3
VRT VRB
Threshold
Level 3.8V(2.8~4.8V) Adjustment are possible 1.0V

11
3.VIDEO INPUT CIRCUIT
Fig. 4 shows the block diagram. Circuit diagram is shown in VIDEO CIRCUIT.
This unit automatically switches the circuit corresponding to the composite video signals of
NTSC,PALandSECAM.Thecomposite videosignalandS-Videosignalinputtothedecoder
are first converted into the 8-bit digital Y,UV signal, and is output as the 8-bit digital RGB from
the RGB converter(IC601).
Horizontal sync signal CSHSYNC, vertical sync signal CSVSYNC, ODEV signal and system
clock LLC2 are simultaneously output from the decoder(IC600), and are used in the process
circuit in the rear step.
Controls of brightness, color and tint, and the initial setting of decoder and RGB converter are
sent from MPU by the I2C bus.
Fig. 4 Composite Video / S-Video Input Circuit Block Diagram
4.AUDIO INPUT CIRCUIT
Fig. 5 shows the block diagram of the audio input circuit. Circuit diagram is shown in AUDIO
CIRCUIT.
The audio signal input to the audio input terminal is inputted to the audio level controller, and
is controlled to the level which corresponds to the volume signal output from MPU.
Theoutputentersthemuteswitchcircuitinthenextstep,andtheaudiosignalisturnedonand
off corresponding to the SMUTE signal which is output from MPU.
CSHSYNC
CSVSYNC
LLC2
ODEV
RGB 8bit
Y,UV/RGB
CONVERTER
Y,UV
8bit
CONTROL
I C BUS
COMPOSITE VIDEO
SDA,SCL
DECODER
CN600 IC600
SAA7110
IC601
SAA7192
21 45~50
53~62
29
31
42
32
63
64
65
26
38,41
30
40
16,17,
20~25
30~34,37~39
40~47
48~50,53~57
5,6
CN601
17,19
S-VIDEO
2

12
Fig. 5 Audio Input Circuit Block Diagram
5. PLL CIRCUIT
Thedotclock(VCOIN)isgeneratedbythePLLcircuitshowninFig.6.Thedotclockisnecessary
to sample the video signal from the computer and change it into the suitable dot data.
Hsync signal from computer enters into IC100. This signal is compared frequency and phase
withthe feed-backsignal, whichis generatedfrom VCOINby thephase comparatorin IC100.
If any error of phase or frequency occurs between Hsync and VCOIN, LOW or HIGH level is
output at PBD of IC100, and when both frequency and phase agree with each other, high
impedance is output.
TheoutputsignalfromthePDBterminalisconvertedintoaDCvoltagebyaloopfilterandthen
controls the VCO.
To select the high band or low band, either VCO is selected according to the signals from No.
120 pin and No. 119 pin of IC100.
SMUTE
VOLUME
PHONE JACK STEREO INPUT
AUDIO
LEVEL
CONTOROLLER
MUTE SW
AMPLIFIER
SPEAKER
SPEAKER
AMPLIFIER
ADJUST
CN502
IC500
TA8184F
SP500
IC503
TDA1905
VR501
1
2
2
7
24
5
4

13
Fig.6 PLL Circuit
6. MEMORY CIRCUIT
BLOCK DIAGRAM is shown in Fig.2.
6.1.Field memory writing
When data sent from the signal selector is written into the field memory(IC103~105), FWCK
(clock slightly later than CLK) generated from the memory controller in IC100 is used.
6.2.Field memory reading
The clock (FRCK) and control signals which are generated in the field memory reading signal
generating circuit in IC100 are used to read data from the field memory.
Readingisasynchronouswithwriting. Intheordinarymode,datawrittenintothefieldmemory
are color-compensated and are sent to LCD.
In the enlargement mode, the enlargement control signal is sent to the field memory from the
fieldmemorywriting/readingsignalgeneratingcircuitinIC100 tomaketheenlargementdisplay
possible.
6.3.Menu, message display memory
The menu and message display is stored in the ROM area of IC400(MPU).
Whenthemenubuttonisfirstpressed,MPUwillwritedataandaddressintoVRAM(IC108,111)
via IC100. Moreover, VRAM data is read via IC100.
The data is sent to LCD at the timing of LCD.
Fig. 8 Memory Circuit Block Diagram
VRAM
IC100
ROMMPU
LCD
FIELD MEMORY
menu and
message data
display data
IC108, 111
IC103~105

14
7. VARIOUS FUNCTIONS OF IC400(H8/3256 M.P.U)
IC400 is a microcomputer which is provided with a set of 16-bit free running timer and 2
channels of SCI in addition to 48K-byte PROM/2K-byte RAM.
7.1.Key data and various functions
The keys (DOWN, UP, SELECT, MENU, RESET) provided on the main body of QD-101MM
switches and selects the adjustment mode displayed in the LCD screen as well as gives the
direct commands to IC400.
1) DOWN
This key decreases the adjustment items selected by the select key, step by step.
2) UP
Being opposite to DOWN, the key increases the adjustment item, step by step.
3) SELECT
Thiskeyis used toselect the adjustmentmode in themenu screen whichis displayed
by the MENU key.
Every push of this key can change the adjustment item, step by step.
4) MENU
This key is used to switch the menu screen.
5) RESET
This key is used to set the initial values of the computer. When this key is pressed,
the adjustment items are all returned to the initial statuses.
7.2.EEPROM control function
The EEPROM(IC413, 414) area is provided to write the timing set values of each computer
whenitisconnectedtoQD-101MM. ThetimingsetvaluesarewrittenintoEEPROMunderthe
following four conditions.
1. All resetting
2. Resetting
3. Power turn-off
4. The connected computer is changed.
Here, writing into EEPROM is executed only when the set value is changed.
7.3.Reset circuit
The circuit diagram is shown in MAIN CURCUIT No.4.
IC407(TL7705CPS-B) detects the power voltage, VCPU, of IC400 and its surrounding circuit,
and generates the RESET signal. If VCPU drops below the detection voltage (TYP4.5V) when
the power is turned off, IC407 shifts the level of the RESET signal to “Low”.
If VCPU rises to exceed the total voltage of the detection voltage VS1 and hysteresis width
VHYS1(TYP15mV), IC407 starts charging the timing capacitor(Ct) with a constant current.
After (TP0=1.3XCtX10[S]), IC407 shifts the RESET signal to “High” level. (See Fig. 8.)
IC411(S-8054ALB) detects the power voltage VCC to generate the power OFF signal. If VCC
drops below the detection voltage VS2 (TYP4. 15V) when the power is turned off, IC411 shifts
the power OFF detection level to “Low”.
If VCC rises beyond the total voltage of the detection voltage VS2 and hysteresis voltage VHYS2
(TYP200mV) when the power is turned on, IC411 shifts the power OFF signal to “High” level.
(See Fig. 9.)

15
RESET
signal
VS1
(4.5V)
VCPU
VHYS1
(15mV)
TPO TPO TPO
POWER OFF
DETECTION
signal
VS2
(4.15V)
VCC
VHYS2
(200mV)
Fig.8
Fig.9
When the power is turned on, VLCD, VCC and VCPU rise. If VCPU exceeds VS1+VHYS1, the RESET
signal is shifted to “High” level at the timing shown in Fig. 10. The reset operation of IC400 is
canceled and executes the program.
Whenthepoweristurnedoff,thepowerOFFdetectionsignalisshiftedto“Low”whenVCC and
VLCD drops sharply below VS2.
Ontheotherhand,VcpuisbackedupbyC425(220mF)sothatitcanmaintain4.5Vforthetime
of TW after the trailing edge of the power OFF detection signal. See Fig. 11. (TW is the time
for IC400 to retreat the data to EEPROM.) If VCPU drops below VS1, the RESET signal level is
shifted to “Low”, and IC400 starts resetting.

16
RESET
VS2(VCC)
VS1(VCPU)
TPO
VCPU
VCC
POWER OFF
DETECTION
signal
RESET
VS2
VS1(4.5V)
POWER OFF
DETECTION
signal
TW
5.0V
4.0V
Fig.10
Fig.11
VCPU
VCC

17
8. LCD CONTROL CIRCUIT
LCD control signal is slower than the video signal of the computer. While the video signal is
serialdata,theLCDdisplaydataisgivenas4-bitparalleldataforeachRGB. Inordertodisplay
the bit signal of the computer in LCD, it is necessary to store the data of one screen in the
memoryandreadouttheimagedataofonescreenatthedrivetimingofLCD. Tocontrolthem,
thefieldmemoryiscontrolledbythememorycontrollerinIC100asshownintheblockdiagram
in Fig. 2.
9. LCD UNIT
9.1.Interface signals
The shield case is connected to GND in LCD module.
(*1) The line mode(480 or 400 or 350) can be selected by the polarity of Hsync and Vsync.
(*2) Don't use "High".
Table 4 Pin assignment of LCD unit
Pin Code Function Remark
1 GND
2 CK Sampling clock signal of data
3 Hsymc Horizontally synchronous signal (*1)
4 Vsync Vertically synchronous signal (*1)
5 GND
6 R0 Red data signal(LSB)
7 R1 Red data signal
8 R2 Red data signal
9 R3 Red data signal
10 R4 Red data signal
11 R5 Red data signal(MSB)
12 GND
13 G0 Green data signal(LSB)
14 G1 Green data signal
15 G2 Green data signal
16 G3 Green data signal
17 G4 Green data signal
18 G5 Green data signal(MSB)
19 GND
20 B0 Blue fata signal(LSB)
21 B1 Blue fata signal
22 B2 Blue fata signal
23 B3 Blue fata signal
24 B4 Blue fata signal
25 B5 Blue fata signal(MSB)
26 GND
27 ENAB Data enable signal(Horizontal display position signal) (*2)
28 Vcc +5V power suppry
29 Vcc +5V power suppry
30 TST Open
31 TST Open
CN1 Pin assignment 30
24
222018161412108642 29272523211917151311975
31 31
2826
Mode 480line 400line 350line
Hsync Negative Negative Positive
Vsync Negative Positive Negative

18
9.2.Sequence circuit of LCD panel
In QD-101MM, it is necessary to conform the power ON/OFF sequence of the LCD panel as
shown Fig.12.
Fig. 13 shows the panel sequence generation circuit.
ThegatesignalwhichhasthesametimingastheinputsignalinFig.12isoutputbytheRESET
IC of IC4 and IC5.
Fig. 13 Panel Sequence Generation Circuit
9.3.Handling the LCD panel
1. The LCD unit is assembled to very high density, do not attempt to disassemble it.
2. The polarizing plate is very easy to scratch, take extra care when handling it.
3. When cleaning the surface of the LCD panel, use absorbent cotton or soft cloth and
carefully wipe the surface.
4.TheLCDpanelwillbecomediscoloredorstainedifanymoistureremainsonthesurface
for a long period of time.
5. The LCD panel is made of glass. If it is hit by any hard object or is dropped, it may
crack.Handle it very carefully.
6.CMOSLSIwhichisusedintheLCDunitisverysensitivetostaticelectricity.Toprevent
damageto the LCDunit from staticelectricity it isnecessary forallservice technicians
touse aconductivemat andwrist strap toground themselveswhenservicing theunit.
10.POWER CIRCUIT
The AC adaptor which is connected to QD-101MM supplies stable power to the unit, and
generates 5V power (VCC, VCPU, VLCD), VPP power, +10V power and the inverter circuit board
power(12V).
T1 T2
VLCD
Signal 0 T1
0 T2
Fig. 12 Power ON/OFF sequence

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10.1. +5V power (VCC, VCPU, VLCD)
IC1 in Fig. 14 is a controller for a fixed frequency pulse width modulation(PWM) switching
regulator and has two constant voltage controllers. One controller is used to generate a 5V
power supply(VCPU,VCC) from the input power supply VIN(12VDC). The other one is for VLCD.
IC1 has a saw-tooth wave oscillator built in whose oscillating frequency is determined by
capacitor C30 connected to pin 1 and resister R29 connected to pin2. In this circuit
configuration,asaw-toothwaveofapprox.75KHzisobservedatpin1ofIC1.Basicallythissaw-
tooth wave is compared with a control signal observed at pin5 of IC1. Only while the voltage
ofthesaw-tooth waveis lower thanthe controlsignalvoltage, theperiod betweenpin7 ofIC1
is "L" becomes longer. As a result the period between external transistor Q11 and Q10 is
conductive becomes longer. The output voltage is fed back to pin 3 of IC1. An error amplifier
inIC1makesacomparisonbetweenthehalfofthereferencevoltageandthefeed-backsignal
to pin 3 and generates a control signal(pin5 of IC1). As explained above the output voltage is
stabilizedbythepulsewidthfrompin7,whichisgeneratedbycomparingthecontrolsignalwith
the saw-tooth wave.
VCPU isadjustedto5.1VwhileVCC is5V.ThisisdonebecausetheloadontheVCC isgreaterthan
the load on VCPU and the forward voltages of D8, D9, and D10 are higher than that of D7.The
voltage supplied to pin 6 of IC1 is called a dead time control signal. It controls the maximum
ONperiodoftheoutputtransistorinIC1.ThemaximumONperiodisrealizedonIC1byshorting
pin 6 and pin 16.
The saw-tooth wave oscillator of pin 1 of IC1 is used also for the control of this 5V power
supply(VLCD).Theoperationofthecircuitissimilartothatoftheother5Vpowersupply(VCPU and
VCC). The output voltage is fed back to pin 14 of IC1. The control signal is produced using a
voltagegeneratedbydividingthereferencevoltageinputtedtopin13ofIC1,andthefeedback
signal. The output voltage is stabilized by the pulse width from pin 10, which is generated by
comparing the control signal with the saw-tooth wave. VLCD is adjusted to 5.0V with VR2.
Fig. 14 +5V Power(VCC,VCPU,VLCD) Circuit