Silicon Laboratories SI5324 User manual

Preliminary Rev. 0.3 11/10 Copyright © 2010 by Silicon Laboratories Si5324
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5324
ANY-FREQUENCY PRECISION CLOCK
MULTIPLIER/JITTER ATTENUATOR
Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs as low as 290 fs rms
(12kHz–20MHz),320fsrms(50kHz–80MHz)
Integrated loop filter with selectable loop bandwidth
(4– 525 Hz)
Meets ITU-T G.8251 and Telcordia GR-253-CORE
jitter specification
Hitless input clock switching with phase build-out
Freerun, Digital Hold operation
Configurable signal format per output (LVPECL,
LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236, 239/237, 66/64,
239/238, 15/14, 253/221, 255/238)
LOL, LOS, FOS alarm outputs
I2C or SPI programmable
On-chip voltage regulator with high PSNR
Single supply 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
Small size: 6 x 6 mm 36-lead QFN
Applications
Broadcast video –3G/HD/SD-SDI, Genlock
Packet Optical Transport Systems (P-OTS), MSPP
OTN OTU-1/2/3/4 Asynchronous Demapping
(Gapped Clock)
SONET OC-48/192/768, SDH/STM-16/64/256 line
cards
1/2/4/8/10G Fibre Channel line cards
GbE/10/40/100G Synchronous Ethernet
(LAN/WAN)
Data converter clocking
Wireless base stations
Test and measurement
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter
performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from
2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to
1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device provides virtually any frequency
translation combination across this operating range. The Si5324 input clock frequency and clock multiplication ratio
are programmable via an I2C or SPI interface. The Si5324 is based on Silicon Laboratories' 3rd-generation
DSPLL®technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.

Si5324
2 Preliminary Rev. 0.3
Functional Block Diagram
DSPLL
®
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ NC1_LS
÷ NC2_LS
Skew Adjust
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Select
I2C/SPI Port
Control
Rate Select
÷N1_HS
Xtal/Refclock

Si5324
Preliminary Rev. 0.3 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Pin Descriptions: Si5324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10. Si5324 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Si5324
4 Preliminary Rev. 0.3
1. Electrical Specifications
Table 1. Performance Specifications
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Temperature Range TA–40 25 85 ºC
Supply Voltage VDD 2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.71 1.8 1.89 V
Supply Current IDD fOUT = 622.08 MHz
Both CKOUTs enabled
LVPECL format output
—251279mA
CKOUT2 disabled — 217 243 mA
fOUT = 19.44 MHz
Both CKOUTs enabled
CMOS format output
—204234mA
CKOUT2 disabled — 194 220 mA
Disable Mode — 165 — mA
Input Clock Frequency
(CKIN1, CKIN2) CKFInput frequency and clock
multiplication ratio deter-
mined by programming
device PLL dividers. Con-
sult Silicon Laboratories con-
figuration software
DSPLLsim to determine PLL
divider settings for a given
input frequency/clock multi-
plication ratio combination.
0.002 — 710 MHz
Output Clock Frequency
(CKOUT1, CKOUT2) CKOF 0.002
970
1213
—
—
—
945
1134
1400
MHz
3-Level Input Pins (RATE0 and RATE1)
Input Mid Current IIMM See Note 2. –2 — 2 µA
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing CKNDPP 0.25 — — VPP
Common Mode Voltage CKNVCM 1.8 V ±5% 0.9 — 1.4 V
2.5 V ±10% 1.0 — 1.7 V
3.3 V ±10% 1.1 — 1.95 V
Rise/Fall Time CKNTRF 20–80% — — 11 ns
Duty Cycle
(Minimum Pulse Width) CKNDC Whichever is smaller 40 — 60 %
2——ns
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.

Si5324
Preliminary Rev. 0.3 5
Output Clocks (CKOUT1, CKOUT2)
Common Mode VOCM LVPECL
100 load
line-to-line
VDD –1.42 — V
DD –1.25 V
Differential Output Swing VOD 1.1 — 1.9 V
Single Ended Output
Swing VSE 0.5 — 0.93 V
Rise/Fall Time CKOTRF 20–80%, fOUT = 622.08 MHz — 230 350 ps
Differential Duty Cycle
Uncertainty CKODC LVPECL
100 load
line-to-line
Measured at 50% point
——±40ps
PLL Performance (fIN = fOUT = 622.08 MHz, BW = 7 Hz)
Lock Time tLOCK End of ICAL to of LOL
Loop Bandwidth = 7 Hz,
FAST_LOCK = 1,
LOCKT = 1
1sec
Settle Time tSETTLE End of ICAL to 180° C of
final phase 60 sec
Phase Change After
Hitless Switch tP-STEP 100 200 ps
Jitter Generation
LVPECL output format JGEN 50 kHz–80 MHz — 320 420 fs rms
12 kHz–20 MHz — 290 410 fs rms
800 Hz–80 MHz — 320 450 fs rms
Jitter Peaking JPK ——0.1dB
Phase Noise CKOPN 100 Hz offset — –95 — dBc/Hz
1 kHz offset — –110 — dBc/Hz
10 kHz offset — –117 — dBc/Hz
100 kHz offset — –118 — dBc/Hz
1 MHz offset — –131 — dBc/Hz
Spurious Noise SPSPUR Max spur @ n x F3
(n > 1, n x F3 < 100 MHz) —–67—dBc
Package
Thermal Resistance
Junction to Ambient JA Still Air — 32 — ºC/W
Thermal Resistance
Case to Ambient JC Still Air — 14 — ºC/W
Table 1. Performance Specifications (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.

Si5324
6 Preliminary Rev. 0.3
Table 2. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
DC Supply Voltage VDD –0.5 — 3.8 V
LVCMOS Input Voltage VDIG –0.3 VDD+0.3 V
CKINn Voltage Level Limits CKNVIN 0—V
DD V
XA/XB Voltage Level Limits XAVIN 0—1.2V
Operating Junction Temperature TJCT –55 — 150 ºC
Storage Temperature Range TSTG –55 — 150 ºC
ESD HBM Tolerance
(100 pF, 1.5 k); All pins except
CKIN+/CKIN–
2——kV
ESD MM Tolerance; All pins
except CKIN+/CKIN– 150 — — V
ESD HBM Tolerance
(100 pF, 1.5 k); CKIN+/CKIN– 750 — — V
ESD MM Tolerance;
CKIN+/CKIN– 100 — — V
Latch-up Tolerance JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.

Si5324
Preliminary Rev. 0.3 7
2. Typical Phase Noise Performance
Figure 1. Broadcast Video
Jitter Bandwidth Jitter (peak-peak) Jitter (RMS)
10 Hz to 20 MHz 5.24 ps 484
Note: Number of samples: 8.91E9

Si5324
8 Preliminary Rev. 0.3
Figure 2. OTN/SONET/SDH Phase Noise
Note: Phase noise plot uses brick wall integration.
Jitter Bandwidth Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz 266 fs
SONET_OC192_A, 20 kHz to 80 MHz 283 fs
SONET_OC192_B, 4 MHz to 80 MHz 155 fs
SONET_OC192_C, 50 kHz to 80 MHz 275 fs
Brick Wall_800 Hz to 80 MHz 287 fs
Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs
per Telecordia GR-253-CORE.

Si5324
Preliminary Rev. 0.3 9
Figure 3. Wireless Base Station Phase Noise
Jitter Bandwidth Jitter (peak-peak) Jitter (RMS)
10 Hz to 20 MHz 7.28 ps 581
Note: Number of samples: 8.91E9

Si5324
10 Preliminary Rev. 0.3
Figure 4. Si5324 Typical Application Circuit (I2C Control Mode)
Figure 5. Si5324 Typical Application Circuit (SPI Control Mode)
GND PAD
Si5324 INT_C1B
C2B
LOL
RST
CKOUT1+
CKOUT1–
VDD
GND
Ferrite
Bead
System
Power
Supply
C1
C2
C3
Serial Data
Serial Clock
Reset
Interrupt/CKIN_1 Invalid Indicator
CKIN_2 Invalid Indicator
PLL Loss of Lock Indicator
Clock Outputs
CKOUT2+
CKOUT2–
SDA
SCL
I2C Interface
Serial Port Address
A[2:0]
CMODE
Control Mode (L)
100 
0.1 µF
0.1 µF
+
–
100 
0.1 µF
0.1 µF
+
–
C4
0.1 µF
0.1 µF
0.1 µF
1 µF
Clock Select/Clock Active
CS_CA
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
Notes:
XA
XB
Refclk+
Option 2: 0.1 µF
Refclk– 0.1 µF
RATE[1:0]2
Crystal/Ref Clk Rate
VDD
15 k
15 k
XA
XB
Crystal
Option 1:
Input
Clock
Sources*
CKIN2+
CKIN2–
130 130 
82 82 
VDD = 3.3 V
130 130 
82 82 
VDD = 3.3 V
CKIN1+
CKIN1–
GND PAD
Si5324
RST
CKOUT1+
CKOUT1–
VDD
GND
Ferrite
Bead
System
Power
Supply
C1
C2
C3
Reset
Clock Outputs
CKOUT2+
CKOUT2–
CMODEControl Mode (H)
CKIN2+
CKIN2–
100 
0.1 µF
0.1 µF
+
–
100 
0.1 µF
0.1 µF
+
–
C4
0.1 µF
0.1 µF
0.1 µF
1 µF
CKIN1+
CKIN1–
INT_C1B
C2B
SPI Interface
LOL
Interrupt/CLKIN_1 Invalid Indicator
CLKIN_2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Data Out
Serial Data In
SDO
SDI
Serial Clock
SCLK
Slave Select
SS
Clock Select/Clock Active
CS_CA
GND PAD
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
Notes:
Input
Clock
Sources*
130 130 
82 82 
VDD = 3.3 V
130 130 
82 82 
VDD = 3.3 V
XA
XB
Refclk+
Option 2: 0.1 µF
Refclk– 0.1 µF
RATE[1:0]2
Crystal/Ref Clk Rate
VDD
15 k
15 k
XA
XB
Crystal
Option 1:

Si5324
Preliminary Rev. 0.3 11
3. Functional Description
Figure 6. Si5324 Functional Block Diagram
The Si5324 is a low loop bandwidth, jitter-attenuating
clock multiplier for high performance applications. The
Si5324 accepts two input clocks ranging from 2 kHz to
710 MHz and generates two output clocks ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The Si5324 can also use its external reference as a
clock source for frequency synthesis. The device
provides virtually any frequency translation combination
across this operating range. Independent dividers are
available for each input clock and output clock, so the
Si5324 can accept input clocks at different frequencies
and it can generate output clocks at different
frequencies. The Si5324 input clock frequency and
clock multiplication ratio are programmable through an
I2C or SPI interface. Silicon Laboratories offers a PC-
based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This utility can be downloaded from
http://www.silabs.com/timing.
The Si5324 is based on Silicon Laboratories' 3rd-
generation DSPLL®technology, which provides any-
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5324
PLL loop bandwidth is digitally programmable and
supports a range from 4 Hz to 525 Hz. A fast lock
feature is available to reduce lock times inherent with
low loop bandwidth PLLs. The DSPLLsim software
utility can be used to calculate valid loop bandwidth
settings for a given input clock frequency/clock
multiplication ratio.
The Si5324 supports hitless switching between the two
synchronous input clocks in compliance with Telcordia
GR-253-CORE that greatly minimizes the propagation
of phase transients to the clock outputs during an input
clock transition (maximum 200 ps phase change).
Manual and automatic revertive and non-revertive input
clock switching options are available. The Si5324
monitors both input clocks for loss-of-signal (LOS) and
provides a LOS alarm when it detects missing pulses on
either input clock. The device monitors the lock status of
the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. Due to the
low loop bandwidth of the part, the LOL indicator clears
before the loop fully settles.
The Si5324 also monitors frequency offset alarms
(FOS), which indicate if an input clock is within a
specified frequency ppm accuracy relative to the
frequency of an XA/XB reference clock. Both Stratum
3/3E and SONET Minimum Clock (SMC) FOS
thresholds are supported.
The Si5324 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average frequency that existed a
fixed amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
DSPLL
®
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ NC1_LS
÷ NC2_LS
Skew Adjust
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Select
I2C/SPI Port
Control
Rate Select
÷N1_HS
Xtal/Refclock

Si5324
12 Preliminary Rev. 0.3
The Si5324 has two differential clock outputs. The signal format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or CMOS loads. When configured for CMOS, four clock outputs
are available. If not required, the second clock output can be powered down to minimize power consumption. In
addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. The
resolution varies from 800 ps to 2.2 ns depending on the PLL divider settings. The DSPLLsim software utility
determines the phase offset resolution for a given combination of input clock and multiplication ratio. For system-
level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing
the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply with best-in-class PSNR.
3.1. External Reference
An external, high quality 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal or external reference is
used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to
perform jitter attenuation. Specific recommendations can be found in the Family Reference Manual.
In digital hold, the DSPLL remains locked and tracks the external reference. Note that crystals can have
temperature sensitivities.
Due to the low bandwidth capabilities of this part, any low-frequency wander or instability on the external reference
will transfer to the output clocks. To address this issue, a stable external reference, TXCO, OCXO, or thermally-
isolated crystal is recommended.
For example, with a 20 ppm oscillator as the reference on the XA/XB pins, temperature changes cause the
oscillator to change frequency slightly. Although the Si5324 is locked to its input on CLKIN, it also uses the XA/XB
as a reference.
3.2. Additional Documentation
Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed
information about the Si5324. Additional design support is available from Silicon Laboratories through your
distributor.
Silicon Laboratories offers a PC-based software utility called DSPLLsim to simplify device configuration, including
frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from
http://www.silabs.com/timing.

Si5324
Preliminary Rev. 0.3 13
4. Pin Descriptions: Si5324
Pin # Pin Name I/O Signal Level Description
1RST ILVCMOSExternal Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are disabled during reset.
The part must be programmed after a reset or power-on to get a
clock output. See Family Reference Manual for details.
This pin has a weak pull-up.
2, 9, 14,
30, 33 NC No Connection.
Leave floating. Make no external connections to this pin for normal
operation.
3 INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The
pin functions as a maskable interrupt output with active polarity con-
trolled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS (and option-
ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and
INT_PIN =0.
0 = CKIN1 present.
1 = LOS (FOS) on CKIN1.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
4C2BOLVCMOSCKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for
CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
1
2
3
2930313233343536
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CKIN2+
CKIN2–
NC
RATE1
CKIN1+
CKIN1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1–
NC
GND
VDD
NC
CKOUT2– CKOUT2+
CMODE
GND
Pad
A0
GND
918 19
28
XB
LOL
GND
CKOUT1+

Si5324
14 Preliminary Rev. 0.3
5, 10, 32 VDD VDD Supply Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following Vdd pins:
50.1µF
10 0.1 µF
32 0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
7
6XB XA IAnalogExternal Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by RATE[1:0] pins.
8, 31, 20,
19 GND GND Supply Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
15 RATE0 RATE1 I 3-Level External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to VDD/2.
H setting corresponds to VDD.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
16
17 CKIN1+ CKIN1– IMultiClock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
13 CKIN2+ CKIN2– IMultiClock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
18 LOL O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324
Preliminary Rev. 0.3 15
21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1.
1 = Select CKIN2.
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-
tion and this input tristates. If configured for input, must be tied high
or low.
Output: In automatic clock selection mode, this pin indicates which
of the two input clocks is currently the active clock. If alarms exist on
both clocks, CK_ACTV will indicate the last active clock that was
used before entering the digital hold state. The CK_ACTV_PIN reg-
ister bit must be set to 1 to reflect the active clock status to the
CK_ACTV output pin.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will
always be reflected in the CK_ACTV_REG read only register bit.
22 SCL I LVCMOS Serial Clock.
This pin functions as the serial clock input for both SPI and I2C
modes.
This pin has a weak pull-down.
23 SDA_SDO I/O LVCMOS Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial
data output.
25
24 A1 A0 ILVCMOSSerial Port Address.
In I2C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I2C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
26 A2_SSILVCMOSSerial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27 SDI I LVCMOS Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324
16 Preliminary Rev. 0.3
29
28 CKOUT1– CKOUT1+ OMultiOutput Clock 1.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by SFOUT1_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
34
35 CKOUT2– CKOUT2+ OMultiOutput Clock 2.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by SFOUT2_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
36 CMODE I LVCMOS Control Mode.
Selects I2C or SPI control mode for the Si5324.
0=I
2C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
GND PAD GND GND Supply Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Si5324
Preliminary Rev. 0.3 17
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, e.g. Register 64, should never be written to.
Register D7 D6 D5 D4 D3 D2 D1 D0
0 FREE_RUN CKOUT_
ALWAYS_ON BYPASS_REG
1CK_PRIOR2[1:0] CK_PRIOR[1:0]
2 BWSEL_REG[3:0]
3 CKSEL_REG[1:0] DHOLD SQ_ICAL
4 AUTOSEL_REG[1:0] HST_DEL[4:0]
5 ICMOS[1:0]
6 SLEEP SFOUT2_REG[2:0} SFOUT1_REG[2:0]
7FOSREFSEL[2:0]
8 HLOG_2[1:0] HLOG_1[1:0]
9 HIST_AVG[4:0]
10 DSBL2_ REG DSBL1_ REG
11 PD_CK2 PD_CK1
19 FOS_EN FOS_THR[1:0] VALTIME[1:0] LOCK[T2:0]
20 CK2_BAD_PIN CK1_ BAD_ PIN LOL_PIN INT_PIN
21 CK1_ACTV_PIN CKSEL_PIN
22 CK_ACTV_ POL CK_BAD_ POL LOL_POL INT_POL
23 LOS2_MSK LOS1_MSK LOSX_MSK
24 FOS2_MSK FOS1_MSK LOL_MSK
25 N1_HS[2:0]
31 NC1_LS[19:16]
32 NC1_LS[15:8]
33 NC1_LS[7:0]
34 NC2_LS[19:16]
35 NC2_LS[15:8]
36 NC2_LS[7:0]
40 N2_HS[2:0] N2_LS[19:16]
41 N2_LS[15:8]
42 N2_LS[7:0]
43 N31[18:16]
44 N31[15:8]
45 N31[7:0]
46 N32[18:16]

Si5324
18 Preliminary Rev. 0.3
47 N32[15:8]
48 N32[7:0]
55 CLKIN2RATE[2:0] CLKIN1RATE[2:0]
128 CK2_ACTV_REG CK1_ACTV_REG
129 LOS2_INT LOS1_INT LOSX_INT
130 DIGHOLD-
VALID FOS2_INT FOS1_INT LOL_INT
131 LOS2_FLG LOS1_FLG LOSX_FLG
132 FOS2_FLG FOS1_FLG LOL_FLG
134 PARTNUM_RO[11:4]
135 PARTNUM_RO[3:0] REVID_RO[3:0]
136 RST_REG ICAL
137 FASTLOCK
138 LOS2_EN [1:1] LOS1_EN [1:1]
139 LOS2_EN[0:0] LOS1_EN[0:0] FOS2_EN FOS1_EN
142 INDEPENDENTSKEW1[7:0]
143 INDEPENDENTSKEW2[7:0]
185 NVM_REVID[7:0]
Table 3. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
CKOUT_ALWAYS_ON SQ_ICAL Results
0 0 CKOUT OFF until after the first ICAL
0 1 CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1 0 CKOUT always ON, including during an ICAL
1 1 CKOUT always ON, including during an ICAL.
Use these settings to preserve output-to-output
skew
Register D7 D6 D5 D4 D3 D2 D1 D0

Si5324
Preliminary Rev. 0.3 19
6. Register Descriptions
Reset value = 0001 0100
Register 0.
BitD7D6 D5 D4D3D2D1D0
Name FREE_RUN CKOUT_
ALWAYS_ON BYPASS_ REG
Type RR/WR/W RRRR/WR
Bit Name Function
7 Reserved Reserved.
6FREE_RUNFree Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB
reference.
0: Disable
1: Enable
5CKOUT_
ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 3 on page 18.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the part is calibrated.
2. Must be 1 to control output to output skew.
4:2 Reserved Reserved.
1 BYPASS_
REG Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is in digital
hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
0 Reserved Reserved.

Si5324
20 Preliminary Rev. 0.3
Reset value = 1110 0100
Reset value = 0100 0010
Register 1.
BitD7D6D5D4D3D2D1D0
Name Reserved CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]
Type RR/WR/W
Bit Name Function
7:4 Reserved Reserved.
3:2 CK_PRIOR2
[1:0] CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0 CK_PRIOR1
[1:0] CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
Register 2.
BitD7D6D5D4D3D2D1D0
Name BWSEL_REG [3:0] Reserved
Type R/W R
Bit Name Function
7:4 BWSEL_REG
[3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
3:0 Reserved Reserved.