Silicon Laboratories Si4468/7 User manual

Rev 1.0 10/14 Copyright © 2014 by Silicon Laboratories Si4468/7
Si4468/7
HIGH-PERFORMANCE, LOW-CURRENT TRANSCEIVER
Features
Applications
Description
Silicon Laboratories' Si446x devices are high-performance, low-current
transceivers covering the sub-GHz frequency bands from 142 to 1050 MHz. The
radios are part of the EZRadioPRO®family, which includes a complete line of
transmitters, receivers, and transceivers covering a wide range of applications. A
high level of integration including support for IEEE 802.15.4 features enables
standards based sub GHz networking solutions. All parts offer outstanding
sensitivity of –133 dBm while achieving extremely low active and standby current
consumption. The Si4468/7 offers frequency coverage in all major bands. The
Si446x includes optimal phase noise, blocking, and selectivity performance for
narrow band and licensed band applications, such as FCC Part90 and 169 MHz
wireless MBus. The 69 dB adjacent channel selectivity with 12.5 kHz channel
spacing ensures robust receive operation in harsh RF conditions, which is
particularly important for narrow band operation. The Si4468 offers exceptional
output power of up to +20 dBm with outstanding TX efficiency. The high output
power and sensitivity results in an industry-leading link budget of 155 dB allowing
extended ranges and highly robust communication links. The Si4467 active mode
TX current consumption of 18 mA at +10 dBm and RX current of 10 mA coupled
with extremely low standby current and fast wake times ensure extended battery
life in the most demanding applications. The Si4468 can achieve up to +27 dBm
output power with built-in ramping control of a low-cost external FET. The devices
can meet worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are
designed to be compliant with 802.15.4g and WMBus smart metering standards.
The devices are highly flexible and can be configured via the Wireless
Development Suite (WDS) available at www.silabs.com.
Frequency range = 142–1050 MHz
Receive sensitivity = –133 dBm @
100 bps plus fast-scanning AFC for
standard TCXO applications
Modulation
(G)FSK, 4(G)FSK, (G)MSK
OOK
Max output power
+20 dBm (Si4468)
+13 dBm (Si4467)
PA support for +27 or +30 dBm
Low active power consumption
10/13 mA RX
18 mA TX at +10 dBm (Si4467)
Ultra low current powerdown modes
30 nA shutdown, 40 nA standby
Preamble sense mode
6 mA average RX current at
1.2 kbps
10 µA average RX current at
50 kbps and 1 sec sleep interval
Fast preamble detection
1 byte preamble detection
Data rate = 100 bps to 1 Mbps
Fast wake and hop times
Power supply = 1.8 to 3.8 V
Excellent selectivity performance
69 dB adjacent channel
79 dB blocking at 1 MHz
Antenna diversity and T/R switch control
Highly configurable packet handler
TX and RX 64 byte FIFOs
129 bytes dedicated Tx or Rx FIFO
Auto frequency control (AFC)
Automatic gain control (AGC)
Low BOM
Low battery detector
Temperature sensor
20-Pin QFN package
Sub-GHz 802.15.4 mesh network ready
IEEE 802.15.4g, and WMBus compliant
Suitable for FCC Part 90 Mask D, FCC
part 15.247, 15,231, 15,249, ARIB T-108,
T-96, T-67, RCR STD-30, China
regulatory
ETSI Category I Operation
EN 300 220
Smart metering (802.15.4g and WMBus)
802.15.4 mesh networking
Home security and alarm
Teleme tr y
Garage and gate openers
Star and point-to-point networks
Home automation
Ultra narrowband, long range
applications
Industrial control
Sensor networks
Health monitors
Electronic shelf labels
Low power wireless sensor
nodes
Patents pending
Pin Assignments
GND
PAD
1
2
3
17181920
11
12
13
14
67 8 9
4
5
16
10
15
GND
GPIO1
nSEL
SDI
SDO
SCLKNC
SDN
TX
GPIO0
VDD
nIRQ
RXp
RXn
XIN GPIO3 GPIO2 XOUT
TXRamp
VDD

Si4468/7
2 Rev 1.0
Functional Block Diagram
Product Freq. Range Max Output Power Ultra Narrow Band
Support IEEE 802.15.4 / 4g Ready
Si4468 Major bands
142–1050 MHz
+20 dBm 
Si4467 Major bands
142–1050 MHz
+13 dBm 
VCO
Loop
Filter PFD / CP
Frac-N Div 30 MHz XO
LO
Gen
LNA
RF
PKDET
PGA ADC
MODEM
FIFO
Packet
Handler
32K LP
OSC
Bootup
OSC
LBD
POR
IF
PKDET
SPI Interface
Controller
Digital
Logic
PowerRamp
Cntl
PA
LDO
TX DIV
RXP
RXN
TX
TXRAMP
XOUTXIN
nSEL
SDI
SDO
SCLK
nIRQ
LDOs
FBDIV
PA
VDD GPIO0 GPIO1
GPIO2GPIO3
SDN

Si4468/7
Rev 1.0 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.6. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.2. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.3. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.1. RX Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2. RX Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.4. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.2. Low Duty Cycle Mode (Auto RX Wake-Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8.5. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
8.6. Preamble Sense Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9. Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9.1. Wireless MBus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9.2. ETSI EN300 220 Category 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9.3. IEEE 802.15.4 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
10. Packet Trace Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
11. Pin Descriptions: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
13. Package Outline: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
14. PCB Land Pattern: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
15. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15.1. Si4468/7 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Si4468/7
4 Rev 1.0
1. Electrical Specifications
Table 1. DC Characteristics1
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage
Range
VDD 1.8 3.3 3.8 V
Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
— 30 1300 nA
IStandby Register values maintained and RC
oscillator/WUT OFF
— 40 2900 nA
ISleepRC RC Oscillator/WUT ON and all register values main-
tained, and all other blocks OFF
— 740 3800 nA
ISleepXO Sleep current using an external 32 kHz crystal — 1.7 — µA
ISensor
-LBD
Low battery detector ON, register values maintained,
and all other blocks OFF
—1—µA
IReady Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF
—1.8—mA
Preamble Sense
Mode Current
Ipsm Duty cycling during preamble search,
1.2 kbps, 4 byte preamble (no sensitivity degradation)
—6—mA
Ipsm Fixed 1 s wakeup interval, 50 kbps, 5 byte preamble — 10 — µA
TUNE Mode Current ITune_RX RX Tune, High Performance Mode — 7.6 — mA
ITune_TX TX Tune, High Performance Mode — 7.8 — mA
RX Mode Current IRXH High Performance Mode
Measured at 915 MHz and 40 kbps data rate.
—13.722 mA
IRXL Low Power Mode Measured at 315 MHz and 40 kbps
data
—10.9— mA
TX Mode Current
(Si4468)
ITX_+20 +20 dBm output power, Class-E match,
915 MHz, 3.3 V
—88108mA
+20 dBm output power, square-wave match,
169 MHz, 3.3 V
—68.580 mA
+13 dBm output power, Class-E match,
915 MHz, 3.3 V
—44.560 mA
TX Mode Current
(Si4467)
ITX_+10 +10 dBm output power, Class-E match,
915/868 MHz, 3.3 V2
—19.7— mA
ITX_+10 +10 dBm output power, Class-E match,
169 MHz, 3.3 V2
—18—mA
ITX_+13 +13 dBm output power, Class-E match,
915/868 MHz, 3.3 V
—24—mA
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. Measured on direct tie RF evaluation board.

Si4468/7
Rev 1.0 5
Table 2. Synthesizer AC Electrical Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Synthesizer Frequency
Range
FSYN 850 — 1050 MHz
350 — 525 MHz
284 — 350 MHz
142 — 175 MHz
Synthesizer Frequency
Resolution
FRES-960 850–1050 MHz —28.6— Hz
FRES-525 420–525 MHz —14.3— Hz
FRES-420 350–420 MHz —11.4— Hz
FRES-350 283–350 MHz —9.5— Hz
FRES-175 142–175 MHz —4.7— Hz
Synthesizer Settling Time tLOCK Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO Calibration.
—50— µs
Phase Noise L(fM)F = 10 kHz, 169 MHz, High Perf Mode — –117 –108 dBc/Hz
F = 100 kHz, 169 MHz, High Perf Mode — –120 –115 dBc/Hz
F = 1 MHz, 169 MHz, High Perf Mode — –138 –135 dBc/Hz
F = 10 MHz, 169 MHz, High Perf Mode — –148 –143 dBc/Hz
F = 10 kHz, 915 MHz, High Perf Mode — –102 –94 dBc/Hz
F = 100 kHz, 915 MHz, High Perf Mode — –105 –97 dBc/Hz
F = 1 MHz, 915 MHz, High Perf Mode — –125 –122 dBc/Hz
F = 10 MHz, 915 MHz, High Perf Mode — –138 –135 dBc/Hz
Note: All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.

Si4468/7
6 Rev 1.0
Table 3. Receiver AC Electrical Characteristics1,2
Parameter Symbol Test Condition Min Typ Max Unit
RX Frequency Range FRX 850 — 1050 MHz
350 — 525 MHz
284 — 350 MHz
142 — 175 MHz
RX Sensitivity 169 MHz3PRX_0.1 (BER < 0.1%)
(100 bps, GFSK, BT = 0.5,
f=100 Hz)
—–133—dBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f=20 kHz)
—–110–108dBm
PRX_100 (BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f=50 kHz)
— –106 –104 dBm
PRX_500 (BER < 0.1%)
(500 kbps, GFSK, BT = 0.5,
f=250 kHz)
— –98 –96 dBm
PRX_9.6 (PER 1%)
(9.6 kbps, 4GFSK, BT = 0.5,
f = ±2.4 kHz)
—–110—dBm
PRX_1M (PER 1%)
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)
— –89 — dBm
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW,
OOK, PN15 data)
—–110–107dBm
(BER < 0.1%, 40 kbps, 350 kHz BW,
OOK, PN15 data)
— –103 –100 dBm
(BER < 0.1%, 120 kbps, 350 kHz BW,
OOK, PN15 data)
— –97 –93 dBm
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used.
3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better
if reading data from packet handler FIFO especially at higher data rates.
4. Conducted emissions measured on RF evaluation boards.

Si4468/7
Rev 1.0 7
RX Sensitivity
915/868 MHz3PRX_0.1 (BER < 0.1%)
(100 bps, GFSK, BT = 0.5,
f=100 Hz)
—–132—dBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f=20 kHz)
— –109 –107 dBm
PRX_100 (BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f=50 kHz)
— –104 –102 dBm
PRX_500 (BER < 0.1%)
(500 kbps, GFSK, BT = 0.5,
f=250 kHz)
— –97 –92 dBm
PRX_9.6 (PER 1%)
(9.6 kbps, 4GFSK, BT = 0.5,
f= kHz)
—–109—dBm
PRX_1M (PER 1%)
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)
— –88 — dBm
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW,
OOK, PN15 data)
— –108 –104 dBm
(BER < 0.1%, 40 kbps, 350 kHz BW,
OOK, PN15 data)
— –101 –97 dBm
(BER < 0.1%, 120 kbps, 350 kHz BW,
OOK, PN15 data)
— –96 –91 dBm
RX Channel Bandwidth BW 0.2 — 850 kHz
RSSI Resolution RESRSSI Valid from –110 dBm to –90 dBm — ±0.5 — dB
1-Ch Offset Selectivity,
169 MHz3
C/I1-CH Desired Ref Signal 3 dB above sensitiv-
ity, BER < 0.1%. Interferer is CW, and
desired is modulated with 2.4 kbps
F = 1.2 kHz GFSK with BT = 0.5, RX
channel BW = 4.8 kHz,
channel spacing = 12.5 kHz
–69 –59 dB
1-Ch Offset Selectivity,
450 MHz3
C/I1-CH –60 –50 dB
1-Ch Offset Selectivity,
868 / 915 MHz3
C/I1-CH –55 –45 dB
Blocking 1 MHz Offset 1MBLOCK Desired Ref Signal 3 dB above sensitiv-
ity, BER = 0.1%. Interferer is CW, and
desired is modulated with 2.4 kbps,
F = 1.2 kHz GFSK with BT = 0.5,
RX channel BW = 4.8 kHz
–79 –68 dB
Blocking 8 MHz Offset 8MBLOCK –86 –75 dB
Table 3. Receiver AC Electrical Characteristics1,2 (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used.
3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better
if reading data from packet handler FIFO especially at higher data rates.
4. Conducted emissions measured on RF evaluation boards.

Si4468/7
8 Rev 1.0
Image Rejection
(IF = 468.75 kHz)
ImREJ No image rejection calibration. Rejec-
tion at the image frequency.
RF = 460 MHz
30 40 — dB
With image rejection calibration in
Si446x. Rejection at the image fre-
quency. RF = 460 MHz
40 55 — dB
No image rejection calibration. Rejec-
tion at the image frequency.
RF = 915 MHz
30 45 — dB
With image rejection calibration in
Si446x. Rejection at the image fre-
quency. RF = 915 MHz
40 52 — dB
No image rejection calibration. Rejec-
tion at the image frequency.
RF = 169 MHz
35 45 — dB
With image rejection calibration in
Si446x. Rejection at the image fre-
quency. RF = 169 MHz
45 60 — dB
Table 3. Receiver AC Electrical Characteristics1,2 (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used.
3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better
if reading data from packet handler FIFO especially at higher data rates.
4. Conducted emissions measured on RF evaluation boards.

Si4468/7
Rev 1.0 9
Table 4. Transmitter AC Electrical Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
TX Frequency
Range
FTX 850 — 1050 MHz
350 — 525 MHz
284 — 350 MHz
142 — 175 MHz
(G)FSK Data Rate DRFSK 0.1 — 500 kbps
4(G)FSK Data Rate DR4FSK 0.2 — 1000 kbps
OOK Data Rate DROOK 0.1 — 120 kbps
Modulation Deviation
Range f960 850–1050 MHz —1.5—MHz
f525 420–525 MHz —750—kHz
f420 350–420 MHz —600—kHz
f350 283–350 MHz —500—kHz
f175 142–175 MHz —250—kHz
Modulation Deviation
Resolution
FRES-960 850–1050 MHz —28.6 —Hz
FRES-525 420–525 MHz —14.3 —Hz
FRES-420 350–420 MHz —11.4 —Hz
FRES-350 283–350 MHz —9.5 —Hz
FRES-175 142–175 MHz —4.7 —Hz
Output Power Range
(Si4468) PTX68 Typical range at 3.3 V –20 — +20 dBm
Output Power Range
(Si4467) PTX67 Typical range at 3.3 V with Class E
match optimized for best PA efficiency –20 — +12.5 dBm
Output Power Variation
(Si4468) At 20 dBm PA power setting, 915 MHz,
Class E match, 3.3 V, 25 °C 19 20 21 dBm
Output Power Variation
(Si4467) At 10 dBm PA power setting, 915 MHz,
Class E match, 3.3 V, 25 °C 91011dBm
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula: Maximum Symbol
Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
3. Default API setting for modulation deviation resolution is double the typical value specified.
4. Output power is dependent on matching components and board layout.

Si4468/7
10 Rev 1.0
Output Power Variation
(Si4468) At 20 dBm PA power setting, 169 MHz,
Square Wave match, 3.3 V, 25 °C 18.5 20 21 dBm
Output Power Variation
(Si4467) At 10 dBm PA power setting, 169 MHz,
Class E match, 3.3 V, 25 °C 9.5 10 10.5 dBm
TX RF Output Steps PRF_OUT
Using switched current match within
6 dB of max power using CLE match
within 6 dB of max power
— 0.25 0.4 dB
TX RF Output Level
Variation vs. Temperature PRF_TEMP –40 to +85 C—2.33dB
TX RF Output Level
Variation vs. Frequency PRF_FREQ Measured across 902–928 MHz — 0.6 1.7 dB
Transmit Modulation
Filtering BT Gaussian Filtering Bandwith Time
Product —0.5—
Table 4. Transmitter AC Electrical Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula: Maximum Symbol
Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
3. Default API setting for modulation deviation resolution is double the typical value specified.
4. Output power is dependent on matching components and board layout.

Si4468/7
Rev 1.0 11
Table 5. Auxiliary Block Specifications1
Parameter Symbol Test Condition Min Typ Max Unit
Temperature Sensor
Sensitivity
TSS— 4.5 — ADC
Codes/
°C
Low Battery Detector
Resolution
LBDRES —50—mV
Microcontroller Clock
Output Frequency Range2
FMC Configurable to Fxtal or Fxtal
divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
32.768K — Fxtal Hz
Temperature Sensor
Conversion
TEMPCT Programmable setting — 3 — ms
XTAL Range3XTALRange 25 — 32 MHz
30 MHz XTAL Start-Up Time t30M Start-up time will vary with
XTAL type and board layout.
— 300 — µs
30 MHz XTAL Cap
Resolution
30MRES —70—fF
32 kHz XTAL Start-Up Time t32k —2—sec
32 kHz Accuracy using
Internal RC Oscillator
32KRCRES — 2500 — ppm
POR Reset Time tPOR ——6ms
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –45 to +85 °C unless otherwise stated. All typical values apply at Vdd=3.3V and 25C unless otherwise stated.
2. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz, 32 MHz, and 32.768 kHz. Other frequencies
tested by bench characterization.
3. XTAL Range tested in production using an external clock source (similar to using a TCXO).

Si4468/7
12 Rev 1.0
Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1
Parameter Symbol Test Condition Min Typ Max Unit
Rise Time2,3 TRISE 0.1 x VDD to 0.9 x VDD,
CL=10pF,
DRV<1:0> = LL
—2.3— ns
Fall Time3,4 TFALL 0.9 x VDD to 0.1 x VDD,
CL=10pF,
DRV<1:0> = LL
—2—ns
Input Capacitance CIN —2—pF
Logic High Level Input Voltage VIH VDD x0.7 — — V
Logic Low Level Input Voltage VIL ——V
DD x0.3 V
Input Current IIN 0<VIN< VDD –1 — 1 µA
Input Current If Pullup is Activated IINP VIL =0V 1 — 4 µA
Drive Strength for Output Low
Level
IOmaxLL DRV[1:0] = LL3—6.66— mA
IOmaxLH DRV[1:0] = LH3—5.03— mA
IOmaxHL DRV[1:0] = HL3—3.16— mA
IOmaxHH DRV[1:0] = HH3—1.13— mA
Drive Strength for Output High
Level
IOmaxLL DRV[1:0] = LL3—5.75— mA
IOmaxLH DRV[1:0] = LH3—4.37— mA
IOmaxHL DRV[1:0] = HL3—2.73— mA
IOmaxHH DRV[1:0] = HH3—0.96— mA
Drive Strength for Output High
Level for GPIO0
IOmaxLL DRV[1:0] = LL3—2.53— mA
IOmaxLH DRV[1:0] = LH3—2.21— mA
IOmaxHL DRV[1:0] = HL3—1.70— mA
IOmaxHH DRV[1:0] = HH3—0.80— mA
Logic High Level Output Voltage VOH DRV[1:0] = HL VDD x0.8 — — V
Logic Low Level Output Voltage VOL DRV[1:0] = HL — — VDD x0.2 V
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage
and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise
stated.
2. 6.7 ns is typical for GPIO0 rise time.
3. Assuming VDD = 3.3 V, drive strength is specified at Voh (min) = 2.64 V and Vol(max) = 0.66 V at room temperature.
4. 2.4 ns is typical for GPIO0 fall time.

Si4468/7
Rev 1.0 13
Table 7. Thermal Characteristics
Parameter Symbol Value Unit
Operating Ambient Temperature Range TA–40 to +125 °C
Thermal Impedance Junction to Ambient* JA 25 °C/w
Junction Temperature Maximum Value* Tj+137 °C
Storage Temperature Range TSTG –55 to +150 °C
*Note: JA and Tjare based on RF evaluation board measurements.
Table 8. Absolute Maximum Ratings
Parameter Value Unit
VDD to GND –0.3, +3.8 V
Instantaneous VRF-peak to GND on TX Output Pin –0.3, +8.0 V
Sustained VRF-peak to GND on TX Output Pin –0.3, +6.5 V
Voltage on Analog Inputs –0.7, VDD + 0.3 V
RX Input Power +10 dBm
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX
matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.

Si4468/7
14 Rev 1.0
2. Functional Description
The Si446x devices are high-performance, low-current, wireless ISM transceivers that cover the sub-GHz bands.
A key feature of the Si4468/7 is the support for IEEE 802.15.4g PHY and some features of 802.15.4 above the
physical layer, which enables low-power, long-range networking solutions including mesh networking. In
conjunction with Silicon Labs industry-leading ZigBee SoCs and EFM32 energy-friendly 32-bit ARM based
microcontrollers, the Si4468/7 enables low-power solutions from sub GHz to 2.4 GHz for various “Internet of
Things” applications.
The wide operating voltage range of 1.8–3.8 V and low current consumption make the Si446x an ideal solution for
battery powered applications. The Si446x operates as a time division duplexing (TDD) transceiver where the
device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert
the 2/4-level FSK/GFSK or OOK modulated receive signal to a low IF frequency. Following a programmable gain
amplifier (PGA) the signal is converted to the digital domain by a high performance  ADC allowing filtering,
demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s
performance and flexibility versus analog based architectures. The demodulated signal is output to the system
MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and
receiver do not operate at the same time. The LO is generated by an integrated VCO and  Fractional-N PLL
synthesizer. The synthesizer is designed to support configurable data rates from 100 bps to 1 Mbps. The Si4468/7
operate in the frequency bands of 142–175, 283–350, 350–525, and 850–1050 MHz with a maximum frequency
accuracy step size of 28.6 Hz. The transmit FSK data is modulated directly into the  data stream and can be
shaped by a Gaussian low-pass filter to reduce unwanted spectral content.
The Si4468 contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency,
consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be
used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size
constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve
comparable performance. The Si4467 is designed to support single coin cell operation with current consumption
below 18 mA for +10 dBm output power. Two match topologies are available for the Si4467: Class-E and
switched-current. Class-E matching provides optimal current consumption, while switched-current matching
demonstrates the best performance over varying battery voltage and temperature with slightly higher current
consumption. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates
automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The Si446x family supports
frequency hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and
improve performance. Built-in antenna diversity and support for frequency hopping can be used to further extend
range and enhance performance. Antenna diversity is completely integrated into the Si446x and can improve the
system link budget by 8–10 dB, resulting in substantial range increases under adverse environmental conditions. A
highly configurable packet handler allows for autonomous encoding/decoding of nearly any packet structure.
Additional system features, such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, and
preamble detection, reduce overall current consumption and allows for the use of lower-cost system MCUs. An
integrated temperature sensor, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The
Si446x is designed to work with an MCU, crystal, and a few passive components to create a very low-cost system.
2.1. Boot Modes
The Si4468/7 has two boot modes. One boot mode supports 802.15.4 functionality to enable standards-based,
sub-GHz mesh networking with support for 802.15.4 MR-FSK PHY (15.4g) and key MAC (15.4) features. The
second boot mode supports legacy Si4463/1/0 compatibility and is intended to support proprietary solutions that
require additional flexibility in configuring the device. The legacy boot mode is called EZRadioPRO boot mode.
This mode is software- and hardware-compatible with Si4463/1/0 and also supports 802.15.4g PHY and WMBus
operation. The boot mode selection is done using the POWER_UP command and is described in the API
documentation.
The application shown in Figure 1 is designed for a system with a TX/RX direct-tie configuration without the use of
a TX/RX switch. Figure 2 demonstrates an application for +20 dBm using an external T/R-switch.

Si4468/7
Rev 1.0 15
Figure 1. Si4467 Direct-Tie Application Example
Figure 2. Si4468 Single Antenna with RF Switch Example
30 MHz
Microcontroller
GP1
GP2
GP3
GP4
C1
L1
L3
L2
C3 C2
SDN nSEL
19 18 17 16
1
2
3
4
15
14
13
78910
SDI
SDO
SCLK
TX
RXp
RXn
TXRAMP
VDD
GPIO1
XIN
GPIO3
GND
XOUT
GPIO0
5
NC
6
VDD
20
GPIO2
11
12
GP5
C7 Si4467
nIRQ
VDD
C6
L5
C8
C4
L4
C5
30 MHz
Microcontroller
GP1
GP2
GP3
GP4
C1
L1
L3 L2
C3 C2
SDN nSEL
19 18 17 16
1
2
3
4
15
14
13
78910
SDI
SDO
SCLK
TX
RXp
RXn
TXRAMP
VDD
GPIO1
XIN
GPIO3
GND
XOUT
GPIO0
5
NC
6
VDD
20
GPIO2
11
12
GP5
L4 C6 Si4468
nIRQ
VDD
C5 C4
L5
C7

Si4468/7
16 Rev 1.0
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si446x communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,
SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters
are demonstrated in Table 9. The host MCU writes data over the SDI pin and can read data from the device on the
SDO output pin. Figure 3 demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI
command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data
which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the
center of the SDI data.
Figure 3. SPI Write Command
The Si446x contains an internal MCU which controls all the internal functions of the radio. For SPI read commands
a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the
command and prepared the data to be output over the SDO pin. Figure 4 demonstrates the general flow of an SPI
read command. Once the CTS value reads FFh then the read data is ready to be clocked out to the host MCU. The
typical time for a valid FFh CTS reading is 20 µs. Figure 5 demonstrates the remaining read cycle after CTS is set
to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the
SDO data on the rising edge of SCLK.
Table 9. Serial Interface Timing Parameters
Symbol Parameter Min
(ns) Max (ns) Diagram
tCH Clock high time 40
tCL Clock low time 40
tDS Data setup time 20
tDH Data hold time 20
tDD Output data delay time 43
tDE Output disable time 45
tSS Select setup time 20
tSH Select hold time 50
tSW Select high period 80
*Note: CL = 10 pF; VDD = 1.8 V; SDO Drive strength setting = 10.
SCLK
SDI
SDO
nSEL
tCL
tSS tCH tDS tDH tDD tSH tDE
tSW
FW Command Param Byte 0 Param Byte n
nSEL
SDO
SDI
SCLK

Si4468/7
Rev 1.0 17
Figure 4. SPI Read Command—Check CTS Value
Figure 5. SPI Read Command—Clock Out Read Data
Send Command Read CTS Retrieve
Response
CTS Value
0x00
0xFF
Firmware Flow
ReadCmdBuff
NSEL
SDO
SDI
SCK
CTS
NSEL
SDO
SDI
SCK
Response Byte 0 Response Byte n

Si4468/7
18 Rev 1.0
3.2. Fast Response Registers
The fast response registers are registers that can be read immediately without the requirement to monitor and
check CTS. There are four fast response registers that can be programmed for a specific function. The fast
response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B,
0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the
“FRR_CTL_X_MODE” properties.
The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional eight
clock cycles will clock out the contents of the next fast response register in a circular fashion. The value of the
FRRs will not be updated unless NSEL is toggled.
3.3. Operating Modes and Timing
The primary states of the Si446x are shown in Figure 6. The shutdown state completely shuts down the radio to
minimize current consumption. Standby/Sleep, SPI Active, Ready, TX Tune, and RX tune are available to optimize
the current consumption and response time to RX/TX for a given application. API commands START_RX,
START_TX, and CHANGE_STATE control the operating state with the exception of shutdown which is controlled
by SDN, pin 1. Table 10 shows each of the operating modes with the time required to reach either RX or TX mode
as well as the current consumption of each mode. The times in Table 9 are measured from the rising edge of nSEL
until the chip is in the desired state. Note that these times are indicative of state transition timing but are not
guaranteed and should only be used as a reference data point. An automatic sequencer will put the chip into RX or
TX from any state. It is not necessary to manually step through the states. To simplify the diagram it is not shown
but any of the lower power states can be returned to automatically after RX or TX.
Figure 6. State Machine Diagram

Si4468/7
Rev 1.0 19
Figure 7 shows the POR timing and voltage requirements. The power consumption (battery life) depends on the
duty cycle of the application or how often the part is in either Rx or Tx state. In most applications the utilization of
the standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will
have an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API
commands to minimize SPI transactions and internal MCU processing.
3.3.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms. If VDD is removed,
then it must stay below 0.15 V for at least 10 ms before being applied again. See Figure 7 and Table 11 for details.
Figure 7. POR Timing Diagram
Table 10. Operating State Response Time and Current Consumption
State/Mode Response Time to Current in State
/Mode
TX RX
ShutdownState 15ms 15ms 30nA
Standby State
Sleep State
SPI Active State
Ready State
TX Tune State
RX Tune State
440 µs
440 µs
340 µs
100 µs
58 µs
—
440 µs
440 µs
340 µs
100 µs
—
60 µs
40 nA
740 nA
1.35 mA
1.8 mA
7.8 mA
7.6 mA
TX State — 100 µs 18 mA @ +10 dBm
RX State 100 µs 75 µs 10.9 or 13.7 mA
Note: TXRX and RXTX state transition timing can be reduced to 70 µs if using Zero-IF mode.
VDD
Time
VRRH
tSR tPORH
VRRL

Si4468/7
20 Rev 1.0
3.3.2. Shutdown State
The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of current
consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN pin should be held
low in all states except the shutdown state. In the shutdown state, the contents of the registers are lost and there is
no SPI access. When coming out of the shutdown state a power on reset (POR) will be initiated along with the
internal calibrations. After the POR the POWER_UP command is required to initialize the radio. The SDN pin
needs to be held high for at least 10us before driving low again so that internal capacitors can discharge. Not
holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly.
If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the
host processor rather than tying it to GND on the board.
3.3.3. Standby State
Standby state has the lowest current consumption with the exception of shutdown but has much faster response
time to RX or TX mode. In most cases standby should be used as the low power state. In this state the register
values are maintained with all other blocks disabled. The SPI is accessible during this mode but any SPI event,
including FIFO R/W, will enable an internal boot oscillator and automatically move the part to SPI active state. After
an SPI event the host will need to re-command the device back to standby through the “Change State” API
command to achieve the 40 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the
interrupt registers must be read to achieve the minimum current consumption of this mode.
3.3.4. Sleep State
Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled. The
source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically calibrated or a
32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an
internal boot oscillator and automatically move the part to SPI active mode. After an SPI event the host will need to
re-command the device back to sleep. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers
must be read to achieve the minimum current consumption of this mode.
3.3.5. SPI Active State
In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either standby or
sleep the device will not automatically return to these states. A “Change State” API command will be required to
return to either the standby or sleep modes.
3.3.6. Ready State
Ready state is designed to give a fast transition time to TX or RX state with reasonable current consumption. In this
mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating
the crystal start-up time.
3.3.7. TX State
The TX state may be entered from any of the state with the “Start TX” or “Change State” API commands. A built-in
sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to
ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.
1. Enable internal LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
Table 11. POR Timing
Variable Description Min Typ Max Units
tPORH High time for VDD to fully settle POR circuit 10 ms
tPORL Low time for VDD to enable POR 10 ms
VRRH Voltage for successful POR 90% x Vdd V
VRRL Starting Voltage for successful POR 0150mV
tSR Slew rate of VDD for successful POR 1ms