Silicon Laboratories Si4432 User manual

Preliminary Rev. 0.2 10/08 Copyright © 2008 by Silicon Laboratories Si4432
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si4432
Si4432 ISM TRANSCEIVER
Features
Applications
Description
Silicon Laboratories’ Si4432 highly integrated, single chip wireless ISM
transceiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes
a complete line of transmitters, receivers, and transceivers allowing the RF
system designer to choose the optimal wireless part for their application.
The Si4432 offers advanced radio features including continuous frequency
coverage from 240–930 MHz and adjustable output power of up to +20 dBm. The
Si4432’s high level of integration offers reduced BOM cost while simplifying the
overall system design. The extremely low receive sensitivity (–118 dBm) coupled
with industry leading +20 dBm output power ensures extended range and
improved link performance. Built-in antenna diversity and support for frequency
hopping can be used to further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble
detection reduce overall current consumption and allow the use of lower-cost
system MCUs. An integrated temperature sensor, general purpose ADC, power-
on-reset (POR), and GPIOs further reduce overall system cost and size.
The Si4432’s digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased performance. This digital architecture simplifies system design while
allowing for the use of lower-end MCUs. The direct digital transmit modulation and
automatic PA power ramping ensure precise transmit modulation and reduced
spectral spreading ensuring compliance with FCC and ETSI regulations.
Frequency Range = 240–930 MHz
Sensitivity = –118 dBm
+20 dBm Max Output Power
Configurable +11 to +20 dBm
Low Power Consumption
18.5 mA receive
27 mA @ +11 dBm
Data Rate = 1 to 128 kbps
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-on-radio
Auto-frequency calibration (AFC)
Antenna diversity & TR switch control
Configurable packet structure
Preamble detector
TX & RX 64 byte FIFOs
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
FSK, GFSK, and OOK modulation
Low BOM
Power-on-reset (POR)
Remote control
Home security & alarm
Teleme tr y
Personal data logging
Toy control
Tire Pressure monitoring
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
Patents pending
Ordering Information:
See page 162.
Pin Assignments
VDD_RF 1
2
3
4
15
14
13
12
6789
19 18 1720
TX
RXp
RXn
SCLK
SDI
SDO
VDD_DIG
ADC_REF
GPIO_0 GPIO_1 GPIO_2
XIN XOUT SDN nIRQ
Metal
Paddle
511VR_IF GND_DIG
10
16
VDR nSEL
Si4432

Si4432
2 Preliminary Rev. 0.2
Functional Block Diagram
LPF CP
Delta Sigma
Modulator
N
LNA
Mixers PGA
AGC Control
PA
VCO
SPI, & Controller
Digital Logic
PFD
PWR_CTRL
TX
RFn
PA_RAMP
PWR_CTRL
PA_RAMP
GPIO_2 GPIO_1
TXMOD
Xout
Xin
Digital Modem
Digital LDO
RC 32K OSC
30M XTAL
OSC
RF LDO
IF LDO
VCO LDO PLL LDO
BIAS
SDN
TXRXSW
ANTDIV
Low Power
Digital LDO
POR
Temp
Sensor
VR_DIG
GPIO_0
ADC_REF
VDD_DIG
SDO
SDI
SCLK
VDD_DIG
VR_IF
LBD
nSEL
VDD_RF
GND_DIG
8Bit
ADC
RFp ADC

Si4432
Preliminary Rev. 0.2 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.3. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.4. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.5. PN9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.6. Synchronous vs. Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.7. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.9. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.4. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.5. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.9. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Si4432
4 Preliminary Rev. 0.2
8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
8.10. TX/RX Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.11. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.12. Analog and Digital Test Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.4. Microcontroller Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
13. Pin Descriptions: Si4432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Si4432
Preliminary Rev. 0.2 5
LIST OF FIGURES
Figure 1. +20 dBm Application with Antenna Diversity and FHSS ...........................................17
Figure 2. TX Timing...................................................................................................................19
Figure 3. RX Timing ..................................................................................................................19
Figure 4. SPI Timing..................................................................................................................20
Figure 5. SPI Timing—READ Mode ..........................................................................................21
Figure 6. SPI Timing—Burst Write Mode ..................................................................................21
Figure 7. SPI Timing—Burst Read Mode ..................................................................................21
Figure 8. State Machine Diagram..............................................................................................22
Figure 9. Sensitivity vs. Carrier Frequency Offset.....................................................................30
Figure 10. FSK vs GFSK Spectrums.........................................................................................32
Figure 11. Direct Synchronous Mode Example.........................................................................34
Figure 12. Direct Asynchronous Mode Example .......................................................................34
Figure 13. FIFO Mode Example ................................................................................................34
Figure 14. PLL Synthesizer Block Diagram...............................................................................37
Figure 15. FIFO Thresholds ......................................................................................................39
Figure 16. Packet Structure.......................................................................................................40
Figure 17. Multiple Packets in TX Packet Handler ....................................................................40
Figure 18. Required RX Packet Structure with Packet Handler Disabled .................................41
Figure 19. Multiple Packets in RX Packet Handler....................................................................41
Figure 20. Multiple Packets in RX with CRC or Header Error ...................................................41
Figure 21. Operation of Data Whitening, Manchester Encoding, and CRC ..............................44
Figure 22. POR Glitch Parameters............................................................................................53
Figure 23. General Purpose ADC Architecture .........................................................................55
Figure 24. ADC Differential Input Example—Bridge Sensor .....................................................57
Figure 25. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................58
Figure 26. Temperature Ranges using ADC8 ...........................................................................60
Figure 27. WUT Interrupt and WUT Operation..........................................................................63
Figure 28. Low Duty Cycle Mode ..............................................................................................63
Figure 29. GPIO Usage Examples............................................................................................65
Figure 30. RSSI Value vs. Input Power.....................................................................................67
Figure 31. Split RF I/Os with Separated TX and RX Connectors - Schematic..........................70
Figure 32. Split RF I/Os with Separated TX and RX Connectors - Top ....................................72
Figure 33. Split RF I/Os with Separated TX and RX Connectors - Top Silkscreen................... 72
Figure 34. Split RF I/Os with Separated TX and RX Connectors - Bottom ...............................73
Figure 35. Common TX/RX Connector with RF Switch - Schematic.........................................74
Figure 36. Common TX/RX Connector with RF Switch - Top ...................................................76
Figure 37. Common TX/RX Connector with RF Switch - Top Silkscreen..................................76
Figure 38. Common TX/RX Connector with RF Switch - Bottom ..............................................77
Figure 39. Antenna Diversity Reference Design - Schematic ...................................................78
Figure 40. Antenna Diversity Reference Design - Top..............................................................80
Figure 41. Antenna Diversity Reference Design - Top Silkscreen ............................................80
Figure 42. Antenna Diversity Reference Design - Bottom.........................................................81
Figure 43. Sensitivity vs. Data Rate ..........................................................................................82
Figure 44. Receiver Selectivity..................................................................................................83
Figure 45. TX Output Power vs. VDD voltage...........................................................................84

Si4432
6 Preliminary Rev. 0.2
Figure 46. TX Output Power vs Temperature ...........................................................................84
Figure 47. TX Modulation (40 kbps, 20 kHz Deviation).............................................................85
Figure 48. TX Unmodulated Spectrum (917 MHz) ....................................................................85
Figure 49. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) .................86
Figure 50. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ...........................86
Figure 51. Synthesizer Phase Noise (VCOCURR = 11) ...........................................................87
Figure 52. RX LNA Matching.....................................................................................................88
Figure 53. TX Matching and Filtering for Different Bands .........................................................89
Figure 54. Microcontroller Connection ......................................................................................89
Figure 55. Package Dimensions .............................................................................................163

Si4432
Preliminary Rev. 0.2 7
LIST OF TABLES
Table 1. DC Characteristics .......................................................................................................8
Table 2. Synthesizer AC Electrical Characteristics ....................................................................9
Table 3. Receiver AC Electrical Characteristics........................................................................10
Table 4. Transmitter AC Electrical Characteristics ...................................................................11
Table 5. Auxiliary Block Specifications .....................................................................................12
Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ...................................13
Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ..............................................13
Table 8. Absolute Maximum Ratings ........................................................................................14
Table 9. Operating Modes ........................................................................................................18
Table 10. Serial Interface Timing Parameters ..........................................................................20
Table 11. Operating Modes ......................................................................................................22
Table 12. Frequency Band Selection .......................................................................................27
Table 13. RX Packet Handler Configuration ............................................................................42
Table 14. Packet Handler Registers .........................................................................................43
Table 15. Minimum Receiver Settling Time ..............................................................................45
Table 16. RX Modem Configurations for FSK and GFSK ........................................................47
Table 17. Filter Bandwidth Parameters ....................................................................................49
Table 18. Channel Filter Bandwidth Settings ...........................................................................50
Table 19. ndec[2:0] Settings .....................................................................................................51
Table 20. RX Modem Configuration for OOK with Manchester Disabled .................................52
Table 21. RX Modem Configuration for OOK with Manchester Enabled .................................52
Table 22. POR Parameters ......................................................................................................53
Table 23. Temperature Sensor Range .....................................................................................60
Table 24. Antenna Diversity Control .........................................................................................66
Table 25. Analog Test Bus .......................................................................................................68
Table 26. Internal Digital Signals Available on the Digital Test Bus .........................................69
Table 27. Split RF I/Os Bill of Materials ....................................................................................71
Table 28. Common TX/RX Connector Bill of Materials ............................................................75
Table 29. Antenna Diversity Bill of Materials ............................................................................79
Table 30. Recommended Crystal Parameters .........................................................................88
Table 31. RX Matching for Different Bands ..............................................................................89
Table 32. Register Descriptions ...............................................................................................90
Table 33. Interrupt or Status 1 Bit Set/Clear Description .........................................................95
Table 34. When do the individual Status Bits get Set/Cleared, if not Enabled as an Interrupt? 96
Table 35. Interrupt or Status 2 Bit Set/Clear Description ........................................................98
Table 36. Detailed Description of Status Registers when not Enabled as Interrupts ...............99
Table 37. Internal Digital Signals Available on the Digital Test Bus .......................................136

Si4432
8 Preliminary Rev. 0.2
1. Electrical Specifications
Table 1. DC Characteristics1
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage Range Vdd 1.8 3.0 3.6 V
Power Saving Modes2IShutdown RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF2—10TBDnA
IStandby Low Power Digital Regulator ON (Register values retained)
and Main Digital Regulator, and RC Oscillator OFF2—400TBDnA
ISleep RC Oscillator and Low Power Digital Regulator ON
(Register values retained) and Main Digital Regulator OFF2—800TBDnA
ISensor-LBD Main Digital Regulator and Low Battery Detector ON,
Crystal Oscillator and all other blocks OFF2—1TBDµA
ISensor-TS Main Digital Regulator and Temperature Sensor ON,
Crystal Oscillator and all other blocks OFF2—1TBDµA
IReady Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF. Crystal Oscillator buffer disabled
—600TBDµA
TUNE Mode Current ITune Synthesizer and regulators enabled — 9.5 TBD mA
RX Mode Current IRX —18.5TBDmA
TX Mode Current ITX_+20 txpow[1:0] = 11 (+20 dBm), VDD = 3.3 V — 60 TBD mA
ITX_+11 txpow[1:0] = 00 (+11 dBm), VDD = 3.3 V — 27 TBD mA
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4432
Preliminary Rev. 0.2 9
Table 2. Synthesizer AC Electrical Characteristics1
Parameter Symbol Conditions Min Typ Max Units
Synthesizer Frequency
Range2
FSYNTH-LB Low Band 240 — 480 MHz
FSYNTH-HB High Band 480 — 930 MHz
Synthesizer Frequency
Resolution
FRES-LB Low Band — 156.25 — Hz
FRES-HB High Band — 312.5 — Hz
Reference Frequency fREF fcrystal /3 — 10 — MHz
Reference Frequency
Input Level2
fREF_LV When using reference frequency instead of crystal.
Measured peak-to-peak (VPP)
0.7 — 1.6 V
Synthesizer Settling Time2tLOCK Measured from leaving Ready mode with XOSC
running to any frequency including VCO Calibration
—200TBDµs
Residual FM2FRMS Integrated over 250 kHz bandwidth
(500 Hz lower bound of integration)
—2 4kHz
RMS
Phase Noise2L(fM)F = 10 kHz — –80 TBD dBc/Hz
F = 100 kHz — –90 TBD dBc/Hz
F = 1 MHz — –115 TBD dBc/Hz
F = 10 MHz — –130 TBD dBc/Hz
Spurious Emissions2POB-TX1 < 1 GHz — — –54 dBm
POB-TX2 1–12.75 GHz, non-intentional
radiator
——–54dBm
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4432
10 Preliminary Rev. 0.2
Table 3. Receiver AC Electrical Characteristics1
Parameter Symbol Conditions Min Typ Max Units
RX Frequency
Range2
FSYNTH-LB Low Band 240 — 480 MHz
FSYNTH-HB High Band 480 — 930 MHz
RX Sensitivity PRX_2 (BER < 0.1%)
(2 kbps, GFSK, BT=0.5,
f = 5kHz)
1
—–117TBDdBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT=0.5,
f = 20 kHz)1
— –106 TBD dBm
PRX_100 (BER < 0.1%)
(100 kbps, GFSK, BT=0.5,
f = 50 kHz)2
— –102 TBD dBm
PRX_OOK (BER < 0.1%)
(4.8 kbps, OOK)1
—–110TBDdBm
RX Bandwidth BW 2.6 — 620 kHz
Residual BER
Performance2
PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm
Input Intercept Point,
3rd Order2
IIP3RX f1= 915 MHz, f2= 915 MHz,
P1= P2= –40 dBm
— –20 TBD dBm
LNA Input Impedance RIN-RX Unmatched, measured differentially
across RX input pins
— 250 — 
RSSI Resolution RESRSSI — ±0.5 — dB
1-Ch Offset Selectivity2
(BER < 0.1%)
C/I1-CH Desired Ref Signal 3 dB above sensitivity.
Interferer and desired modulated with
40 kbps F = 20 kHz GFSK with BT = 0.5,
channel spacing = 150 kHz
— –31 TBD dB
2-Ch Offset Selectivity2
(BER < 0.1%)
C/I2-CH — –35 TBD dB
3-Ch Offset Selectivity2
(BER < 0.1%)
C/I3-CH — –40 TBD dB
Blocking at 1 MHz21MBLOCK Desired Ref Signal 3 dB above sensitivity.
Interferer and desired modulated with
40 kbps F = 20 kHz GFSK with BT = 0.5
— –52 TBD dB
Blocking at 4 MHz24MBLOCK — –56 TBD dB
Blocking at 8 MHz28MBLOCK — –63 TBD dB
Image Rejection ImREJ IF=937 kHz — –30 — dB
Spurious Emissions2POB_RX1 Measured at RX pins
(LO feed through)
——–54dBm
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4432
Preliminary Rev. 0.2 11
Table 4. Transmitter AC Electrical Characteristics1
Parameter Symbol Conditions Min Typ Max Units
TX Frequency
Range2
FSYNTH-LB Low Band 240 — 480 MHz
FSYNTH-HB High Band 480 — 930
FSK Modulation Data Rate2DRFSK 1—128kbps
OOK Modulation Data
Rate2
DROOK 1.2 — 40 kbps
Modulation Deviation2Δf ±0.625 ±320 kHz
Modulation Deviation
Resolution
ΔfRES —0.625— kHz
Output Power Range2PTX Tested at 915 MHz, txpow[1:0] = 11 +11 — +20 dBm
TX RF Output Steps2PRF_OUT TXPWR[1:0] = 00 thru 11 TBD 3 TBD dB
TX RF Output Level
Variation vs. Voltage2
PRF_V Measured from VDD=3.6 V to
VDD=1.8 V
—2TBDdB
TX RF Output Level2
Variation vs. Temperature
PRF_TEMP –40 to +85 C—2TBDdB
TX RF Output Level
Variation vs. Frequency2
PRF_FREQ Measured across any one
frequency band
—1TBDdB
Transmit Modulation
Filtering
B*T Gaussian Filtering Bandwith Time
Product
—0.5—
Spurious Emissions2POB-TX1 POUT =11dBm,
Frequencies <1 GHz
——–54dBm
POB-TX2 1–12.75 GHz, excluding harmonics — — –54 dBm
Harmonics2P2HARM Using Reference Design TX Matching
Network and Filter with Max Output Power
(20 dBm). Harmonics reduce linearly with
output power
——–42dBm
P3HARM ——–42dBm
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4432
12 Preliminary Rev. 0.2
Table 5. Auxiliary Block Specifications1
Parameter Symbol Conditions Min Typ Max Units
Temperature Sensor
Accuracy2
TSAWhen calibrated using temp
sensor offset register
—0.5—°C
Temperature Sensor
Sensitivity2
TSS—5—mV/°C
Low Battery Detector
Resolution2
LBDRES —50—mV
Low Battery Detector
Conversion Time2
LBDCT —250—µs
Microcontroller Clock
Output Frequency2
MC Configurable to 30 MHz,
15 MHz, 10 MHz, 4 MHz,
3MHz,2MHz,1MHz,or
32.768 kHz
32.768K — 30M Hz
General Purpose ADC
Accuracy
ADCENB —8—bit
General Purpose ADC
Resolution
ADCRES —4—mV
Temp Sensor & General
Purpose ADC Conversion
Time
ADCCT — 305 — µsec
30 MHz XTAL Start-Up time t30M —1—ms
30 MHz XTAL Cap
Resolution
30MRES —97—fF
32 kHz XTAL Start-Up Time t32k —6—sec
32 kHz XTAL Accuracy 32KRES — 100 — ppm
32 kHz RC OSC Accuracy 32KRCRES — 2500 — ppm
POR Reset Time tPOR —16—ms
Software Reset Time tsoft —100—µs
Notes:
1. All specification guaranteed by production test unless otherwise noted.
2. Guaranteed by qualification.

Si4432
Preliminary Rev. 0.2 13
Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter Symbol Conditions Min Typ Max Units
Rise Time TRISE 0.1 x VDD to 0.9 x VDD, CL= 5 pF — — 8 ns
Fall Time TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF — — 8 ns
Input Capacitance CIN ——1pF
Logic High Level Input Voltage VIH VDD –0.6 — — V
Logic Low Level Input Voltage VIL —0.6 V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Logic High Level Output
Voltage
VOH IOH<1 mA source, VDD=1.8 V VDD –0.6 — — V
Logic Low Level Output Voltage VOL IOL<1 mA sink, VDD=1.8 V — — 0.6 V
Note: All specification guaranteed by production test unless otherwise noted.
Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter Symbol Conditions Min Typ Max Units
Rise Time TRISE 0.1 x VDD to 0.9 x VDD,
CL= 10 pF, DRV<1:0>=HH
——8ns
Fall Time TFALL 0.9 x VDD to 0.1 x VDD,
CL= 10 pF, DRV<1:0>=HH
——8ns
Input Capacitance CIN ——1pF
Logic High Level Input Voltage VIH VDD –0.6 — V
Logic Low Level Input Voltage VIL ——0.6V
Input Current IIN 0<VIN< VDD –100 — 100 nA
Input Current If Pullup is Activated IINP VIL=0 V 5 — 25 µA
Maximum Output Current IOmaxLL DRV<1:0>=LL 0.1 0.5 0.8 mA
IOmaxLH DRV<1:0>=LH 0.9 2.3 3.5 mA
IOmaxHL DRV<1:0>=HL 1.5 3.1 4.8 mA
IOmaxHH DRV<1:0>=HH 1.8 3.6 5.4 mA
Logic High Level Output Voltage VOH IOH< IOmax source,
VDD=1.8 V
VDD –0.6 — — V
Logic Low Level Output Voltage VOL IOL< IOmax sink,
VDD=1.8 V
——0.6V
Note: All specification guaranteed by production test unless otherwise noted.

Si4432
14 Preliminary Rev. 0.2
Table 8. Absolute Maximum Ratings
Parameter Value Unit
VDD to GND –0.3, +3.6 V
VDD to GND on TX Output Pin –0.3, +8.0 V
Voltage on Digital Control Inputs –0.3, VDD + 0.3 V
Voltage on Analog Inputs –0.3, VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA–40 to +85 C
Thermal Impedance ΘJA 30 C/W
Junction Temperature TJ+125 C
Storage Temperature Range TSTG –55 to +125 C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Caution: ESD sensitive device.
Power Amplifier may be damaged if switched on without proper load connected.

Si4432
Preliminary Rev. 0.2 15
1.1. Definition of Test Conditions
Production Test Conditions:
TA= +25 °C
VDD = +3.3 VDC
External reference signal (XIN) = 1.0 VPP at 30 MHz, centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si4432 (not the RF module)
Extreme Test Conditions:
TA= –40 to +85 °C
VDD = +1.8 to +3.6 VDC
External reference signal (XIN) = 0.7 to 1.6 VPP at 30 MHz centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si4432 (not the RF module)
Test Notes:
All electrical parameters with Min/Max values are guaranteed by one (or more) of the following test methods.
Electrical parameters shown with only Typical values are not guaranteed.
Guaranteed by design and/or simulation but not tested.
Guaranteed by Engineering Qualification testing at Extreme Test Conditions.
Guaranteed by 100% Production Test Screening at Production Test Conditions.

Si4432
16 Preliminary Rev. 0.2
2. Functional Description
The Si4432 is a 100% CMOS ISM wireless transceiver
with continuous frequency tuning over the complete
240–930 MHz band. The wide operating voltage range
of 1.8–3.6 V and low current consumption makes the
Si4432 and ideal solution for battery powered
applications.
The Si4432 operates as a time division duplexing (TDD)
transceiver where the device alternately transmits and
receives data packets. The receiver uses a single-
conversion, image-reject mixer to downconvert the 2-
level FSK/GFSK/OOK modulated receive signal to a low
IF frequency. Following a programmable gain amplifier
(PGA) the signal is converted to the digital domain by a
high performance  ADC allowing filtering,
demodulation, slicing, error correction, and packet
handling to be performed in the built-in DSP increasing
the receiver’s performance and flexibility versus analog
based architectures. The demodulated signal is then
output to the system MCU through a programmable
GPIO or via the standard SPI bus by reading the 64-
byte RX FIFO.
A single high precision local oscillator (LO) is used for
both transmit and receive modes since the transmitter
and receiver do not operate at the same time. The LO is
generated by an integrated VCO and  Fractional-N
PLL synthesizer. The synthesizer is designed to support
configurable data rates, output frequency, frequency
deviation, and Gaussian filtering at any frequency
between 240–930 MHz. The transmit FSK data is
modulated directly into the  data stream and can be
shaped by a Gaussian low-pass filter to reduce
unwanted spectral content.
The PA output power can be configured between +11
and +20 dBm in 3 dB steps. The PA is single-ended to
allow for easy antenna matching and low BOM cost.
The PA incorporates automatic ramp-up and ramp-
down control to reduce unwanted spectral spreading.
This Si4432 supports frequency hopping, TX/RX switch
control, and antenna diversity switch control to extend
the link range and improve performance. Antenna
diversity is completely integrated into the Si4432 and
can improve the system link budget by 8–10 dB
(according to published papers on Antenna Diversity)
resulting in substantial range increases depending on
the environmental conditions. The +20 dBm power
amplifier can also be used to compensate for the
reduced performance of a lower cost antenna or
antenna with size constraints due to a small form-factor.
Competing solutions require large and expensive
external PAs to achieve comparable performance.
The Si4432 is designed to work with a microcontroller,
crystal, and a few passives to create a very low cost
system as shown Figure 1. Voltage regulators are
integrated on-chip which allow for a wide range of
operating supply voltage conditions from +1.8 to +3.6 V.
A standard 3 or 4-pin SPI bus is used to communicate
with the microcontroller. Three configurable general
purpose I/Os are available for use to tailor towards the
needs of the system. A more complete list of the
available GPIO functions is shown in "8. Auxiliary
Functions" on page 53 but just to name a few,
microcontroller clock output, Antenna Diversity, TRSW
control, POR, and specific interrupts. A limited number
of passive components are needed to match the LNA
and PA; refer to "9. Reference Design" on page 70 for
the required component values at different frequency
ranges.
The application shown in Figure 1 is designed for a
system with Antenna Diversity. The Antenna Diversity
Control Algorithm is completely integrated into the chip
and is discussed further in "8.9. Antenna-Diversity" on
page 66.
For a simpler application example not using Antenna
Diversity see the "9. Reference Design" on page 70.

Si4432
Preliminary Rev. 0.2 17
Figure 1. +20 dBm Application with Antenna Diversity and FHSS
X1
30MHz
supply voltage
microcontroller
VDD
VSS
GP1
GP2
GP3
GP4
100n
C7
100p
C8
C1
C8
L1
L3 L2
C6
C3 C2
1u
1u
R1, L1-L5 and C1-C4 values depend on frequency band,
antenna impedance, output power and supply voltage range.
Programmable load capacitors for X1 are integrated.
VDD_RF SCLK
19 18 17 16
1
2
3
4
15
14
13
7 8 9
10
SDI
SDO
VDD_D
RXn
TX
RXp
GPIO0 GPIO1
VR_DIG
nIRQ
SDN
XOUT
nSEL
GPIO2
5
VR_IF
6
ADC_REF
GND_D
20
XIN
11
12
C10
GP5
1u
C9
1u
L4
C4
C5
Si4432
TR & ANT-DIV
Switch

Si4432
18 Preliminary Rev. 0.2
2.1. Operating Modes
The Si4432 provides several modes of operation which can be used to optimize the power consumption of the
device application. Depending upon the system communication protocol, the optimal trade-off between the radio
wake time and power consumption can be achieved.
Table 9 summarizes the modes of operation of the Si4432. In general, any given mode of operation may be
classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in
each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the
appropriate commands over the SPI in order to optimize the average current consumption. An “X” in any cell
means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF,
without noticeably affecting the current consumption. The SPI circuit block includes the SPI interface and the
register space. The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal
oscillator, and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and
low-battery detector.
Table 9. Operating Modes
Mode
Name Circuit Blocks
Digital LDO SPI 32 kHz OSC AUX 30 MHz
XTAL PLL PA RX IVDD
Shutdown OFF (Register
contents lost)
OFF OFF OFF OFF OFF OFF OFF 10 nA
Standby ON (Register
contents
retained)
ON OFF OFF OFF OFF OFF OFF 400 nA
Sleep ON ON X OFF OFF OFF OFF 800 nA
Sensor ON X ON OFF OFF OFF OFF 1 µA
Ready ON X X ON OFF OFF OFF 600 µA
Tuning ON X X ON ON OFF OFF 9.5 mA
Transmit ON X X ON ON ON OFF 27 mA*
Receive ON X X ON ON OFF ON 18.5 mA
*Note: 27 mA at +11 dBm.

Si4432
Preliminary Rev. 0.2 19
Figure 2. TX Timing
Figure 3. RX Timing
TX Packet
XTAL Settling
Time
PLL T0
PLL CAL
PLLTS
~1ms
Configurable 0-70us,Default = 20us
45us, May be skipped
PRE PA RAMP
PA RAMP UP
TXMOD DELAY
PA RAMP DOWN
Configurable 0-310us, Recommend 100us
6us, Fixed
Configurable 5-20us, Recommend 5us
1.5Bits @DR
Configurable 5-20us, Recommend 5us
RX Packet
XTAL Settling
Time
PLL T0
PLL CAL
PLLTS
~1ms
Configurable 0-70us, Default =20us
45us, May be skipped
Configurable 0-310us, Recommend 100us

Si4432
20 Preliminary Rev. 0.2
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4432 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU
can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA),
as demonstrated in Figure 4. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control
registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it
signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are
latched into the Si4432 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 10.
The SCLK rate is flexible with a maximum rate of 10 MHz.
Figure 4. SPI Timing
To read back data from the Si4432, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight positive
edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the
selected register will be available on the SDO output pin. The READ function is shown in Figure 5. After the READ
function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit
clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Table 10. Serial Interface Timing Parameters
Symbol Parameter Min (nsec) Diagram
tCH Clock high time 40
tCL Clock low time 40
tDS Data setup time 20
tDH Data hold time 20
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50
tSS Select setup time 20
tSH Select hold time 50
tSW Select high period 80
nSEL
SCLK
SDI
MSB
LSB
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1
D0
A4
xx
xx
A3 RW A7A6
A5
RW
Data
Address
SDI
SCLK
SDO
nSEL
tCL tCH
t
DS tDH tDD
tSS
t
E
N
tSH
t
DE
t
SW