Skyworks Si5341 User manual

Si5341, Si5340 Rev D Family Reference
Manual
Ultra Low Jitter, Any-Frequency, Any Output Clock Generator:
Si5341, Si5340 Rev D Family Reference Manual
The Si5341/40 Clock Generators combine MultiSynth™ technologies to enable any-
frequency clock generation for applications that require the highest level of jitter
performance. These devices are programmable via a serial interface with in-circuit
programmable nonvolatile memory (NVM) ensuring power up with a known frequency
configuration.
RELATED DOCUMENTS
• Si5341/0 Data Sheet
• Si5341/0 Device Errata
• Si5341/0 -EVB User Guide
• Si5341/0 -EVB Schematics, BOM &
Layout
• IBIS models
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Table of Contents
1. Overview .................................5
1.1 Work Flow Expectations with ClockBuilder Pro and the Register Map ...........5
1.2 Family Product Comparison .........................6
1.3 Available Software Tools and Support ......................7
2. Functional Description............................8
2.1 Dividers ................................9
3. Powerup and Initialization ......................... 12
3.1 Reset and Initialization ...........................12
3.1.1 Power Supply Sequencing ........................12
3.2 NVM Programming ............................13
4. Clock Inputs............................... 15
4.1 Inputs on XA/XB .............................15
4.1.1 Crystal on XA/XB............................15
4.1.2 Clock Input on XA/XB ..........................16
4.2 Clock Inputs on IN2, IN1, IN0 .........................17
4.3 Unused Inputs ..............................17
4.4 Reference Input Selection (IN0, IN1, IN2, XA/XB) ..................18
4.5 Fault Monitoring .............................19
4.5.1 Status Indicators ............................20
4.5.2 Interrupt Pin (INTRb) ..........................21
5. Output Clocks .............................. 22
5.1 Outputs ................................22
5.2 Performance Guidelines for Outputs .......................22
5.3 Output Signal Format ............................23
5.3.1 Differential Output Terminations .......................24
5.3.2 Differential Amplitude Controls .......................24
5.3.3 Output Driver Settings for LVPECL, LVDS, HCSL, and CML .............25
5.3.4 LVCMOS Output Terminations .......................26
5.3.5 LVCMOS Output Impedance and Drive Strength Selection ..............27
5.3.6 LVCMOS Output Signal Swing .......................27
5.3.7 LVCMOS Output Polarity .........................28
5.3.8 Output Enable/Disable ..........................29
5.3.9 Output Driver State When Disabled .....................30
5.3.10 Synchronous/Asynchronous Output Disable Feature ...............30
5.4 Output Crosspoint .............................31
5.5 Zero Delay Mode .............................32
6. Digitally Controlled Oscillator (DCO) Modes ................... 34
6.1 Using the N Dividers for DCO Applications ....................34
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6.1.1 DCO with Frequency Increment/Decrement Pins/Bits ...............34
6.1.2 DCO with Direct Register Writes ......................34
6.2 Using the M Divider for DCO Applications .....................34
7. Dynamic PLL Changes........................... 35
7.1 Revisions B and A .............................35
7.2 Revision D ...............................35
7.3 Dynamic Changes to Output Frequencies without Changing PLL Settings ..........36
7.4 Dynamic Changes to Output Frequencies while Changing PLL Settings Using a CBPro Register
Map .................................36
8. Serial Interface.............................. 37
8.1 I2C Interface ...............................38
8.2 SPI Interface...............................40
9. Field Programming ............................ 44
10. Recommended Crystals and External Oscillators ................ 45
11. Crystal and Device Circuit Layout Recommendations............... 46
11.1 64-Pin QFN Si5341 Layout Recommendations ..................46
11.1.1 Si5341 Applications without a Crystal ....................46
11.1.2 Si5341 Crystal Layout Guidelines ......................47
11.1.3 Output Clocks ............................51
11.2 44-Pin QFN Si5340 Layout Recommendations ...................52
11.2.1 Si5340 Applications without a Crystal as the Reference Clock ............52
11.2.2 Si5340 Crystal Guidelines ........................53
12. Power Management ........................... 56
12.1 Power Management Features ........................56
12.2 Power Supply Recommendations .......................56
12.3 Grounding Vias .............................56
12.4 Power Supply Sequencing .........................57
13. Base vs. Factory Preprogrammed Devices ................... 58
13.1 “Base” Devices (Also Known as “Blank” Devices) ..................58
13.2 Factory Preprogrammed (Custom OPN) Devices ..................58
14. Register Map .............................. 59
14.1 Register Map Overview and Default Settings Values .................59
14.2 Si5341 Register Map ...........................59
14.2.1 Page 0 Registers Si5341.........................60
14.2.2 Page 1 Registers Si5341.........................69
14.2.3 Page 2 Registers Si5341.........................73
14.2.4 Page 3 Registers Si5341.........................79
14.2.5 Page 9 Registers Si5341.........................82
14.2.6 Page A Registers Si5341 ........................83
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14.2.7 Page B Registers Si5341 ........................84
14.3 Si5340 Registers .............................84
14.3.1 Page 0 Registers Si5340.........................85
14.3.2 Page 1 Registers Si5340.........................94
14.3.3 Page 2 Registers Si5340.........................97
14.3.4 Page 3 Registers Si5340........................103
14.3.5 Page 9 Registers Si5340........................106
14.3.6 Page A Registers Si5340 .......................107
14.3.7 Page B Registers Si5340 .......................108
15. Appendix—Setting the Differential Output Driver to Non-Standard Amplitudes .....109
16. Revision History.............................110
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1. Overview
Using patented MultiSynth™ technology, the Si5341/40 generates up to 10 unique clock frequencies, each with 0 ppm frequency syn-
thesis error. Each output clock has an independent VDDO reference and selectable signal format, simplifying format/level translation.
The loop filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions.The Si5341/40
is ideally suited for simplifying clock tree design by minimizing the number of timing components required. The Si5341/40 supports
factory or in-circuit programmable non-volatile memory, enabling the device to power up in a user-specified configuration. The default
configuration may be overwritten at any time by reprogramming the device via I2C/SPI.
1.1 Work Flow Expectations with ClockBuilder Pro and the Register Map
This reference manual is to be used to describe all the functions and features of the parts in the product family with register map
details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to
provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement
a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and
other operating settings are supported by the devices. However, describing all the possible changes are not a primary purpose of this
document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to
implement the most common, real-time frequency plan changes.
The primary purpose of the software is that it saves having to understand all the complexities of the device. The software abstracts the
details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for
the end application. The software walks the user through each step, with explanations about each configuration step in the process to
explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final
configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order
a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the
settings in the register map described in this document.
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1.2 Family Product Comparison
The following table lists a comparison of the different family members.
Table 1.1. Product Selection Guide
Part Number Number of Inputs Number of
Fractional Dividers Number of Outputs Package Type
Si5341 4 5 10 64-pin QFN
Si5340 4 4 4 44-pin QFN
Si5341/40
FB_IN
IN0
IN_SEL[1:0]
IN1
IN2
XB
XA
XTAL
OSC
Multi
Synth OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Si5340 Si5341
PLL
NVM
I2C/ SPI
Control/
Status
Figure 1.1. Block Diagram Si5341/40
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1.3 Available Software Tools and Support
ClockBuilder Pro is a software tool that is used for the Si5341/40 family and other product families, capable of configuring the timing
chip in an intuitive friendly step by step process. The software abstracts the details from the user to allow focus on the high level input
and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through
each step, with explanations about each configuration step in the process to explain the different options available. The software will
restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to a device
or written to the EVB and a custom part number can be created. ClockBuilder Pro integrates all the datasheets, application notes and
information that might be helpful in one environment. It is intended that customers will use the software tool for the proper configuration
of the device. Register map descriptions are given in the document should not be the only source of information for programming the
device. The complexity of the algorithms is embedded in the software tool.
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2. Functional Description
The Si5341/40 uses next generation MultiSynth™ technology to offer the industry’s most frequency-flexible, high performance clock
generator. The PLL locks to either an external crystal (XA/XB) or to an external input on XAXB, IN0, IN1 or IN2. The input frequency
(crystal or external input) is multiplied by the DSPLL and divided by the MultiSynth™ stage (N divider) and R divider to any frequency
in the range of 100 Hz to 712.5 MHz per output. The phase-locked loop is fully contained and does not require external loop
filter components to operate. Its function is to phase lock to the selected input and provide a common reference to all the output
MultiSynth high-performance fractional dividers (N). The high-resolution fractional MultiSynth™ dividers enables true any-frequency
input to any-frequency on any of the outputs. A crosspoint mux connects any of the MultiSynth divided frequencies to any of the
outputs drivers. Additional output integer dividers (R) provide further frequency division if required. The frequency configuration of
the device is programmed by setting the input dividers (P), the DSPLL feedback fractional divider (M_NUM/M_DEN), the MultiSynth
fractional dividers (N_NUM/N_DEN), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro configuration utility determines
the optimum divider values for any desired input and output frequency plan.
The output drivers offer flexible output formats which are independently configurable on each of the outputs. This clock generator is
fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile memory. The block diagram for the
Si5341 is shown in Figure 2.1 Si5341 Detailed Block Diagram on page 10, and the block diagram for the Si5340 is shown in Figure
2.2 Si5340 Detailed Block Diagram on page 11.
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2.1 Dividers
There are five divider classes within the Si5341/40. See Figure 2.2 Si5340 Detailed Block Diagram on page 11 for a block diagram
that shows all of these dividers.
• 1. Wide range input dividers Pfb, P2, P1, P0
• Only integer divider values
• Range is from 1 to 216 – 1
• Since the input to the phase detector needs to be > 10 MHz, the practical range is limited to ~75 on the high side.
• Each divider has an update bit that must be written to cause a newly written divider value to take effect.
2. Narrow range input divider Pxaxb
• Only divides by 1, 2, 4, 8
3. Feedback M divider
• Ultra low jitter in fractional and integer modes
• MultiSynth divider
• Integer or fractional divide values
• 44 bit numerator, 32 bit denominator
• Practical range limited by phase detector range of 10–120 MHz and VCO range of 13500–14256 MHz
• This divider has an update bit that must be written to cause a newly written divider value to take effect.
4. Output N dividers
• Ultra low jitter in fractional and integer modes
• MultiSynth divider
• Integer or fractional divide values
• 44 bit numerator, 32 bit denominator
• Min value is 10
• Maximum value is 212 – 1
• Each N divider has an update bit that must be written to cause a newly written divider value to take effect. In addition there is
a global update bit that when written updates all N dividers.
5. Output R divider
• Only even integer divide values
• Min value is 2
• Maximum value is 225 – 2
Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 6. Digitally Controlled
Oscillator (DCO) Modes for more information and block diagrams on DCO mode.
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VDD
VDDA
3
SDA/SDIO
A1/SDO
SCLK
A0/CS
I2C_SEL
SPI/
I2CNVM
RST
Zero Delay
Mode
FB_IN
FB_IN
OE
Si5341
Generator
Clock
÷R0
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
÷R1
OUT0
VDDO0
OUT0
OUT2
VDDO2
OUT2
OUT3
VDDO3
OUT3
OUT4
VDDO4
OUT4
OUT5
VDDO5
OUT5
OUT6
VDDO6
OUT6
OUT7
VDDO7
OUT7
OUT8
VDDO8
OUT8
OUT9
VDDO9
OUT9
OUT1
VDDO1
OUT1
÷Pfb
LPF
PD
÷Mn
Md
PLL
IN_SEL[1:0]
XA
XB
25MHz, 48-
54MHz
XTAL
OSC
÷P2
÷P1
÷P0
IN0
IN0
IN1
IN1
IN2
IN2
FDEC
FINC
Frequency
Control
÷N0n
N0d t0
÷N2n
N2d
÷N3n
N3d
÷N4n
N4d
t2
t3
t4
÷N1n
N1d t1
MultiSynth
SYNC
Dividers/
Drivers
Status
Monitors
LOL
INTR
÷Pxaxb
Figure 2.1. Si5341 Detailed Block Diagram
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RST
OE
Si5340
÷N0n
N0d t0
÷N2n
N2d
÷N3n
N3d
t2
t3
÷N1n
N1d t1
IN_SEL[1:0]
XA
XB
IN0
IN0
IN1
IN1
IN2
IN2
LPF
PD
PLL
÷
Mn
Md
Zero Delay
Mode
FB_IN
FB_IN
LOL
INTR
LOSXAB
SDA/SDIO
A1/SDO
SCLK
A0/CS
I2C_SEL
SPI/
I2CNVM
Status
Monitors
Generator
Clock
÷P0
÷P1
÷P2
÷Pfb
MultiSynth
÷R0
÷R2
÷R3
÷R1
OUT0
VDDO0
OUT0
OUT2
VDDO2
OUT2
OUT3
VDDO3
OUT3
OUT1
VDDO1
OUT1
Dividers/
Drivers
25MHz, 48-
54MHz
XTAL
OSC
÷Pxaxb
VDD
VDDA
3
Figure 2.2. Si5340 Detailed Block Diagram
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3. Powerup and Initialization
The following figure shows the powerup and initialization sequence.
Power-Up
Serial interface
ready
RST
pin asserted
Hard Reset
bit asserted
Initialization
NVM download
Soft Reset
bit asserted
Figure 3.1. Power-Up and Initialization
3.1 Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data
from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this
initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A
hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be
restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit.
A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Table 3.1. Reset Registers
Register Name
Hex Address [Bit Field]
Function
Si5341 Si5340
HARD_RST 001E[1] 001E[1] Performs the same function as power cycling the device. All regis-
ters will be restored to their default values.
SOFT_RST 001C[0] 001C[0] Performs a soft reset. Resets the device while it does not re-
download the register configuration from NVM.
The Si541/40 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to
generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power
supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins.
3.1.1 Power Supply Sequencing
If the output clocks do not need to have a specific phase/delay relationship between them the timing of the power supplies coming up
to full voltage is irrelevant. However, if the phase/delay of any output clock to any other output clock is important, then the VDDO of the
relevant clock output must come up to full voltage before VDD and VDDA voltages are applied. See . Voltage can always be applied to
the VDDS pin regardless of any output clock alignment.
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3.2 NVM Programming
Devices have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks.
There are three NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). Two
user NVM banks remain; therefore, the device NVM can be re-burned in the field up to two times. Factory NVM cannot be modified, and
contains fixed configuration information for the device.
The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how
many banks, if any, are available to burn. The following table describes possible values:
Table 3.2. NVM Bank Burning Values
Active NVM BANK Value (Deci-
mal)
Number of User Banks Burned Number of User Banks Available to Burn
3 (factory state) 1 2
15 2 1
63 3 0
Note: While polling DEVICE_READY during the procedure below, the following conditions must be met to ensure the correct values are
written into the NVM:
• VDD and VDDA power must both be stable throughout the process.
• No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01.
DEVICE_READY is available on every register page, so no page change is needed to read it.
• Only the DEVICE_READY register (0xFE) should be read during this time.
The procedure for writing registers into NVM is as follows:
1. Write registers as needed for desired device operation. Verify device operation to ensure the device is configured correctly before
preceeding. Do not skip this important step.
2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the
NVM bank.
3. Write 0xC7 to NVM_WRITE register. This starts the internal NVM burn sequence, writing NVM from the internal registers. Do not
access ANY other registers than DEVICE_READY during the NVM burn process. Doing so may corrupt the NVM burn in progress.
4. Poll DEVICE_READY until DEVICE_READY=0x0F (waiting for completion of NVM burn sequence).
5. Set NVM_READ_BANK 0x00E4[0]=1. This will download the NVM contents back into non-volatile memory (registers).
6. Poll DEVICE_READY until DEVICE_READY=0x0F (waiting for NVM download to complete).
7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it
will be a 3. After NVM_WRITE, the value will be 15.
Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device
to generate a POR. All of these actions will load the new NVM contents back into the device registers.
The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your
PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device
configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.
Table 3.3. NVM Programming Registers
Register Name Hex Address
[Bit Field]
Function
ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.
NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.
NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.
DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when
value = 0x0F.
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Warning: Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt
the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the
PAGE register.
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4. Clock Inputs
The PLL in the Si5341/40 requires a clock at the XAXB or IN2, 1, 0 input pins or a clock from a crystal connected across the XAXB
pins.
4.1 Inputs on XA/XB
4.1.1 Crystal on XA/XB
An external standard crystal (XTAL) is connected to XA/XB when this input is configured as a crystal oscillator. A crystal frequency of
25 MHz can be used although crystals in the frequency range of 48 MHz to 54 MHz are recommended for the best jitter performance.
Recommended crystals are listed below. The Si5341/40 includes a built-in XTAL load capacitance (CL) of 8 pF, but crystals with CL
specifications as high as 18 pF can also be used. When using crystals with CL specs higher than 8 pf it is not generally recommended
to use external capacitors from XA/XB to ground to increase the crystal load capacitance. Rather the frequency offset due to CL
mismatch can be adjusted using the XAXB_FREQ_OFFSET word which allows frequency adjustments of up to ±1000 ppm. See
11. Crystal and Device Circuit Layout Recommendations for the PCB layout guidelines.
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4.1.2 Clock Input on XA/XB
An external clock can also be input on the XA/XB pins. Selection between the external crystal or clock is controlled by register
configuration. The internal crystal load capacitors (CL) are disabled in external clock mode. Because the input buffer at XA/XB is a
lower noise buffer than the buffers on IN2,1,0, a very clean input clock at XA/XB, such as a very high quality TCXO or XO, will, in some
cases, produce lower output clock jitter than the same input at IN2,1,0. If the XAXB input is unused and powered down then the XA
and XB inputs can be left floating. Note that ClockBuilder Pro will power down the XAXB input if it is selected as “unused”. If XAXB is
powered up but no input is applied then the XA input should be left floating and the XB input must be connected directly to ground. Both
a single-ended or a differential clock can be connected to the XA/XB pins as shown in the following figure:
50
Differential Connection
2xCL
2xCL
XB
XA
2xCL
2xCL
XB
XA
Single-ended XO Connection
Crystal Connection
OSC
XB
XA
XTA
L
2xCL
2xCL
Si5341/40
Si5341/40 Si5341/40
Note: 2.0 Vpp_se max
XO with Clipped Sine
Wave Output
2xCL
2xCL
XB
XA
OSC
Si5341/40
Note: 2.0 Vpp_se max
CMOS/XO
Output
R2
R1
XO VDD R1 R2
3.3 V 523 Ohms
2.5 V
1.8 V
50
0.1 µf
0.1 µf
0.1 µf
0.1 µf
0.1 µf
0.1 µf
0.1 µf
Single-ended Connection
Note: 2.5 Vpp diff max
X1
X2
nc
nc
X1
X2
nc
nc
X1
X2
nc
nc
X2
X1
OSC
OSC
475 Ohms
158 Ohms
422 Ohms
649 Ohms
866 Ohms
Figure 4.1. Crystal Resonator and External Reference Clock Connection Options
In addition to crystal operations, a clipped sine wave, CMOS, or differential reference clock is also accepted on the XA/XB interface.
Most clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 100 Ω or 50 Ω load. For this reason, place the
TCXO as close to the Si5340/41 as possible to minimize PCB trace length. In addition, ensure that both the Si5340/41 and the TCXO
are both connected directly to the ground plane. The above figure includes the recommended method of connecting a clipped sine
wave TCXO to the Si5340/41. Because the Si5340/41 provides DC bias at the XA and XB pins, the ~800 mV peak-peak swing can be
input directly into the XA interface of the Si5340/41 once it has been ac-coupled.
The above figure also illustrates the recommended method of connecting a CMOS rail-to-rail output to the XA/XB inputs. Because the
signal is single-ended, the XB input is ac-coupled to ground. The resistor network attenuates the rail-to-rail output swing to ensure that
the maximum input voltage swing at the XA pin is less than the data sheet specification. The signal is ac-coupled before connecting it to
the Si5340/41 XA input. Again, since the signal is single-ended, the XB input should be ac-coupled to ground.
If an external oscillator is used as the XAXB reference, it is important to use a low jitter source because there is effectively no jitter
attenuation from the XAXB pins to the outputs. To minimize jitter at the XA/XB pins, the rise time of the XA/XB signals should be as fast
as possible.
For best jitter performance, use a XAXB frequency above 40 MHz. Also, for XAXB frequencies higher than 125 MHz, the PXAXB
control must be used to divide the input frequency down below 125 MHz.
In most applications, using the internal OSC with an external crystal provides the best phase noise performance. See AN905: External
References; Optimizing Performance for more information on the performance of various XO's with these devices.
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The recommended crystal and oscillator suppliers are listed in the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and
OCXOs Reference Manual.
4.2 Clock Inputs on IN2, IN1, IN0
A single ended or differential clock may be input to the IN2, 1, 0 inputs as shown below. All input signals must be ac-coupled. When
INx (x = 0, 1, 2) is unused and powered down the plus and minus input can be left floating. ClockBuilder Pro will power down any INx
input that is selected as “unused.” If any INx is powered up but does not have any input signal then the plus input should be left floating
and the minus input should be directly connected to ground. If the plus input is left floating and the minus input is connected to ground
with a 4.7 kΩ or smaller resistor, then the INx can be powered up or down when it does not have an input. The recommended input
termination schemes are shown in the figure below. Unused inputs can be disabled by register configuration.
50
100
INx
INxb
50
Standard AC-Coupled Differential
LVDS, LVPECL, CML
Standard AC-Coupled Single-Ended
INx
3.3V, 2.5V, 1.8V LVCMOS
R1
R2
50
RS
RS matches the CMOS driver to a
50 ohm transmission line (if used)
C1
INxb
*This cap should have less than ~20 ohms of capacitive reactance at the clock input
frequency.
** Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if
needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the
output jitter due to faster input slew rate at INx. If attenuation is not needed for
Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1,
and R2 should be physically placed as close as practicle to the device input pins.
0.1uF *
0.1uF *
* These caps should have < ~5 ohms capacitive reactance at the clock input frequency.
0.1uF *
0.1uF
0.1uF
Clock IC
Standard
Clock IC
Standard
**
Figure 4.2. Terminations for Differential and Single-Ended Inputs
4.3 Unused Inputs
Unused inputs can be disabled and left unconnected. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the
unused input bits will disable them. Enabled inputs not actively being driven by a clock may benefit from pull up or pull down resistors to
avoid them responding to system noise.
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4.4 Reference Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL1,0 pins or by register control. The register bit IN_SEL_REGCTRL determines input
selection as pin or register selectable. If the selected input does not have a clock, all output clocks will be shut off.
Table 4.1. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0] Selected Input
0 0 IN0
0 1 IN1
1 0 IN2
1 1 XA/XB
Table 4.2. Input Control Registers
Register Name
Hex Address [Bit Field]
Function
Si5341 Si5340
XAXB_FREQ_OFFSET 0202[7:0]–0205[7:0]
Adjusts for crystal load capacitance mismatch causing oscillation
frequency errors up to ±1000 ppm. This word is in 2s complement
format.
The XAXB_FREQ_OFFSET word is added to the M divider nu-
merator.
XAXB_EXTCLK_EN 090E[0]
Selects between the XTAL or external reference clock on the
XA/XB pins. Default is 0, XTAL. Set to 1 to use an external refer-
ence oscillator
IN_SEL_REGCTRL 0021[0] Determines pin or register clock input selection.
IN_SEL 0021[2:1] Selects the input when in register input selection mode.
IN_EN 0949[3:0] Allows enabling/disabling IN0, IN1, IN2 and FB_IN when not in
use.
Table 4.3. XAXB Pre-Scale Divide Ratio Register
Setting Name Hex Address [Bit Field] Function
PXAXB 0x0206[1:0] Sets the XAXB input divider value according to the table be-
low.
The following table lists the values, along with the corresponding divider ratio.
Table 4.4. XAXB Pre-Scale Divide Values
Value (Decimal) PXAXB Divider Value
0 1
1 2
2 4
3 8
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4.5 Fault Monitoring
The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock
(LOL) for the PLL. This is shown in the following figure.
PLL
LPFPD
Mn
IN0
IN0 LOS0
÷P0
IN1
IN1 ÷P1
FB_IN
FB_IN
IN2
IN2
÷P2
LOL
Si5341/40
XB
XA OSC
÷Pfb
Md
÷
LOSXAXB
LOS1
LOS2
LOSFB
LOL
LOS0 LOS1 LOS2
LOSXAB
INTR
÷Pxaxb
Figure 4.3. LOS and LOL Fault Monitors
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4.5.1 Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each of
the status indicator register bits has a corresponding sticky bit (_FLG) in a separate register location. Once a status bit is asserted its
corresponding _FLG bit will remain asserted until cleared. Writing a logic zero to a _FLG register bit clears its state.
Table 4.5. Status Monitor Bits (Si5341 and Si5340)
Setting Name Hex Address [Bit Field] Function
Status Register Bits
SYSINCAL 0x000C[0] Asserted when in calibration.
LOSXAXB 0x000C[1]
Loss of Signal at the XA input.
The XB input does not have an LOS detector.
LOSREF 0x000C[2] Loss of Signal for the input that has been selected.
LOL 0x000C[3] Loss of Lock for the PLL.
SMBUS_TIMEOUT 0x000C[5] The SMB bus has a timeout.
LOSIN[3:0] 0x000D[3:0] Loss of Signal for the FB_IN, IN2, IN1, IN0 inputs.
Sticky Status Register Bits
SYSINCAL_FLG 0x0011[0] Sticky bit for SYSINCAL
LOSXAXB_FLG 0x0011[1] Sticky bit for LOSXAXB
LOSREF_FLG 0x0011[2] Sticky bit for LOSREF
LOL_FLG 0x0011[3] Sticky bit for LOL
SMBUS_TIMEOUT_FLG 0x0011[5] Sticky bit for SMBUS_TIMEOUT
LOSIN_FLG 0x0012[3:0] Sticky bit for FB_IN, IN2, IN1, IN0
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