Skyworth 8M51B User manual

SERVICE MANUAL
8M51B CHASSIS
Description:
MODEL.
Engineering Dept:
Artwork By:
Checked By:
Approved By:
Brand Name:
JOB NO.
Date:
Date:
Date:
SERVICE MANUAL 8M51B
2012-5-23
SKYWORTH
SIZE:A5
Design and specifications are subject to change without prior notice.
(Only Referrence)
123
456
789
FREE ZE
POW ER
MENU
.
MUTE
P.P S.M
OK
SLEEP HOME ZOO M
REC CH.LIST FAV EPG
INDE X INFO
EXIT
MTSCC
AUDIO
SUBTITLE
SOURCE
0
T.SHI FT
RETURN
CH
VOL

Content--------------------------------------------------------------2
11-17
18
19-20
21-28
29-45
46-49
50-57

LED 8M51B

TOSHIBA CODE
Component
NTSC-M PAL-M PAL-N
VHF LOW 2~B
VHF HIGH C~W+11
VHF W+12~69
55.25MHz ~ 127.25MHz
133.25MHz ~ 311.25MHz
367MHz ~ 801.25MHz

65
120
140
For 32” LED
For 42” LED
For 47” LED

8
8
6

40
40
3
2
1
4.2
50
0.5
80
40
3
12000
(26inches is 8 ohm)
3.3 3.3
DC Voltage, PANEL(12) 12

40
YES
8
6
46
46
NO
NO
Standard
Spanish
Standard
20

4
2
4
0 40 7 0
0 40 7 0
0 40
40 85
-Y0 50
30000

ISDB-T Analog IF
DDRIII FLASH
2Gb
SYSTEM
POWER SUPPLY
IF+/-
IF+/-
Block Diagram for 8M51B series
2Gbx1+1Gbx1
2Gb
TC90527 ISDB-T Demodulator
POWER SUPPLY
Side Terminal
KEY PAD, IR Receiver
TUNER
Com
p
onent
MSD6329 Ultra high speed 32-bi RISC CPU IF Demo. Build in MPEG1/2/4 /H.264 Decoder
Analog Demo
Serial TS
CitAdi
p
LED PANEL
JPEG MP3 Decoder
C
ompos
it
e +
A
u
di
o
L/R
Audio L/R
AMP5707 8W + 8W
I2S
HDMI data
USB2
USB1
Composite Composite
+Audio L/R
HP AMP. BH3544.
HDMI4 R/L 8M51B
+Audio L/R
Rear Terminal
HDMI3
PC
-
VGA
LAN
VGA-Audio
L/R
Transformer IP101A
S/PDIF Output
HDMI1
PC
VGA
USB1
L/R
HDMI2
USB2
S/PDIF Output

IC Block Diagram
-
U2（3.3V/1A 3-TERMINAL POSITIVE VOL TAGEREGULATOR）LD1117-3.3 SOT-223
GND (Fixed Output)
ADJ (Adjustable Output)
Thermal
Shutdown
Ou t
+
-
INPUT
OUTPUT
U50 （1.1V/3A LOW DROPOUT LINEARAR REGULATOR）AOZ1051PI SO-8
500kHz
Oscillator
AGND PGND
VIN
EN
FB
SS
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
SS
5μA
Q1
Q2
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
+
–
+
–
+
–
+

U3 （2.5V/1A ）AS1117L-ADJ A1 SOT-223
U19 （1.2V/1A）AP1122EG-13 SOT223-3L
GND (Fixed Output)
ADJ (Adjustable Output)
Thermal
Shutdown
Out
+
-
INPUT
OUTPUT
3
Thermal
Shutdown 1
2Vout
GND
1.2V +
+
CURRENT
LIMIT
Vin
+
+

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription and Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
PIN DIAGR AM (M SD 632 9SV)
Top View
12345678910111213
ANC LVB0N LVB1P LVBCKN LVB3P LVA0N LVA 1P LVACKN LVA3P GN D GND GN D
BUSB0_DM NC NC LVB1N LVB2P LVB3N LVB4P LVA 1N LVA2P LVA3N A_DDR3_
A[1]
A_DDR3_
A[14] A_M CLKZ
CUSB0_DP NC NC LVB0P LVB2N LVBCKP LVB4N LVA0P LVA 2N LVACKP LVA4P A_DDR3_
A[12]
A_DDR3_
BA[1]
DNC RTC_XIN RT C _X OU
TGPIO204 GN D GPIO197 GPIO194 GPIO190 GPIO202 GPIO187 LVA4N A_DDR3_
A[11]
A_DDR3_
A[6]
EHW RESET GPIO_PM
[5 ]
GPIO_PM
[8 ] GPIO203 GPIO185 GN D GN D GPIO199 GPIO189 GPIO186 GPIO188 A_DDR3_
A[8]
A_DDR3_
A[4]
FSDO GPIO_PM
[6 ]/S C Z 1 SCZ0 GPIO 200 G PIO 192 G PIO 196 GN D G N D G PIO 191 G PIO 201 GPIO 184 GN D GN D
GSD I SCK BIN0P SPD IFO SPD IFI G PIO 198 G PIO 193 GN D GN D G PIO 195 G PIO 183 GN D GN D
HBIN0M SO G IN0 GIN 0P GPIO_PM
[1 0 ]
ET_R EF_
CLK
ET_TX D [0
]
ET_TX_E
NGN D GN D GN D GN D GN D GN D
JGIN 0M R IN0P R IN0M GPIO_PM
[1 3 ]
ET_TX D [1
]ET_M D IO ET_CRS_
DV GN D GN D GN D GN D GN D GN D
KBIN1P BIN1M SO G IN1 GPIO_PM
[4 ] ET_M DC ET_RX D [0
]
GPIO_PM
[0 ] GN D GN D GN D GN D GN D GN D
LGIN 1P GIN 1M R IN1P GPIO_PM
[2 ]
ET_RX D [1
]
GPIO_PM
[1 ]
GPIO_PM
[1 2 ] GN D GN D GN D GN D GN D GN D
MR IN1M BIN2P B IN2M IR IN A V _LINK GPIO_PM
[3 ]
DD CA _D A/
UART0_TX GN D GN D GN D GN D GN D GN D
NSO G IN2 GIN 2P GIN 2M VSYN C0 H S YN C0 SAR2 DD CA _CK/
UART0_RX GN D GN D GN D GN D GN D GN D
PR IN2P R IN2M C VBS5 SA R0 SAR1 VSYN C1 SA R3 G N D GN D G N D GN D G N D GN D
RCV BS2 CV BS4 CV BS3 H SYN C1 N C N C PG A_C OM BYPASS GN D G N D GN D G N D GN D
TCVBS1 VCOM CVBS0 AUR0 AUL0 AVDD _M
OD33
AVDD _PG
A25 NC AVDD_AU
33 VD D C GN D GN D GN D
UCVBSOUT
0
CVBSOUT
1AUVRP AVDD_RE F25
AVDD _AD
C25
AVDD _AD
C25 NC AVDD_AL IV E
AVDD _EA
R33 GN D GN D GN D
VAUVRM AUVAG AUL2 AVDD _DV
I_ U S B
AVDD _DV
I_ U S B
AVDD _DV
I_ U S B
AVDD _MP
LL
AVDD _D
MP LL GN D G N D GN D
WAUR2 A U L3 AUR3 G N D GN D G N D N C G N D
YAUL4 AUR4 AUL1 DDCDC_C
K
DDCDC_D
A
DDCD A_D
A
HOTPLUG
B
TS0DATA
[6 ]
TS1DATA
[1 ] T S1V A LID T S1C LK G P IO 137
PCMA D R [1
2]/CI_A[12
]
AA AUR1 AUOUTL1 AUOUTR1 HOTPLUG
C
DDCDB_C
KTS2VALID TS2DATA [0 ]
TS0DATA
[4 ]
TS1DATA
[0 ]
TS1DATA
[3 ]
TS1DATA
[5 ]
TS0DATA
[2 ]
TS0DATA
[1 ]
AB AUOUT L0 AUO UTR0 EAR_O UT
L
DDCDD_C
K
DDCDB_D
A
DDCD A_C
KTS2CLK TS2SYNC TS1SYNC TS1DATA
[2 ] TS0VALID TS0CLK TS0DATA
[0 ]
AC EAR_O UT
RXIN XOUT DDCDD_
DA IF_A GC A R C0 TS0DATA
[3 ]
TS0DATA
[5 ]
TS0DATA
[7 ]
TS1DATA
[4 ]
TS1DATA
[6 ]
TS1DATA
[7 ] TS0SYNC
AD GPIO180 GPIO181 GPIO182 RF_AGC/
TAGC NC HOTPLUG
DRX CC KN RX C0P RX C2N RX D CKP RX D 1N RX D 2P RX B 0N
AE G PIO 179 IP VIFM SIFM N C N C HOTPLUG
ARX C0N RX C1P RX D CKN RX D 0P RX D 2N RX BCKP
AF IM VIFP SIFP NC NC CEC RXCCKP RXC1N RXC2P RXD0N RXD1P RXBCKN
12345678910111213
D oc.N o.:20120 10163
IC Block Diagram
U9(LCDTV CONTROLLER WITH VIDEO ECODE)MSD6329SV-Z1-SVN MSTAR

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
14 15 16 17 18 19 20 21 22 23 24 25 26
GN D G N D GN D G N D GN D GN D GN D GN D GN D GN D GN D GN D G N D A
A_M CLK A_DDR3_
DQL[5]
A_DDR3_
DQL[1]
A_DDR3_
DQU[2]
A_DDR3_
DQU[6]
A_DDR3_
DQSBU
A_DDR3_
DQSU
A_DDR3_
DQU[1]
A_DDR3_
DQU[7]
A_DDR3_
DQMU
A_DDR3_
DQL[0]
A_DDR3_
DQL[4] B_M CLKZ B
A_M CLKE A_DDR3_
DQL[7]
A_DDR3_
DQL[3]
A_DDR3_
DQML
A_DDR3_
DQU[0]
A_DDR3_
DQU[4]
A_DDR3_
DQSBL
A_DDR3_
DQSL
A_DDR3_
DQU[3]
A_DDR3_
DQU[5]
A_DDR3_
DQL[2]
A_DDR3_
DQL[6] B_M CLK C
A_DDR3_
A[10] A_RASZ A_CA SZ A_DDR3_
BA[0]
A_DDR3_
A[5] A_RESET A_DDR3_
A[13]
A_DDR3_
A[2]
A_DDR3_
A[0]
A_DDR3_
BA[2]
B_DD R3_
DQL[7]
B_DD R3_
DQL[5] GND D
A_O DT A_W EZ A_DDR3_
A[3]
A_DDR3_
A[7]
A_DDR3_
A[9] B_M CLKE B_DD R3_
DQL[3]
B_DD R3_
DQL[1] GND E
GN D G N D GN D G N D GN D GN D GN D GN D B_DD R3_
DQML
B_DD R3_
DQU[2] GND F
GN D G N D GN D G N D GN D GN D GN D GN D B_DDR3_
A[14]
B_DD R3_
A[1]
B_DD R3_
DQU[0]
B_DD R3_
DQU[6] GND G
GN D G N D GN D G N D GN D GN D GN D GN D B_DDR3_
A[8]
B_DD R3_
A[11]
B_DD R3_
DQU[4]
B_DD R3_
DQSBU GND H
GN D G N D GN D G N D GN D GN D GN D GN D B_DDR3_
A[4]
B_DD R3_
A[6]
B_DD R3_
DQSBL
B_DD R3_
DQSU GND J
GN D G N D AVDD _DD
R0
AVDD _DD
R0
AVDD _DD
R0
AVDD _DD
R0 GN D GN D B_DDR3_
BA[1]
B_DD R3_
A[12]
B_DD R3_
DQSL
B_DD R3_
DQU[1] GND K
GN D G N D GN D AVDD_DD
R0
AVDD _DD
R1
AVDD _DD
R1 GN D GN D B_DD R3_
A[10]
B_DD R3_
DQU[3]
B_DD R3_
DQU[7] GND L
GN D G N D GN D AVDD_DD
R1
AVDD _DD
R1 GN D GN D GN D B_DDR3_
A[3]
B_DD R3_
BA[0]
B_DD R3_
DQU[5]
B_DD R3_
DQMU GND M
GN D G N D GN D AVDD_DD
R1 GN D G N D GN D GN D B_DDR3_
A[7]
B_DD R3_
A[5]
B_DD R3_
DQL[2]
B_DD R3_
DQL[0] GND N
GN D G N D GN D G N D GN D GN D GN D GN D B_DDR3_
A[9] B_RESET B_DDR3_
DQL[6]
B_DD R3_
DQL[4] GND P
GN D G N D GN D G N D GN D GN D GN D B YPASS_
VCO RE
B_DD R3_
A[2]
B_DD R3_
A[13] B_ODT B_RASZ GND R
GN D G N D GN D G N D GN D VD D C GN D GN D B_DDR3_
BA[2]
B_DD R3_
A[0] B _W EZ B _C A SZ GND T
GN D G N D GN D G N D GN D DVDD_D
DR GN D GN D GN D GN D N C N C I2 S _ O U T
_SD U
VDDC VDDC DVDD_D
DR GN D GN D GN D GN D I2 S _ O U T
_BCK
I2 S _ O U T
_WS
I2 S _ O U T
_M CK V
GN D G N D GN D G N D GN D VD D C AV D D _11 AVDD _LP
LL GN D GN D G PIO 102 I2 S _ I N _ S
D
I2 S _ I N _ B
CK W
PCMA D R [1
4]/CI_A[14
]
NF_AD[1]/P
CMA D R[1]/
CI_A[1]
NF_AD[0]/P
CMA D R[0]/
CI_A[0]
NF _CEZ NF _CEZ1 GN D VDDC NC VD DP VDD P I2 S _ I N _W
SDDCR_CK DDCR_DA Y
GPIO138
NF_AD[4]/P
CMA D R[4]/
CI_A[4]
NF_AD[2]/P
CMA D R[2]/
CI_A[2]
NF_AD[3]/P
CMA D R[3]/
CI_A[3]
NF _R EZ GN D VD D C VD D C VD D C VD D C PW M2 PW M4 PW M1 AA
NF _W PZ G PIO 140
NF_AD[7]/P
CMA D R[7]/
CI_A[7]
NF_AD[6]/P
CMA D R[6]/
CI_A[6]
NF_RBZ NF_ALE GPIO40 NC VDDC VDDC PW M3 PW M0 USB1_DP AB
PCMA D R [1
1]/CI_A[11
]
PCMR EG/
CI_CLK
NF_AD[5]/P
CMA D R[5]/
CI_A[5]
GPIO139
PCMA D R [1
3]/CI_A[13
]
NF _CLE NF _W EZ G PIO 39 GPIO42/U
ART1_TX
GPIO41/U
ART1_RX USB1_DM USB2_DP USB2_DM AC
RX B1P RX AC KN RX A0P RX A2N PCM IRQ/
CI_INT
PCM IO R/
CI_RD GPIO45 PCMA D R[5]
/CI_A[5]
PCMA D R [2]
/CI_A[2]
PCMA D R [3]
/CI_A[3]
PCMA D R [8]
/CI_A[8]
PCMA D R [1
0]/CI_A[10
]
GPIO38 AD
RX B1N RX B2P RX A0N RX A1P
PCM W AIT
/C I_ W A C
K
PCM IO W/
CI_WR
PCM CEN/
CI_CS
PCMA D R [0]
/CI_A[0]
PCMA D R [6]
/CI_A[6]
PCMA D R [4]
/CI_A[4]
PCMA D R [7]
/CI_A[7] CI_CD PCMA D R [9] /CI_A[9] AE
RX B0P RX B2N RX AC KP RX A1N RX A 2P PCM W EN PC M O EN GPIO44/U
ART2_RX
PCMA D R [1]
/CI_A[1] CI_R ST G PIO 141 GPIO43/UA RT2_TX AF
14 15 16 17 18 19 20 21 22 23 24 25 26
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
Pin Name Pin Type Fun ction Pin
G PIO [40:38] I/O w / 5V-tolerant GeneralPurpose Input/O utput;4m A driving strength AB20,AC21,
AD26
G PIO _PM[ 13:12] I/O w / 5V-tolerant GeneralPurpose Input/O utput;4m A driving strength J4,L7
GPIO_PM[10] I/O w/5V-tolerant G eneralPurpose Input/O utput;4m A driving strength H 4
G PIO _PM[ 8] I/O w / 5V -tolerant G eneralPurpose Input/O utput;4m A driving strength E3
G PIO _PM[ 6]/
SCZ1
I/O w / 5 V -to lerant GeneralPurpose Input/O utput;4m A driving strength /
ExternalSPI Flash ChipSelect
F2
G PIO _PM[ 5:0] I/O w / 5V-tolerant GeneralPurpose Input/O utput; 4m A driving strength E2,K4,M 6,L4,
L6, K7
PW M 4 O utput PulseWidth M odulation O utput;4m A driving strength AA25
PW M 3 O utput PulseWidth M odulation O utput;4m A driving strength AB24
PW M 2 O utput PulseWidth M odulation O utput;4m A driving strength AA24
PW M 1 O utput PulseWidth M odulation O utput;4m A driving strength AA26
PW M 0 O utput PulseWidth M odulation O utput;4m A driving strength AB25
SAR3 Analog Input SAR Low Speed AD C Input 3;
GeneralPurpose Input/O utput
P7
SAR2 Analog Input SAR Low Speed AD C Input 2;
GeneralPurpose Input/O utput
N6
SAR1 Analog Input SAR Low Speed AD C Input 1;
GeneralPurpose Input/O utput
P5
SAR0 Analog Input SAR Low Speed AD C Input 0;
GeneralPurpose Input/O utput
P4
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
DR AM Interface
Pin Name Pin Type Fun ction Pin
A_DD R3_A
[1 4 :0 ]
Output DRAM M em ory Address B12,D20,C12,
D 12,D 14,E19,
E12,E18,D 13,
D 18,E13,E17,
D21,B11,D22
A_DD R3_BA
[2 :0]
O utput D RAM M em ory Bank Address D 23,C13,D 17
A_M CLKE O utput D RAM M em ory Clock Enable C14
A_ODT I/O Reserved for future O n-D ieTermination E15
A_W EZ O utput W rite Enable; active low E16
A_RASZ O utput Row Address Strobe; active low D 15
A_CA SZ O utput Column Add ress Strobe; active low D 16
A_M CLK Output DRAM M em ory Positiv e D iffe re n t ialClock B14
A_M CLKZ Output DRAM M em ory Negative D ifferentialClock B13
A_DD R3_DQ MU Output Data M ask forLow Byte;active high B23
A_DD R3_DQ ML O utput Data M ask forLow Byte;active high C17
A_DD R3_DQ SU I/O Data Strobe B20
A_DD R3_DQ SL I/O Data Strobe C21
A_DD R3_DQ SBU I/O Data Strobe Inverse B19
A_DD R3_DQ SBL I/O Data Strobe Inverse C20
A_DD R3_DQU
[7 :0]
I/O DRAM M em ory Data Bus B22,B18,C23,
C19,C22,B17,
B21,C18
A_DD R3_DQL
[7 :0]
I/O D R A M M e m o ry D a ta B u s C 1 5 , C 25 , B 1 5 ,
B25,C16,C24,
B16,B24
A_RESET Input D RAM M em ory Reset; active low D 19
B_DDR3_A
[1 4 :0 ]
O utput DRAM M em ory Address G22,R23,K23,
H 23,L23,P22,
H22,N22,J23,
N23,J22,M 22,
R22,G23,T23
B_DDR3_BA
[2 :0]
O utput D RAM M em ory Bank Address T22,K22,M 23
B_M CLKE O utput D RAM M em ory Clock Enable E23
B_O DT I/O Reserved for future O n-D ieTermination R 24
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
Pin Name Pin Type Fun ction Pin
B_W EZ O utput W rite Enable; active low T 24
B_RASZ O utput Row Address Strobe; active low R 25
B_CASZ O utput Column Add ress Strobe; active low T25
B_M CLK O utput DRAM M em ory Positiv e D ifferentialClock C26
B_M CLKZ O utput D RAM M em ory N egative D ifferentialClock B26
B_D D R3_D Q MU O utput D ata M ask for Low Byte; active high M 25
B_DDR3_DQML Output Data Mask forLow Byte;active high F24
B_DDR3_DQSU I/O Data Strobe J25
B_DDR3_DQSL I/O Data Strobe K24
B_DDR3_DQSBU I/O Data Strobe Inverse H 25
B_DDR3_DQSBL I/O Data Strobe Inverse J24
B_DDR3_DQU
[7 :0]
I/O D RAM M em ory D ata Bus L25,G 25, M 24,
H 24, L24, F25,
K25,G24
B_DDR3_DQL
[7 :0]
I/O D RAM M em ory Data Bus D 24,P24,D 25,
P25,E24,N 24,
E25,N 25
B_R ESET Input D R AM M em ory Reset; active low P23
Ethernet RM IIInterface
Pin Name Pin Type Fun ction Pin
ET_CRS_D V I/O w / 5V-tolerant Ethernet M AC Ca rrierSense/Receive D ata Valid J7
ET_TXD [1:0] O utput w / 5V-tolerant Ethernet M AC Transm itD ata Bus J5,H6
ET_TX_EN O utput w / 5V-tolerant Ethernet M AC Transm itEnable H7
ET_REF_CLK Input w / 5V-tolerant EthernetM AC Synchronous Clock Reference for R eceive,
Transm itand ControlInterface
H5
ET_RXD [1:0] Inputw / 5V-tolerant Ethernet M AC R eceive Da ta Bus L5, K6
ET_M D C O utputw / 5V-tolerant Ethernet M AC M anagem entDa ta Clock K5
ET_M D IO I/O w / 5V-tolerant Ethernet M AC M anagem ent D ata Bus J6
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
USB Interface
Pin Name Pin Type Fun ction Pin
USB0_DP Analog I/O USB Non Inverting Data Input/O utputfor Port0 C1
USB0_DM Analog I/O U SB Inverting Da ta Input/O utputfor Port0 B1
USB1_DP Analog I/O USB Non Inverting Data Input/O utputfor Port1 AB26
USB1_DM Analog I/O U SB Inverting Da ta Input/O utputfor Port1 AC24
USB2_DP Analog I/O USB Non Inverting Data Input/O utputfor Port2 AC25
USB2_DM Analog I/O U SB Inverting Da ta Input/O utputfor Port2 AC26
UART Interface
Pin Name Pin Type Fun ction Pin
GPIO44/
UART2_RX
I/O w / 5 V -to lerant G eneralPurpose Input/O utput; 4m A driving strength /
UniversalAsynchronous R eceiver 2
AF21
GPIO43/
UART2_TX
I/O w / 5 V -to lerant G eneralPurpose Input/O utput; 4m A driving strength /
UniversalAsynchronous Transm itte r 2
AF25
GPIO42/
UART1_TX
I/O w / 5 V -to lerant GeneralPurpose Input/O utput;4m A driving strength /
UniversalAsynchronous Transm itte r 1
AC22
GPIO41/
UART1_RX
I/O w / 5 V -to lerant GeneralPurpose Input/O utput;4m A driving strength /
UniversalAsynchronous R eceiver 1
AC23
D D CA _DA/
UART0_TX
I/O w / 5 V -to lerant DDC D ata for Analog port /
UniversalAsynchronous Transm itte r 0
M7
DDCA_CK/
UART0_RX
I/O w / 5 V -to lerant DDC Clock for Analog port/
UniversalAsynchronous R eceiver 0
N7
VIFInterface
Pin Name Pin Type Fun ction Pin
VIFM Analog Input N egative Video IF Input AE3
VIFP Analog Input Positive Video IF Input AF3
RF_AGC/
TAGC
Analog O utput RF AG C /
Tun erAutom aticG ainControlO utput
AD4
PGA_CO M Analog Input VIF PG A N egative Source R7
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
Misc. Interface
Pin Name Pin Type Fun ction Pin
D D CA _DA/
UART0_TX
I/O w / 5 V -to lerant D DC Da ta for Analog port/
UniversalAsynchronous Transm itte r 0
M7
DDCA_CK/
UART0_RX
I/O w / 5 V -to lerant DDC Clock for Analog port /
UniversalAsynchronous Receiver 0
N7
D D CDA _DA I/O w / 5V-tolerant HDC P SerialBusData /DDC Data ofDVI/HDMIPortA Y6
D D CDA _CK Inputw / 5V-tolerant H DC P SerialBus Clock / D D C ClockofDVI/HDMIPortA AB6
DDCD B_DA I/O w/5V-tolerant HDC P SerialBus D ata / D D C Da ta ofD VI/H D M I Port B A B5
DDCD B_CK Inputw/5V-tolerant H DC P SerialBus Clock / D D C ClockofDVI/HDMIPortB AA5
D D CDC _DA I/O w / 5V-tolerant HDC P SerialBus D ata / D D C Da ta ofD VI/H D M I Port C Y5
D D CDC _CK Inputw / 5V-tolerant H DC P SerialBus Clock / D D C ClockofDVI/HDMIPortC Y4
D D CDD _DA I/O w / 5V-tolerant HDC P SerialBus D ata / D D C Da ta ofD VI/H D M I Port D AC4
D D CDD _CK Input w / 5V-tolerant H DC P SerialBus Clock / D D C ClockofDVI/HDMIPortD AB4
HOTPLUGA I/O w/5V-tolerant Hot-plug controlforDVI/HDMIPortA AE7
H O TPLU GB I/O w / 5V -tolerant Hot-plug controlfor D VI/H D M I Port B Y7
HOTPLUGC I/O w/5V-tolerant Hot-plug controlforDVI/HDMIPortC AA4
HOTPLUGD I/O w/5V-tolerant Hot-plug controlforDVI/HDMIPortD AD6
D D C R_DA I/O w / 5V-tolerant D DC Da ta for R O M Y26
D D C R_C K I/O w / 5V-tolerant DDC Clock for RO M Y25
XIN CrystalO scillator Input CrystalO scillator Input AC2
XO UT CrystalO scillator O utput C rystalO scillator O utput AC3
RTC_XOU T CrystalOscillatorO utput RTC 32KH z CrystalO utput D3
RTC_XIN CrystalOscillator Input RTC 32KH z CrystalInput D2
IRIN Inputw / 5V-tolerant IR R eceiverInput M4
H W R ESET Schm ittTrigger Inputw /
5V-tolerant
Hardware Reset;active high E1
BYPASS For ExternalBypass Capacito r R 8
IF_AG C O utputw / 5V-tolerant IF AG C AC5
RF_AGC/
TAGC
O utputw / 5V-tolerant RF AG C /
Tun erAutom aticG ainControlO utput
AD4
CEC I/O Consum erElectronicsControl AF7
AV_LINK I/ O AV Link M5
BYPASS_VCO RE Output Internal VCO RE Volta g e T e st ing Point R21
Doc.No.:
20120 10163

MSD6329SV
DVB Digita l T e levision System -on-Chip
Preliminary P inDiagram /De scription an d Me chan ical D im ensions Version 0.2
1/25/2011
Copyright 2011 M Star Sem ico nd uc to r, In c. A llri gh ts re se rv e d .
Pow erPins
Pin Name Pin Type Fun ction Pin
AVDD _LPLL 3.3V Pow er LPLL Pow er W 21
AVDD _D M PLL 3.3V Pow er CrystalPow er V8
AVDD _M PLL 3.3V Pow er M PLL Pow er V7
AVDD _ALIVE 3.3V Pow er Alive D om ainIO Power U8
AVDD _D VI_U SB 3.3V Pow er D VI U SB Pow er V4-V6
AVDD _EAR33 3.3V Pow er Earphone D river Pow er U 9
AVDD _A U 33 3.3V Pow er Audio Pow er T9
AVDD _AD C25 2.5V Pow er Video AD C Pow er U5,U6
AVDD _REF25 2.5V Pow er D em od AD C Pow er U4
AVDD _M O D33 3.3V Pow er M O D 3.3V Pow er T6
AVDD _PGA25 2.5V Pow er D em od PGA Pow er T7
AVDD _11 1.1V Pow er Analog 1.1V Pow er W 20
AVDD _DD R0 1.5V Pow er D D R3 Pow er K16-K19,L17
AVDD _DD R1 1.5V Pow er D DR3 Pow er L18,L19,M 17,M 18,N 17
D VDD _DDR 1.1V Pow er D D R 1.1V Pow er U19,V19
VD DP 3.3V Pow er D igitalInput/O utput Pow er Y22,Y23
VDDC 1.1V Pow er D igitalCore Pow er T10,T19,V14,V16,W 19,Y20,
AA20-AA23,AB22,AB23
G ND G round G round A11-A26,D 5,D 26,E6,E7,E26,F7,
F8,F12-F21,F26,G 8,G 9,G 12-G 21,
G26,H8-H21,H26,J8-J21,J26,
K8-K15,K20,K21,K26,L8-L16,L20,
L21, L26, M 8-M 16,M 19-M 21,M 26,
N 8-N16,N18-N 21,N 26,P8-P21,P26,
R9-R20,R26,T11-T18,T20,T21,
T26,U10,U12-U18,U20-U23,
V 9 -V 1 1 , V 2 0 -V 23 , W 9 - W 1 1,
W 13-W 18,W 22,W 23,Y19,AA 19
No Connects
Pin Name Pin Type Fun ction Pin
NC No connect A2,B2,B3,C2,C3,D1,R5,R6,T8,
U7,U24,U25,W 12,Y21,AB21,AD5 ,
AE5,AE6,AF5,AF6
Doc.No.:
20120 10163