SMSC 1.8V IO Voltage (10%) flexPWR USB3310 User manual

SMSC USB3310 REV CPRODUCT PREVIEW Revision1.11(10-31-08)
Data Brief
PRODUCT FEATURES
USB3310
Hi-Speed USB Transceiver
with 1.8V ULPI Interface -
Multi-Frequency Reference
Clock
USB-IF “Hi-Speed” compliant to the Universal Serial
Bus Specification Rev 2.0
Interface compliant with the ULPI Specification
revision 1.1 as a Single Data Rate (SDR) PHY
1.8V IO Voltage (±10%)
flexPWRTM Technology
— Low current design ideal for battery powered
applications
— “Sleep” mode tri-states all ULPI pins and places the
part in a low current state
Supports FS pre-amble for FS hubs with a LS device
attached (UTMI+ Level 3)
Supports HS SOF and LS keep-alive pulse
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
Allows host to turn VBUS off to conserve battery
power in OTG applications
Support OTG monitoring of VBUS levels with internal
comparators
“Wrapper-less” design for optimal timing performance
and design ease
— Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max) allows use of legacy UTMI Links with a ULPI
bridge
Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
13, 19.2, 24 or 26MHz Selectable Reference
ClockFrequency
— 0 to 3.6V input drive tolerant
— Able to accept “noisy” clock sources
Internal low jitter PLL for 480MHz Hi-Speed USB
operation
Internal detection of the value of resistance to ground
on the ID pin
Integrated battery to 3.3V LDO regulator
— 2.2uF bypass capacitor
— 100mV dropout voltage
Integrated ESD protection circuits
—Upto±15kV without any external devices
Carkit UART mode for non-USB serial data transfers
Industrial Operating Temperature -40°C to +85°C
Packaging Options
— 24 pin QFN lead-free RoHS compliant package
(4 x 4 x 0.90 mm height)
Applications
The USB3310 is targeted for any application where a Hi-
Speed USB connection is desired and when board
space, power, and interface pins must be minimized.
The USB3310 is well suited for:
Cell Phones
PDAs
MP3 Players
GPS Personal Navigation
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers
Set Top Boxes
Video Record/Playback Systems
IP and Video Phones
Gaming Consoles
POS Terminals

Order Number(s):
USB3310C-CP-TR FOR 24 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)
REEL SIZE IS 4000 PIECES.
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
Revision 1.11 (10-31-08) 2 SMSC USB3310 REV C
PRODUCT PREVIEW
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]
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Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
SMSC USB3310 REV C3 Revision 1.11 (10-31-08)
PRODUCT PREVIEW
General Description
The USB3310 is a highly integrated Hi-Speed USB 2.0 Transceiver (PHY) that supports systems
architectures based on a 13, 19.2, 24 or 26MHz reference clock. The frequency of the reference clock
is selected by configuration. It is designed to be used in both commercial and industrial temperature
applications.
The USB3310 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device,
or an On-the-Go (OTG) device. In addition to the supporting USB signaling the USB3310 also provides
USB UART mode.
USB3310 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the
Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers
between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte
transfers the ULPI interface requires only 12 pins.
The USB3310 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-
less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
The USB3310 is designed to operate with an external reference clock at one of four frequencies. By
using an available reference, the USB3310 saves the cost of a crystal reference.
The USB3310 includes a integrated 3.3V LDO regulator to generate its own supply from power applied
at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout
voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on
VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some
parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V
supply to the USB3310, the VBAT and VDD33 pins should be connected together.
The USB3310 also includes integrated pull-up resistors that can be used for detecting the attachment
of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3310 can
charge its battery at more than the 500mA allowed when charging from a USB Host.
Figure 1 USB3310 Block Diagram
OTG
Carkit
Hi-Speed
USB
Transceiver
ULPI Interface
ULPI
Registers
and State
Machine
BIAS
LowJitter
Integrated
PLL
Integrated
Power
Management
VBUS
ID
DP
DM
RBIAS
REFSEL[1]
ESD Protection
DATA[7:0]
REFSEL[0]
RESETB
VDD18
VDD33
VBAT
DIR
NXT
STP
CLKOUT
REFCLK

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
Revision 1.11 (10-31-08) 4 SMSC USB3310 REV C
PRODUCT PREVIEW
USB3310Pin Locations and Descriptions
Package Diagram with Pin Locations
The pinout below is viewed from the top of the package.
Pin Definitions
The following table details the pin definitions for the figure above.
Figure 2 USB3310 QFN Pinout - Top View
Table 1 USB3310 Pin Description
PIN
BALL NAME DIRECTION/ TYPE ACTIVE LEVEL DESCRIPTION
1
B1 ID Input,
Analog N/A ID pin of the USB cable. For non-OTG applications this pin can be floated. For
an A-Device ID is grounded. For a B-
Device ID is floated.
2
C1 VBUS I/O,
Analog N/A VBUS pin of the USB cable. This pin is used for the Vbus comparator inputs and
for Vbus pulsing during session request
protocol.
3
C2 VBAT Power N/A Regulator input. The regulator supply can
be from 5.5V to 3.1V.
DATA7
VBUS
ID
VDD3.3
DM
DP
NXT
DIR
STP
DATA3
DATA1
REFSEL[1]
DATA2
REFSEL[0]
VBAT
VDD1.8
CLKOUT
DATA5 DATA6 DATA4
1
2
3
4
5
6
7 8 9 10 11 12
18
17
16
15
14
13
24 23 22 21 20 19
24Pin QFN
4x4mm
RESETB
DATA0
RBIAS REFCLK

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
SMSC USB3310 REV C5 Revision 1.11 (10-31-08)
PRODUCT PREVIEW
4
D2 VDD3.3 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3310.
5
D1 DM I/O,
Analog N/A D- pin of the USB cable.
6
E1 DP I/O,
Analog N/A D+ pin of the USB cable.
7
E2 DATA[7] I/O,
CMOS N/A ULPI bi-directional data bus. DATA[7] is
the MSB.
8
E3 DATA[6] I/O,
CMOS N/A ULPI bi-directional data bus.
9
D3 DATA[5 I/O,
CMOS N/A ULPI bi-directional data bus.
10
E4 DATA[4] I/O,
CMOS N/A ULPI bi-directional data bus.
11
E5 CLKOUT Output,
CMOS N/A 60MHz reference clock output. All ULPI signals are driven synchronous to the
rising edge of this clock.
12
D5 DATA[3] I/O,
CMOS N/A ULPI bi-directional data bus.
13
D4 DATA[2] I/O,
CMOS N/A ULPI bi-directional data bus.
14
C4 REFSEL[1] Input,
CMOS N/A These signals select one of the available reference frequencies:
[1] [0] Description
0 0 13MHz
0 1 19.2MHz
1 0 26MHz
1 1 24MHz
15
B4 REFSEL[0] Input,
CMOS N/A
16
C5 DATA[1] I/O,
CMOS N/A ULPI bi-directional data bus.
17
B5 DATA[0] I/O,
CMOS N/A ULPI bi-directional data bus. DATA[0] is
the LSB.
18
A5 NXT Output,
CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Table 1 USB3310 Pin Description (continued)
PIN
BALL NAME DIRECTION/ TYPE ACTIVE LEVEL DESCRIPTION

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
Revision 1.11 (10-31-08) 6 SMSC USB3310 REV C
PRODUCT PREVIEW
19
A4 DIR Output,
CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the
Link, it drives DIR high to take ownership
of the bus. When the PHY has no data to
transfer it drives DIR low and monitors
the bus for commands from the Link.
20
A3 STP Input,
CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the
bus. If the Link is sending data to the
PHY, STP indicates the last byte of data
was on the bus in the previous cycle.
21
B3 VDD1.8 Power N/A External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3310.
22
B2 RESETB Input,
CMOS, N/A When low, the part is suspended with all of the I/O tri-stated. When high the
USB3310 will operate as a normal ULPI
device.
23
A2 REFCLK Input,
CMOS N/A Reference Clock input.The required frequency is configured by the
REFSEL[1:0] pins.
24
A1 RBIAS Analog,
CMOS N/A Rbias pin. This pin requires an 8.06kΩ (±1%) resistor to ground, placed as close
as possible to the USB3310.
FLAG
C3 GND Ground N/A Ground.
QFN only: The flag should be connected
to the ground plane with a via array
under the exposed flag. This is the main
ground for the IC.
Table 1 USB3310 Pin Description (continued)
PIN
BALL NAME DIRECTION/ TYPE ACTIVE LEVEL DESCRIPTION

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
SMSC USB3310 REV C7 Revision 1.11 (10-31-08)
PRODUCT PREVIEW
Application Diagrams
Figure 3 USB3310 QFN Application Diagram (Device)
LinkController
USB331X
RBIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
VBAT
VDD3.3
VBUS
DM
DP
ID
RESETB
USB
Receptacle
DM
DP
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
6
5
24
GND FLAG
2
3
VBUS 1
SHIELD
GND
4
3
2
1
CBYP
CVBUS
3.1-5.5V
Supply
RVBUS may be installed in this configuration to
assist in protecting the VBUS pin. 820 Ohms
will protect against VBUS transients up to
8.5V. 10K Ohms will protect against
transients up to 10V.
REFCLK
VDD18 21
Reference
COUT
CDC_BLOCK 8.06k
Steady state voltage at the VBUS pin must not be
allowed to exceed VVMAX.
RVBUS
NC
7
8
9
10
12
13
16
17
20
18
19
11
22
23
CBYP
1.8VSupply
REFSEL[1] 14
The capacitor CVBUS must be
installed onthissideof RVBUS.
Signal at REFCLK
must comply with
VIH and VIL
REFSEL[0] 15
Pin Strap
Determines
REFCLK
frequency

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
Revision 1.11 (10-31-08) 8 SMSC USB3310 REV C
PRODUCT PREVIEW
Figure 4 USB3310 QFN Application Diagram (Host or OTG)
Link Controller
USB331X
RBIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
REFCLK
VBAT
VDD3.3
VBUS
DM
DP
RESETB
USB
Receptacle
DM
DP
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
6
5
24
1
GND FLAG
2
3
VBUS
GND
SHIELD
CVBUS
4
3
2
VBUS Switch
OUT
EN
COUT
CBYP
IN
ID 4ID
1
3.1 - 5.5V
Supply
8.06k
Reference
5V
RVBUS
The capacitor CVBUS must be
installed onthissideof RVBUS.Signal at REFCLK
must comply with
VIH and VIL
VDD18 21
CBYP
1.8VSupply
REFSEL[1] 14
REFSEL[0] 15
Pin Strap
Determines
REFCLK
frequency
CPEN
Voltage at the VBUS pin must not be allowed
to exceed VVMAX.
RVBUS may be installed in this
configuration to assist in protecting
the VBUS pin. 820 Ohms will
protect against VBUS transients up
to 8.5V. 7
8
9
10
12
13
16
17
20
18
19
11
22
23

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock Revision 1.11 (10-31-08) 9 SMSC USB3310 REV C
PRODUCT PREVIEW
Package Outline
Figure 5 24-Pin QFN, 4x4mm Body, 0.5mm Pitch