Sony XDP-4000X Operating Instructions (primary... User manual

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SERVICE MANUAL
SPECIFICATIONS
Power requirements 12 V DC car battery (negative
ground, 10.5 V – 16 V)
Current drain 1 A
Frequency response 5 Hz – 20 kHz
Signal-to-noise ratio 105 dB (Optical input)
Harmonic distortion 0.003 % (Optical input)
Separation 95 dB at 1 kHz
Input/output terminals BUS input (1)
BUS output (1)
Line input (RCA jack) (2)
Line output (RCA jack) (4)
Optical digital input (2)
Dimensions Approx. 249 ×45 ×183 mm
(9 7/8 ×1 13/16 ×7 1/4 in.) (w/h/d)
Mass Approx. 2 kg (4 lb. 7 oz.)
Design and specifications are subject to change without
notice.
XDP-4000X
US Model
Canadian Model
AEP Model
UK Model
E Model
DIGITAL EQUALIZER PREAMPLIFIER
MICROFILM
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.

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SECTION 1
SERVICE NOTE
TABLE OF CONTENTS
1. SERVICE NOTE................................................................. 2
2. GENERAL
Operation ................................................................................. 4
Connection............................................................................... 5
3. DISASSEMBLY
3-1. Case (Upper)....................................................................... 7
3-2. Main Board......................................................................... 7
4. DIAGRAMS
4-1. IC Pin Descriptions ............................................................ 8
4-2. Block Diagram – Input section –...................................... 15
4-3. Block Diagram – DSP section –....................................... 17
4-4. Block Diagram – Output section – ................................... 19
4-5. Printed Wiring Board – Main Section – ........................... 21
4-6. Schematic Diagram – Main Section (1/4) – ..................... 25
4-7. Schematic Diagram – Main Section (2/4) – ..................... 27
4-8. Schematic Diagram – Main Section (3/4) – ..................... 29
4-9. Schematic Diagram – Main Section (4/4) – ..................... 31
4-10. Schematic Diagram – DAC, Intelligence,
Indicator Section –............................................................ 33
4-11. Printed Wiring Board – DAC Section – ........................... 35
4-12. Printed Wiring Boards – Intelligence,
Indicator Section –............................................................ 37
5. EXPLODEDVIEW........................................................... 43
6. ELECTRICAL PARTS LIST......................................... 44
+
–
BATT,ACC
GND
master unit
regulated DC
power supply
(14.4V)
+
–
B+
GND
regulated DC
power supply
(14.4V)
BUS CONTROL IN
BUS CONTROL IN
(MASTER)
XDP-4000X
METHOD OF OPERATINGTHE XDP-4000X
This set cannot be operated alone.
To operated this, it should be connected with a master unit such as
CDX-C880 or XR-C9100 as shown below.

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12345
6 7 8 9
METHOD OF DETERMINING ACCEPTANCE OR REJECTION OF
INTELLIGENCE BOARD (A-3317-137-A) OF XDP-4000X
• No parts in the intelligence board can be repaired.
If the intelligence board is defective, the whole board
should be replaced.
Pin numbers of 9-pin D-SUB connector (CN707)
(viewed from the top of the set)
Note that the voltage given in the following
descriptions is relative to the ground power pin.
Intelligence board check
Is voltage at pin !º of IC707 +5V?
Is voltage at pin 3of CN707
between –8 and –9V ?
Is the resistance between pin 1of CN703
and ground hundreds of 100 kilohms or more
Pull cable out of CN703 on main board.
Is voltage at pin 2of the CN703 +5V?
Intelligence board at fault
Intelligence board at fault
Intelligence board is normal
Main board at fault
Set ACC-OFF and pull cable out of
CN703 on main board
Main board at fault
Yes
Yes
Yes
Yes
Is voltage at pin 9of IC707 +5V?
Is voltage at pin 2of CN707 0V?
Is voltage at pin 9of IC707 0V?
Add –8 to –9V to pin 2of CN707
Yes
Yes
Yes
No
No
No
No
No
No
No
The fault of the main board may be caused by one of the
following:
1. Shorted CN703 (OPEN).
2. Shorted pins !™ and !¢ of IC702 (OPEN).
3. Damaged port of IC702.

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This section is extracted
from instruction manual.
SECTION 2
GENERAL

– 5 –

– 6 –

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SECTION 3
DISASSEMBLY
Note : Follow the disassembly procedure in the numerical order given.
3-1. CASE (UPPER)
3 ornamental plate assy
2 hexagon socket bolt (M4x6
)
1 hexagon socket bolt (M4x6)
4 CN706
5 CN703
6 PTT3x6
7 PTT3x6
8 PTT3x6
9 PTT3x6
0 case (upper)
3-2. MAIN BOARD
1 connectors
4 PTT3x6
3 PTT3x6
2 DAC board
5 PTP3x8
6 PTT2.6x8
7 PTP3x8
8 MAIN board
9 spacer

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SECTION 4
DIAGRAMS
4-1. IC PIN DESCRIPTIONS
• IC502 CXD2710R (DIGITAL SIGNAL PROCESSOR)
Pin No. Pin Name I/O Pin Description
1 AMPIN I Loop filter amplifier input for the PLL.
2 AMPOUT O Loop filter amplifier output for the PLL.
3 VDD — Digital power supply pin (+5 V)
4 VSS — Ground
5 AVSS1 — Ground (for PLL)
6 VCOC I VCO control input
7 AVDD1 — Power supply pin (for PLL) (+5V)
8 VCOOUT O VCO output for the PLL. Not used. (open)
9 MCK1 I Master clock (768Fs) input
10 MCK2 I Master clock (384Fs) input
11 MCKOUT O Master clock (384Fs) output. Not used. (open)
12 MCKSEL I Input for clock signal setting internal VCO or MCK1 (pin 9).
Internal VCO used: “L”, MCK1 (pin 9) used: “H” (Fixed at “L”.)
13 XMUTE I Output mute signal input of the serial interface. (“L”: mute ON) (Fixed at “H”.)
14 DIN I Program data serial input
15 VSS — Ground
16 SCK I Program data shift clock signal input
17 XLD I Program data load input
18 DOUT O Internal data serial output to the system control (IC702).
19 BUSY O Busy signal at serial data transfer output to the system control (IC702).
20 XCLR I Reset signal input from the system control (IC702). “L”: reset
21 – 27 TEST I Test pin (Normally connect to ground.)
28 VDD — Digital power supply pin (+5 V)
29 VSS — Ground
30 – 38 TEST I Test pin (Normally connect to ground.)
39 TEST — Test pin (Normally open.)
40 VSS — Ground
41 – 52 TEST — Test pin (Normally open.)
53 VDD — Digital power supply pin (+5 V)
54 VSS — Ground
55 – 64 TEST — Test pin (Normally open.)
65 VSS — Ground
66 – 74 TEST — Test pin (Normally open.)
75 EBDIR I Test pin (Normally connect to ground.)
76 UBDIR I Test pin (Normally connect to ground.)
77 TEST0 I Test pin (Normally connect to ground.)
78 VDD — Digital power supply pin (+5 V)
79 VSS — Ground
80 TEST1 I Test pin (Normally connect to ground.)
81 DTEST0 I Test pin (Normally connect to ground.)
82 DTEST1 I Test pin (Normally connect to ground.)
83 AVDD2 — Power supply pin (for D-RAM) (+5V)
84 AVSS2 — Ground (for D-RAM)
85 AVDD3 — Power supply pin (for D-RAM) (+5V)
86 AVSS3 — Ground (for D-RAM)
87 S3OUT O Serial data output of 1 sampling, 2 channel.
88 S2OUT O Serial data output of 1 sampling, 2 channel.
89 S1OUT O Serial data output of 1 sampling, 2 channel.
90 VSS — Ground
91 S3DI I Serial data input of 1 sampling, 2 channel.
92 S2DI I Serial data input of 1 sampling, 2 channel.

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Pin No. Pin Name I/O Pin Description
93 S1DI I Serial data input of 1 sampling, 2 channel.
94 BCK I Bit clock input of the serial input/output data.
95 LRCK I Sampling clock input of the serial input/output data.
96 LOCK O Error output of the PLL unlock.
97 V O Frequency divider output for the PLL.
98 VAR I PLL phase comparator variable input
99 REF I PLL phase comparator reference input
100 PD O PLL phase comparator charge pump output

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• IC503, 504 CXD2711Q (DIGITAL SIGNAL PROCESSOR)
Pin No. Pin Name I/O Pin Description
1 VSS — Ground
2 CRDY O Output of ready signal at serial data transfer to the system control (IC702).
“H”: Ready
3 CCNT I Input of control/data from address bus for the system control (IC702). “L”: data input
4 XCWR I Strobe signal input for data writing from the system control (IC702).
Data are written by a falling edge.
5 XCRD I Strobe signal input for data reading from the system control (IC702). “L”: data read
6 VDD — Power supply pin (+3.3 V)
7 CD0 I/O Two-way data bus (LSB) with the system control (IC702).
8 CD1 I/O
9 CD2 I/O Two-way data bus with the system control (IC702).
10 CD3 I/O
11 VSS — Ground
12 CD4 I/O
13 CD5 I/O Two-way data bus with the system control (IC702).
14 CD6 I/O
15 CD7 I/O Two-way data bus (MSB) with the system control (IC702).
16 VDD — Power supply pin (+3.3 V)
17 XMUTE I Mute control signal input of the audio data. “L”: mute. (Fixed at “H”.)
18 XCCS I Input of chip select signal from address bus. “L”: chip select
19 VSS — Ground
20 MCKO O Master clock signal (18.432 MHz) output. Not used. (open)
21 VSS — Ground
22 XT2O O System clock signal (36.864 MHz) output. Not used. (open)
23 XT2I I System clock signal (36.864 MHz) input
24 VSS — Ground
25 (BIST) — Test pin. Not used. (open)
26 (TCK) — Test pin. Not used. (open)
27 (TDI) — Test pin. Not used. (open)
28 (TENA1) — Test pin. Not used. (open)
29 (TDO) — Test pin. Not used. (open)
30 VST I Not used. (Fixed at “L”.)
31 VSS — Ground
32 XRST I Reset signal input. “L”: reset
33 BCLK I/O Block clock signal input/output. Not used. (open)
34 LRCK I/O L/R sampling clock signal input/output
35 BCK I/O Bit clock signal input/output
36 VSS — Ground
Serial audio data signal input A
37 SIA I IC503: Serial audio data signal input from the digital signal processor (IC502).
IC504: Serial audio data signal input from the digital signal processor (IC502).
Serial audio data signal input B
38 SIB I IC503: Serial audio data signal input from the digital signal processor (IC502).
IC504: Serial audio data signal input from the digital signal processor (IC502).
Serial audio data signal output A
39 SOA O IC503: Serial audio data (high) signal output
IC504: Serial audio data (sub) signal output
Serial audio data signal output B
40 SOB O IC503: Serial audio data (high) signal output
IC504: Serial audio data (low) signal output
41 VSS — Ground
42 – 45 TEST I Test pin. Not used. (Connect to ground.)