Steren HOT-557 User manual
User's Manual 1
HOT-557
Layout-Version 1.5
Pentium™processor
Based PCI MAIN BOARD
User's Manual
FCC Notice:
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of
FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy. If not installed and used properly, in
strict accordance with the manufacturer’s instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause
interference to radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures :
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/television technician for help and for additional suggestions.
The user may find the following booklet prepared by the Federal Communications Commission helpful “How to Identify
and Resolve Radio-TV Interference Problems.” This booklet is available from the U.S. Government Printing Office.
Washington, DC 20402, Stock 004-000-00345-4
FCC Warning
The user is cautioned that changes or modifications not expressly approved by the manufacturer could void the user’s
authority to operate this equipment.
Note : In order for an installation of this product to maintain compliance with the limits for a Class B device, shielded
cables and power cord must be used.
NOTICE
Copyright 1997.
All Right Reserved
Manual Ver 3.0
All information, documentation, and specifications contained in this manual are subject to change without prior
notification by the manufacturer.
The author assumes no responsibility for any errors or omissions which may appear in this document nor does it
make a commitment to update the information contained herein.
TRADEMARKS
Intel is a registered trademark of Intel Corporation
PentiumProcessor is a registered trademark of Intel Corporation
PC/AT is a registered trademark of International Business Machine Corporation.
PS/2 is a registered trademark of IBM Corporation.
All other brand and product names referred to in this manual are trademarks or registered trademarks of their
respective holders.
CE Notice:
Following standards were applied to this product, in order to achieve compliance
with the electromagnetic compatibility:
- Immunity in accordance with EN 50082-1: 1992
- Emmitions in accordance with EN 55022: 1987 Class B.
User's Manual 3
TABLE OF CONTENTS
PREFACE ............................................................................................ 4
CHAPTER 1 INTRODUCTION.................................................................. 5
Specification.......................................................................................................5
CHAPTER 2 HARDWARE CONFIGURATION............................................... 7
Jumpers ...............................................................................................................7
CPU Clock Speed Selection..............................................................................8
Onboard Regulators Output - J100, J101, J102, J107................................10
Pipeline Burst Type Cache Size Selection - JP29, JP30.............................11
Flash EPROM Jumper - JP19.........................................................................12
Clear CMOS - JP21.........................................................................................12
Clear Password - JP9.......................................................................................13
Display Mode Jumper - JP7............................................................................13
Factory Reserved Jumpers - JP39, JP43, JP44.............................................13
Connectors & Sockets......................................................................................14
CHAPTER 3 MEMORYCONFIGURATION ............................................... 15
CHAPTER 4 AWARD BIOS SETUP....................................................... 17
The Main Menu................................................................................................18
Standard CMOS Setup....................................................................................20
BIOS Features Setup.......................................................................................22
Chipset Features Setup....................................................................................24
Power Management Setup...............................................................................27
PCI Configuration Setup.................................................................................29
Integrated Peripherals......................................................................................31
Password Setting..............................................................................................33
User's Manual 4
HOT-557 mainboard is a highly integrated IBM PC/AT compatible system
board. The design will accept Intel Pentium, Cyrix/IBM 6x86/L and AMD K5
processors and also features high-performance pipeline burst secondary cache
memory support with size of 256KB and 512KB. The memory subsystem is
designed to support up to 128 MB of EDO RAM, Standard Fast Page DRAM
and SDRAM in standard 72-pin SIMM socket and 168-pin 3.3 V DIMM
socket. A type 7 Pentium processor socket provides access to future processor
enhancements.
HOT-557 provides a new level of I/O integration. Intel's 82430VX PCIset
chipset provides increased integration and improved performance over other
chipset designs. The 82430VX PCIset chipset provides an integrated Bus
Mastering IDE controller with two high performance IDE interfaces for up to
four IDE devices.
The onboard Super I/O controller provides the standard PC I/O functions:
floppy interface, two FIFO serial ports, an IrDA device port and a SPP/EPP/
ECP capable parallel port.
Up to four PCI local bus slots provide a high bandwidth data path for data-
movement intensive functions such as graphics, and up to three ISA slots
complete the I/O function.
The HOT-557 provides the foundation for cost effective, high performance,
highly expandable platforms, which deliver the latest in Pentium processor and
I/O standard
Preface
User's Manual 5
Chapter1 Introduction
Specification
CPU Function
Pentium processors : 75~200MHz
Cyrix/IBM 6x86/L processors : P120+~P166+
AMD K5 processors : PR75~PR166
Chipset
Intel PCIset 82437VX, 82438VX and 82371SB
Memory
Supports two banks of EDO, Fast Page Mode DRAM or
3.3V Sync. DRAM ranging from 8MB to 128MB
Supports 4MB, 8MB, 16MB, 32MB 72-pins SIMMs or
8MB, 16MB, 32MB 168-pin DIMMs
Cache Memory
Integrated L2 write-back cache controller
- 256KB or 512KB Direct Mapped Pipeline Burst Cache
Power Management Function
Provides four power management modes : Full on, Doze,
Standby, and Suspend
Supports Microsoft APM
Provides EPMI (External Power Management Interrupt) pin
User's Manual 6
Expansions
32-bit PCI bus slot x 4
16-bit ISA bus slot x 3
2-channel PCI IDE port
- Support up to 4 IDE devices
- PIO Mode 4, DMA Mode 2 transfers up to 22 MB/sec
- Integrated 8 x 32-bit buffer for PCI IDE burst transfers
One floppy port
One parallel port
- Supports SPP (PS/2 compatible bidirectional Parallel
Port), EPP (Enhanced Parallel Port), andECP (Extended
Capabilities Port) high performance parallel port.
Two serial ports
- Supports 16C550 compatible UARTS.
- Supports IrDA (Infra-red) communication.
One PS/2 mouse port
Two USB (Universal Serial Bus) ports
System Bios
Award PnP Bios v4.51PG
Bundled with Symbios Login (NCR) SDCM V4.0 SCSI Bios
Board Design
Dimension 220mm x 280mm
User's Manual 7
Jumpers
Chapter2Hardware Configuration
User's Manual 8
CPU Clock Speed Selection
HOT-557 mainboard features a clock generator to provide adjustable system
clock frequency. JP36 is a 6-pin jumper that determine the system clock
frequency from 50 MHz to 66 MHz.
HOT-557 mainboard also provides Jumpers JP23 and JP24 to figure the
CPU core clock multiplier. By inserting or removing jumper caps on JP23
and JP24, the user can change theHost Bus Clock/CPU Core Clock
ratio from 1 : 1.5 to 1 : 3.
Intel Pentium Processor
CPU Type System Clock
(JP36) Clock Multiplier
(JP23, JP24)
200 MHz66 MHz3 x
166 MHz66 MHz2,5 x
150 MHz60 MHz2,5 x
133 MHz66 MHz2 x
125 MHz50 MHz2,5 x
120 MHz60 MHz2 x
100 MHz66 MHz1,5 x
90 MHz60 MHz1,5 x
75 MHz50 MHz1,5 x
User's Manual 9
AMD K5 Processor
CPU Type System Clock
(JP36) Clock Multiplier
(JP23, JP24)
PR200
(133 MHz)66 MHz2 x
PR166
(116,7MHz)66 MHz1,75 x
PR150
(105 MHz)60 MHz1,75 x
PR133
(100 MHz)66 MHz1,5 x
PR120
(90 MHz)60 MHz1,5 x
PR100
(100 MHz)66 MHz1,5 x
PR90
(90 MHz)60 MHz1,5 x
PR75
(75 MHz)50 MHz1,5 x
Cyrix/IBM 6x86/6x86L
CPU Type System Clock
(JP36) Clock Multiplier
(JP23, JP24)
P166+
(133 MHz)66 MHz2 x
P150+
(120 MHz)60 MHz2 x
P133+
(110 MHz)55 MHz2 x
P120+
(100 MHz)50 MHz2 x
User's Manual 10
HOT-557 mainboard is designed with dual onboard voltage regulator to
provide single 3.3V voltage (VIO=VCORE) for Intel Pentium P54C, 3.5V for
Cyrix/IBM 6x86 and AMD K5 processors, and also provide dual 3.3/2.8V
voltage (VIO, VCORE separated) for Intel P55C, Cyrix/IBM 6x86L and
AMD future processors.
Onboard Regulator Output- J100, J101, J102, J107
Single Voltage Output (VIO=VCORE)
Voltage
Output J100 J108 J107 J105
3.53 V
3.33 V
3.10 V
2.94 V
2.82 V
Vcore
Output J100 J108 J107 Vio
Output J105
2.82 V3.33 V
2.94 V3.44 V
3.10 V
Dual Voltage Output (VIO, VCORE separated)
User's Manual 11
Pipeline Burst Type Cache Size Selection - JP29, JP30
HOT-557 mainboard supports 256KB or 512KB pipeline burst cache.
If the HOT-557 is ordered with no cache installed, the cache can be field
upgraded by installing aprimary 256KB pipeline burst cache module
into the CELP socket.
If factory option on HOT-557 mainboard integrate 256KB pipeline burst
cache onboard already, the cache size can be field upgraded to 512KB by
installing a secondary 256KB pipeline burst cache module into the
CELP socket.
256KB Cache Memory
On mainboard integrate 256KB pipeline burst cache mounted, or a primary
256KB pipeline burst cache module in the CELP socket.
512KB Cache Memory
On mainboard integrate 256KB pipeline burst cache mounted and a
secondary 256KB pipeline burst cache module in the CELP socket.
Note : There are some technical difference between the primary 256KB
pipeline burst cache module and secondary one, if 512KB cache memory
are required, please contact your supplier for help .
User's Manual 12
HOT-557 mainboard supports jumperJP21 for discharging mainboard's
CMOS memory. The CMOS memory retains the system configuration
information in the component of R.T.C.
You should short this jumper for a moment when you wish to clear CMOS
memory, and then make sure open this jumper for normal operation to retain
your new CMOS data.
Note: Clear CMOS & R.T.C function is available only when
"DS12887A" or "DS12B887" is in use.
There are different ways to discharge CMOS memory between "DS12887A" and
"DS12B887".
DS12887A- Turn off power, close jumper JP21 for 2 to 3 seconds then release and
CMOS will be discharged.
DS12B887- Close jumper JP21, turn on power for 2 to 3 seconds then release JP21 and
turn off power, CMOS will be discharged.
Clear CMOS - JP21
Flash EPROM Jumper - JP19
HOT-557 mainboard supports two types of flash EPROM, 5 volt and 12
volt. By setting up jumper JP19, you can update both types of flash
EPROM with new system BIOS files as they come available.
JP19 Pin 2-3 Close for 5V, Pin 1-2 Close for 12V.
BIOS UPGRADES
Flash memory makes distributing BIOS upgrades easy. A new version of
the BIOS can be installed from a diskette.
Please note the following when making the BIOS updates.
***** Flash utility can't work under protected/virtual mode. Memory
manager like QEMM.386, EMM386 should not be loaded. (or
Simply bypass all config.sys and autoexec.bat on system boot
up.
***** Flash utility supports both 5V and 12V Flash EEPROM.
User's Manual 13
Clear Password - JP9
Allows system password to be cleared by shorting jumper JP9 and turning
the system on, "Password is cleared by jumper, (JCP) !" message will
be shown on power-on screen. The system should then be turned off and
the jumper JP9 should be returned to OPEN to restore normal operation.
The procedure should only be done if the user password has been
forgotten. (This function is not available when AMD K5 or Cyrix 6x86
CPU is in use)
Display Mode Jumper - JP7
Factory Reserved Jumpers - JP39, JP43, JP44
On the HOT-557 mainboard remain three jumpers for future use.
Normally, those jumpes were defualt by the manafacturer and need not to
change by the user.
JP39 is a three pin header and default on pin 2-3 closed by a cap.
JP43 is a two pin header and default on closed by a cap.
JP44 is a three pin header and default on opened.
User's Manual 14
Note 1: JP3 - Infrared module connector
The main board provides a 5-pin infrared connector - JP3 as
an optional infrared module for wireless transmitting and
receiving. Only first 4 pins are available, left 3 pins are
reserved for future use.
Note 2: J10, J11 - USB connectors
The main board provides two sets USB (Universal Serial
Bus) connectors - J10 and J11 for USB devices use.
Note 3: JP1 - 12V cooling fan power connector
The main board provides a on-board 12V cooling fan power
connector for cooling fan. Please make sure the red wire
connect to +12V and black wire connect to ground (GND).
Connectors & Sockets
Connectors & Sockets
ITEMFUNCTION
J2,J3,J4,J5On-boardSIMM sockets
DIM1,DIM2On-board3.3VDIMM sockets
J23,J17,J18,J19 On-boardPCISlots
J20,J21,J22 On-boardISA Slots
J6 On-boardPCIPrimaryIDEConnector
J7 On-boardPCISecondaryIDEConnector
CN1On-boardFloppyControllerConnector
CN4On-boardParallelPortConnector
CN2On-boardSerialport-1Connector
CN3On-boardSerialPort-2Connector
J99 On-boardPS/2MousePortConnector
J14 PowerLEDand Keylock Connector
J12 PCSpeakerConnector
JP12 HardwareResetSwitchConnector
JP33 Green LED
JP15 EPMIConnector
JP22 On-boardEnhanced IDER/WLED
Connector
J10,J11 UniversalSerialBus(USB)Connectors
JP3Infra-red Communication PortConnector
JP1Cooling Fan Connector
User's Manual 15
Chapter3Memory Configuration
The HOT-557 mainboard provides four 72-pin SIMM sockets and two 168-
pin DIMM sockets that make it possible to install up to 128MB of RAM.
The SIMM socket support 4MB, 8MB, 16MB, and 32MB 5V single- or
double-side fast page or EDO DRAM modules, and DIMM socket support
8MB, 16MB, . . ., 3.3V single- or double-side SDRAM, fast page, or EDO
modules.
Caution : The user should not populate both 5V SIMM modules & 3.3V
DIMM modules at the same time.
The four SIMM sockets are arranged in two banks of two sockets each, the
two DIMM socket are also arranged in two banks of one socket each. Each
bank provides a 64/72-bit wide data path.
Both SIMMs in a bank must be of the same memory size and type, although
the different types of memory may differ between banks. It is possible to
have 70 ns fast page DRAM in one bank and 60 ns EDO DRAM in the other.
The memory configuration tables on next two pages liste the SIMMs and
DIMMs memory configuration.
User's Manual 16
SIM1SIM2SIM3SIM4DIM1DIM2TOTAL
4MB4MB—— —— —— —— 8MB
—— —— 4MB4MB—— —— 8MB
4MB4MB4MB4MB—— —— 16 MB
8MB8MB—— —— —— —— 16 MB
—— —— 8MB8MB—— —— 16 MB
4MB4MB8MB8MB—— —— 24 MB
8MB8MB4MB4MB—— —— 24 MB
8MB8MB8MB8MB—— —— 32 MB
16 MB16 MB—— —— —— —— 32 MB
—— —— 16 MB16 MB—— —— 32 MB
4MB4MB16 MB16 MB—— —— 40 MB
16 MB16 MB4MB4MB—— —— 40 MB
8MB8MB16 MB16 MB—— —— 48 MB
16 MB16 MB8MB8MB—— —— 48 MB
16 MB16 MB16 MB16 MB—— —— 64 MB
32 MB32 MB—— —— —— —— 64 MB
—— —— 32 MB32 MB—— —— 64 MB
4MB4MB32 MB32 MB—— —— 72 MB
32 MB32 MB4MB4MB—— —— 72 MB
8MB8MB32 MB32 MB—— —— 80 MB
32 MB32 MB8MB8MB—— —— 80 MB
16 MB16 MB32 MB32 MB—— —— 96 MB
32 MB32 MB16 MB16 MB—— —— 96 MB
32 MB32 MB32 MB32 MB—— —— 128 MB
—— —— —— —— 8MB—— 8MB
—— —— —— —— 8MB8MB16 MB
—— —— —— —— 16 MB—— 16 MB
—— —— —— —— 8MB16 MB24 MB
—— —— —— —— 16 MB16 MB32 MB
—— —— —— —— 32 MB—— 32 MB
—— —— —— —— 8MB32 MB40 MB
—— —— —— —— 16 MB32 MB48 MB
—— —— —— —— 32 MB32 MB64 MB
Table 3-1. Memory Configuration Table
User's Manual 17
HOT-557 BIOS ROM has a built-in Setup program that allows users to
modify the basic system configuration. This type of information is stored in
battery-backed RAM so that it retains the Setup information when the
power is turned off.
Entering Setup
Power on the computer and press <Del> immediately will allow you to
enter Setup. The other way to enter Setup is to power on the computer,
when the below message appear briefly at the bottom of the screen
during the POST (Power On Self Test), press <Del> key or
simultaneously press <Ctrl>,<Alt>, and <Esc> keys.
TO ENTER SETUP BEFORE BOOT PRESS CTRL-ALT-ESC OR DEL KEY
If the message disappears before you respond and you still wish to enter
Setup, restart the system to try again by turning it OFF the ON or
pressing the "RESET" button on the system case. You may also restart
by simultaneously press <Ctrl>,<Alt>, and <Delete> keys. If you do not
press the keys at the correct time and the system does not boot, an error
message will be displayed and you will again be asked to,
PRESS F1 TO CONTINUE, CTRL-ALT-ESC OR DEL TO ENTER SETUP
Chapter4Award BIOS Setup
User's Manual 18
The Main Menu
Standard CMOS setup
This setup page includes all the items in a standard compatible BIOS.
BIOS features setup
This setup page includes all the items of Award special enhanced features.
Chipset features setup
This setup page includes all the items of chipset features.
Power Management Setup
This setup page includes all the items of Power Management features.
PCI Configuration setup
This item specifies the value (in units of PCI bus blocks) of the latency
timer for the PCI bus master and the IRQ level for PCI device. Power-on
with BIOS defaults
Load BIOS Defaults
BIOS defaults loads the values required by the system for the maximum
performance. However, you may change the parameter through each Setup
Menu.
User's Manual 19
Load Setup Defaults
Setup defaults loads the values required by the system for the O.K.
performance. However, you may change the parameter through each Setup
Menu.
Integrated Peripherals
This setup page includes all the items of peripheral features.
IDE HDD auto detection
Automatically configure IDE hard disk drive parameters.
Supervisor Password
Change, set, or disable supervisor password. It allows you to limit access to
the system and Setup, or just to Setup.
User Password
Change, set, or disable user password. It allows you to limit access to the
system and Setup, or just to Setup.
Save & Exit setup
Save CMOS value change to CMOS and exit setup
Exit without saving
Abandon all CMOS value changes and exit setup.
User's Manual 20
Standard CMOS Setup
Date
The date format is <day>, <month> <date> <year>. Press <F3> to show the
calendar.
Time
The time format is <hour> <minute> <second>. The time is calculated base
on the 24-hour military-time clock. For example. 5 p.m. is 17:00:00.
Drive C type/Drive D type
This item identify the types of hard disk drive C and drive D that has been
installed in the computer. There are 46 predefined types and a user
definable type.
Press PgUp or PgDn to select a numbered hard disk type or type the number
and press <Enter>. Note that the specifications of your drive must match
with the drive table. The hard disk will not work properly if you enter
improper information for this item. If your hard disk drive type is not
matched or listed, you can use Type User to define your own drive type
manually.
If you select Type User, related information is asked to be entered to the
following items. Enter the information directly from the keyboard and press
<Enter>. Those information should be provided in the documentation from
your hard disk vendor or the system manufacturer.
Table of contents
Other Steren Motherboard manuals
