Steren HOT-557 User manual

User's Manual 1
HOT-557
Layout-Version 1.5
Pentium™processor
Based PCI MAIN BOARD
User's Manual

FCC Notice:
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of
FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy. If not installed and used properly, in
strict accordance with the manufacturer’s instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause
interference to radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures :
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/television technician for help and for additional suggestions.
The user may find the following booklet prepared by the Federal Communications Commission helpful “How to Identify
and Resolve Radio-TV Interference Problems.” This booklet is available from the U.S. Government Printing Office.
Washington, DC 20402, Stock 004-000-00345-4
FCC Warning
The user is cautioned that changes or modifications not expressly approved by the manufacturer could void the user’s
authority to operate this equipment.
Note : In order for an installation of this product to maintain compliance with the limits for a Class B device, shielded
cables and power cord must be used.
NOTICE
Copyright 1997.
All Right Reserved
Manual Ver 3.0
All information, documentation, and specifications contained in this manual are subject to change without prior
notification by the manufacturer.
The author assumes no responsibility for any errors or omissions which may appear in this document nor does it
make a commitment to update the information contained herein.
TRADEMARKS
Intel is a registered trademark of Intel Corporation
PentiumProcessor is a registered trademark of Intel Corporation
PC/AT is a registered trademark of International Business Machine Corporation.
PS/2 is a registered trademark of IBM Corporation.
All other brand and product names referred to in this manual are trademarks or registered trademarks of their
respective holders.
CE Notice:
Following standards were applied to this product, in order to achieve compliance
with the electromagnetic compatibility:
- Immunity in accordance with EN 50082-1: 1992
- Emmitions in accordance with EN 55022: 1987 Class B.

User's Manual 3
TABLE OF CONTENTS
PREFACE ............................................................................................ 4
CHAPTER 1 INTRODUCTION.................................................................. 5
Specification.......................................................................................................5
CHAPTER 2 HARDWARE CONFIGURATION............................................... 7
Jumpers ...............................................................................................................7
CPU Clock Speed Selection..............................................................................8
Onboard Regulators Output - J100, J101, J102, J107................................10
Pipeline Burst Type Cache Size Selection - JP29, JP30.............................11
Flash EPROM Jumper - JP19.........................................................................12
Clear CMOS - JP21.........................................................................................12
Clear Password - JP9.......................................................................................13
Display Mode Jumper - JP7............................................................................13
Factory Reserved Jumpers - JP39, JP43, JP44.............................................13
Connectors & Sockets......................................................................................14
CHAPTER 3 MEMORYCONFIGURATION ............................................... 15
CHAPTER 4 AWARD BIOS SETUP....................................................... 17
The Main Menu................................................................................................18
Standard CMOS Setup....................................................................................20
BIOS Features Setup.......................................................................................22
Chipset Features Setup....................................................................................24
Power Management Setup...............................................................................27
PCI Configuration Setup.................................................................................29
Integrated Peripherals......................................................................................31
Password Setting..............................................................................................33

User's Manual 4
HOT-557 mainboard is a highly integrated IBM PC/AT compatible system
board. The design will accept Intel Pentium, Cyrix/IBM 6x86/L and AMD K5
processors and also features high-performance pipeline burst secondary cache
memory support with size of 256KB and 512KB. The memory subsystem is
designed to support up to 128 MB of EDO RAM, Standard Fast Page DRAM
and SDRAM in standard 72-pin SIMM socket and 168-pin 3.3 V DIMM
socket. A type 7 Pentium processor socket provides access to future processor
enhancements.
HOT-557 provides a new level of I/O integration. Intel's 82430VX PCIset
chipset provides increased integration and improved performance over other
chipset designs. The 82430VX PCIset chipset provides an integrated Bus
Mastering IDE controller with two high performance IDE interfaces for up to
four IDE devices.
The onboard Super I/O controller provides the standard PC I/O functions:
floppy interface, two FIFO serial ports, an IrDA device port and a SPP/EPP/
ECP capable parallel port.
Up to four PCI local bus slots provide a high bandwidth data path for data-
movement intensive functions such as graphics, and up to three ISA slots
complete the I/O function.
The HOT-557 provides the foundation for cost effective, high performance,
highly expandable platforms, which deliver the latest in Pentium processor and
I/O standard
Preface

User's Manual 5
Chapter1 Introduction
Specification
CPU Function
Pentium processors : 75~200MHz
Cyrix/IBM 6x86/L processors : P120+~P166+
AMD K5 processors : PR75~PR166
Chipset
Intel PCIset 82437VX, 82438VX and 82371SB
Memory
Supports two banks of EDO, Fast Page Mode DRAM or
3.3V Sync. DRAM ranging from 8MB to 128MB
Supports 4MB, 8MB, 16MB, 32MB 72-pins SIMMs or
8MB, 16MB, 32MB 168-pin DIMMs
Cache Memory
Integrated L2 write-back cache controller
- 256KB or 512KB Direct Mapped Pipeline Burst Cache
Power Management Function
Provides four power management modes : Full on, Doze,
Standby, and Suspend
Supports Microsoft APM
Provides EPMI (External Power Management Interrupt) pin