STMicroelectronics STEVAL-IME008V1 User manual

For further information contact your local STMicroelectronics sales office.
August 2015 DocID026791 Rev 2 1/19
STEVAL-IME008V1
STHV749 Ultrasound Pulser IC evaluation board
Data brief
Features
•4-channel outputs: high voltage and low
voltage BNC connectors
•Load simulator using signal equivalent circuits
•Possibility to set up own load simulator
•16 preset waveforms
•USB connector to connect STM32 with PC and
supply power to it
•4 MB serial Flash memory to host FPGA code
and waveforms
•Memory expansion connector to add external
serial Flash
•Connectors to supply high voltage and low
voltage to the STHV749 output stage
•LEDs to monitor the power management stage
•Human machine interface to select, start and
stop the generation of the preset waveforms
•25 LEDs to monitor board behavior
•RoHS compliant
Description
The STEVAL-IME008V1 is a product evaluation
board designed around the STHV749 4-channel
7-level high voltage pulser, a state-of-the-art
device designed for ultrasound imaging
applications.
The output waveforms can be displayed directly
on an oscilloscope by connecting the scope probe
to the relative BNCs. 16 preset waveforms are
available to test the HV pulser under varying
conditions.
www.st.com

Schematic diagrams STEVAL-IME008V1
2/19 DocID026791 Rev 2
1 Schematic diagrams
Figure 1. STEVAL-IME008V1 circuit schematic (1 of 16)
DATAOUT0 DATAOUT1 DATAOUT2 DATAOUT3 DATAOUT4
DATAOUT5
DATAOUT6 DATAOUT7
DATAOUT8
DATAOUT9 DATAOUT10 DATAOUT11
DATAOUT[0:15]
MCU_FPGA_GPIO[0:7]
DATAOUT12
DATAOUT13
HVPCW
DVDD VDDP HVP0
HVMCWVDDM HVM0
DVDD VDDP VDDM HVP0 HVP1 HVPCW HVM0 HVM1 HVMCW
HVM1
HVP1
FPGA_BLK FPGA
THSD_EN
FPGA_SPI_CCLK
FPGA_SPI_MOSI
FPGA_SPI_MISO1 FPGA_SPI_MISO2
FPGA_SPI_MISO3 FPGA_SPI_SEL
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
DATAOUT[0:15]
CW
CK
MCU_FPGA_GPIO[0:7] MCU_FPGA_PROG MCU_FPGA_INIT_B MCU_FPGA_MODE1 FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE MCU_FPGA_SUSPEND
BOARD_POWER_BLK
BOARD_POWER
HVP0
DVDD
VDDP
VDDM
HVM0
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
FLASH_3V3
USB_DISCONNECT
USB_DM
USB_DP
MCU_3V3
HVPCW
HVMCW
HVP1
HVM1
STM32_FLASH_BLK
STM32_FLASH
FLASH_C
FLASH_DQ0
FLASH_nS
FLASH_DQ2 FLASH_DQ3 FLASH_DQ1
USB_DISCONNECT
USB_DM
USB_DP
MCU_FPGA_PROG
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
FPGA_MCU_AWAKE
MCU_FPGA_SUSPEND
FLASH_3V3
MCU_3V3
FPGA_GPIO[0:7]
STHV749_BLK
STHV749
DVDD
VDDP
VDDM
IN1_0
IN1_1
IN4_0 IN3_1 IN4_1 CW THSD_EN
CK
IN2_0 IN3_0 IN2_1
HVM_CW
HVP_CW
HVP1
IN2_2 IN3_2
HVM0
IN4_2
HVM1
IN1_2
HVP0
SEL
GSPG30072014DI1135

DocID026791 Rev 2 3/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 2. STEVAL-IME008V1 circuit schematic (2 of 16)
SOT23-5L
C7 Details: Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K) Package 0402
USB
C8 Details:
DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA)
Package 0603
SOTT323-6L
RS (515-1995)
Molex (54819-0572)
Kingbright KP2012SURC
RS: 466-3829 Farnell: 8529930
LED 0805
USB ON
DM DP
DP
DM
USBDP USBDM
USB_DISCONNECT
USB_DISCONNECT
USBDM
USBDP
USB_3V3
USB_DISCONNECT
USB_DM
USB_DP
USB_5V USB_5V
C3
4.7nF
C8
2.2uF 6.3V
R90 56R
CN1
1
USB_miniB
VBUS DM
2
DP
3
4ID nc
5GND
6SHELL
7SHELL
8SHELL 9SHELL
D26 RED
U1
D1
1
D2 D3
USBUF02W6
Grd
2
34
5
3.3V
D4 6
C11
33nF
R1
1M
C7
1uF
U2
VIN
1
LDS3985M33R
GND
2
3
INH
4BYPS
5
VOUT
GSPG30072014DI1140

Schematic diagrams STEVAL-IME008V1
4/19 DocID026791 Rev 2
Figure 3. STEVAL-IME008V1 circuit schematic (3 of 16)
3.3V Power Management
J4 Details Phoenix Contact (Mfg Code MPT 0.5/2-2.54) RS (220-4260) C12 and C13 Detail TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND) Dimension 0603 - EIA 1608
C14 Detail
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
L1 Detail TDK (VLF4012AT-2R2M1R5) - RS (614-3147)
NOT ASSEMBLY
MCU
FPGA
3V3 Connector
3V3
SW1 Details:
SW1
RS 711-8329
KNITTER-SWITCH (MMS228T)
USB_3V3
EXT_3V3
MCU_3V3
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
FLASH_3V3FLASH_3V3
EXT_3V3 DVDD
D27 RED
J4
1 2
L1 2.2uH
C12
4u7
6.3V
MMS228T
2COM_1a 7
COM_1b
3ON_2a 6
ON_2b
1ON_1a 8
ON_1b
nc
4nc 5
U3
ST1S12xx
Vin
4
5
FB/VoEN
1
2GND
SW 3
C13
4u7
6.3V
R124
56
C14 10u 10V
R125 56
J41
1 2
D28
RED
D1
SM2T3V3A
GSPG30072014DI1150

DocID026791 Rev 2 5/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 4. STEVAL-IME008V1 circuit schematic (4 of 16)
STHV800 Power Management
MKDS 1.5/2-5.08)
J2 Details
RS 2X(193-0564)
Phoenix Contact
(Mfg Code
C1, C2, C9, C10, C15, C16 Details:
GND_POWER
Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M)
Package 6.5mm x 5.5 mm
C4, C5, C6 Details:
Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M)
Package 1210 - EIA 3225
DVDD
VDDP
GND
HVPCW
HVP1
HVP0
GND
VDDM
HVMCW
HVM1
HVM0
GND
LOW POWER- HIGH VOLTAGE + HIGH VOLTAGE
J1 Details
RS 2X(193-0564)
Phoenix Contact
(Mfg Code
MKDS 1.5/2-5.08)
J3 Details
RS 2X(193-0564)
Phoenix Contact
(Mfg Code
HVPCW
HVP0
DVDD
VDDP
VDDM
HVP1
HVMCW
HVM0
HVM1
HVPCW
HVP0
DVDD
VDDP
VDDM
HVMCW
HVM0
HVP1
HVM1
GND_POWER
MKDS 1.5/2-5.08)
GND_POWER
GND_POWER GND_SHIELD
R2
0
C9
100V
22000n 100V
0
R123
C2
100V
22000n 100V
J2 LV
1
2
3
4
C4
16V
22000n 16V
C79
100V
22000n 100V
C6
16V
22000n 16V
C78
100V
22000n 100V
C10
100V
22000n 100V
C5
16V
22000n 16V
22000n 100V
C1
100V
J3 HVM
1
2
3
4
J1 HVP
1
2
3
4
GSPG30072014DI1155

Schematic diagrams STEVAL-IME008V1
6/19 DocID026791 Rev 2
Figure 5. STEVAL-IME008V1 circuit schematic (5 of 16)
Jumper J5 is used to control I/O pullups during FPGA configuration.
Diff. pair Diff. pair
Diff. pair
Diff. pair
Diff. pair Diff. pair
Diff. pair Diff. pair Diff. pair
Diff. pair
Diff. pair
Open (default) to float I/O output during FPGA configuration.
Set jumper 1:2 to enable I/O pullups during FPGA configuration.
Diff. pair
Diff. pair
Diff. pair
Diff. pair Diff. pair
Diff. pair
Diff. pair
C16 and C17 Details: TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND) Dimension 0805 - EIA 2012
Jumpers J35, J36 and J37 are used to set dataout output state. Configure J35 and J36 to setup outputs idle state as follows:
NOT ASSEMBLY
NOT ASSEMBLY
NOT ASSEMBLY
THESE JUMPERS
HSWAPEN
Open J37 (default) to connect FPGA outputs Close J37 to disconnect outputs (High-Z)
00 - (J35 and J36 open) --> High-Z (default)
01 - (J35 closed and J36 open) --> Clamp/HVR_SW 11 - (J35 and J36 closed) --> High-Z
10 - (J35 open and J36 closed) --> Clamp
IDLE STATE
HEADER 17X2
STHV748 I/O CONNECTOR
FPGA DISCONNECT
DATAOUT0 DATAOUT1
DATAOUT2 DATAOUT3 DATAOUT4 DATAOUT5
DATAOUT6
DATAOUT7 DATAOUT8
DATAOUT9 DATAOUT10
DATAOUT11 DATAOUT12
DATAOUT13
DATAOUT14 DATAOUT15
DATAOUT[0:15]
HSWAPEN
CK
THSD_EN
CW
DATAOUT11 THSD_EN
DATAOUT0
DATAOUT2
DATAOUT4 DATAOUT6 DATAOUT8
DATAOUT10
DATAOUT12
DATAOUT14 DATAOUT1 DATAOUT3
DATAOUT5
DATAOUT7 DATAOUT9
DATAOUT13
CK DATAOUT15
CW
HI_Z
IDLE_STATE1
IDLE_STATE0
THSD_EN
CK CW
DATAOUT[0:15]
+VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
R122
J5
10K 0402
JUMPER
1
2
C15
100n 0402
C16
10uF 10V 0805
J35
12
C17
10uF 10V 0805
J37
1 2
R120
10K 0402
U4A
FPGA - Bank 0
XC6SLX16-2CSG324C
C4
D4
A2 B2 C6 D6 A3
B3
A4
B4
A5
C5 E6 F7 A6
B6
E8
E7 A7 C7 C8 D8
F8
G8
A8
B8 C9 D9 A9 B9
C11
D11 A10 C10
F9
G9
A11 B11
F10
G11 A12 B12 E11 F11 C12 D12
A13
C13
E12
F12 A14 B14
E13
F13 A15
C15
C14 D14 A16 B16
R3 10K 0402
J6
2
4
6
8
10 12
14
16
18 20
22
24
26
28
30
32 34
1
3 5 7 9
11
13 15 17 19 21
23 25
27 29 31
33
R121
10K 0402
C18
100n 0402
J36
1 2
IO_0_L01N_VREF
IO_0_L01P_HSWAPEN
IO_0_L02N
IO_0_L02P
IO_0_L03N
IO_0_L03P
IO_0_L04N
IO_0_L04P
IO_0_L05N
IO_0_L05P
IO_0_L06N
IO_0_L06P
IO_0_L07N
IO_0_L07P
IO_0_L08N_VREF
IO_0_L08P
IO_0_L09N
IO_0_L09P
IO_0_L10N
IO_0_L10P
IO_0_L11N
IO_0_L11P
IO_0_L32N
IO_0_L32P
IO_0_L33N
IO_0_L33P
IO_0_L34N_GCLK18
IO_0_L34P_GCLK19
IO_0_L35N_GCLK16
IO_0_L35P_GCLK17
IO_0_L36N_GCLK14
IO_0_L36P_GCLK15
IO_0_L37N_GCLK12
IO_0_L37P_GCLK13
IO_0_L38N_VREF
IO_0_L38P
IO_0_L39N
IO_0_L39P
IO_0_L40N
IO_0_L40P
IO_0_L41N
IO_0_L41P
IO_0_L42N
IO_0_L42P
IO_0_L47N
IO_0_L47P
IO_0_L50N
IO_0_L50P
IO_0_L51N
IO_0_L51P
IO_0_L62N_VREF
IO_0_L62P
IO_0_L63N_SCP6
IO_0_L63P_SCP7
IO_0_L64N_SCP4
IO_0_L64P_SCP5
IO_0_L65N_SCP2
IO_0_L65P_SCP3
IO_0_L66N_SCP0
IO_0_L66P_SCP1
GSPG30072014DI1200

DocID026791 Rev 2 7/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 6. STEVAL-IME008V1 circuit schematic (6 of 16)
NOT ASSEMBLY
FPGA USER I/O
STOP_PB
FPGA_RESET
CTRL_LED1
CTRL_LED0
SEL_PROG_PB
FPGA_CLK_66MHZ
START_PB
FPGA_DOUT_BUSY
FPGA_AWAKE
FPGA_USER_IO_10
FPGA_USER_IO_11
FPGA_USER_IO_12
FPGA_USER_IO_13
FPGA_USER_IO_14
FPGA_USER_IO_15
CTRL_LED3
CTRL_LED2
FPGA_PMOD1_P2
FPGA_PMOD1_P1
FPGA_PMOD1_P4
FPGA_PMOD1_P3
FPGA_PMOD1_P8
FPGA_PMOD1_P7
FPGA_PMOD1_P10
FPGA_PMOD1_P9
FPGA_PMOD2_P2
FPGA_PMOD2_P1
FPGA_PMOD2_P4
FPGA_PMOD2_P3
FPGA_PMOD2_P8
FPGA_PMOD2_P7
FPGA_PMOD2_P10
FPGA_PMOD2_P9
FPGA_USER_IO_0
FPGA_USER_IO_1
FPGA_USER_IO_2
FPGA_USER_IO_3
FPGA_USER_IO_4
FPGA_USER_IO_5
FPGA_USER_IO_6
FPGA_USER_IO_7
FPGA_USER_IO_8
FPGA_USER_IO_9
FPGA_MCU_AWAKE
TP1
1
TEST POINT
J7
HEADER 16X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
U4B
FPGA - Bank 1
XC6SLX16-2CSG324C
F16
F15
C18
C17
G14
F14
D18
D17
G13
H12
E18
E16
K13
K12
F18
F17
H14
H13
H16
H15
G18
G16
K14
J13
L13
L12
K16
K15
L16
L15
H18
H17
J18
J16
K18
K17
L18
L17
M18
M16
N18
N17
P18
P17
N16
N15
T18
T17
U18
U17
N14
M14
M13
L14
P16
P15
IO_1_L01N_A24_VREF
IO_1_L01P_A25
IO_1_L29N_A22_M1A14
IO_1_L29P_A23_M1A13
IO_1_L30N_A20_M1A11
IO_1_L30P_A21_M1RESET
IO_1_L31N_A18_M1A12
IO_1_L31P_A19_M1CKE
IO_1_L32N_A16_M1A9
IO_1_L32P_A17_M1A8
IO_1_L33N_A14_M1A4
IO_1_L33P_A15_M1A10
IO_1_L34N_A12_M1BA2
IO_1_L34P_A13_M1WE
IO_1_L35N_A10_M1A2
IO_1_L35P_A11_M1A7
IO_1_L36N_A8_M1BA1
IO_1_L36P_A9_M1BA0
IO_1_L37N_A6_M1A1
IO_1_L37P_A7_M1A0
IO_1_L38N_A4_M1CLKN
IO_1_L38P_A5_M1CLK
IO_1_L39N_M1ODT
IO_1_L39P_M1A3
IO_1_L40N_GCLK10_M1A6
IO_1_L40P_GCLK11_M1A5
IO_1_L41N_GCLK8_M1CASN
IO_1_L41P_GCLK9_IRDY1_M1RASN
IO_1_L42N_GCLK6_TRDY1_M1LDM
IO_1_L42P_GCLK7_M1UDM
IO_1_L43N_GCLK4_M1DQ5
IO_1_L43P_GCLK5_M1DQ4
IO_1_L44N_A2_M1DQ7
IO_1_L44P_A3_M1DQ6
IO_1_L45N_A0_M1LDQSN
IO_1_L45P_A1_M1LDQS
IO_1_L46N_FOE_B_M1DQ3
IO_1_L46P_FCS_B_M1DQ2
IO_1_L47N_LDC_M1DQ1
IO_1_L47P_FWE_B_M1DQ0
IO_1_L48N_M1DQ9
IO_1_L48P_HDC_M1DQ8
IO_1_L49N_M1DQ11
IO_1_L49P_M1DQ10
IO_1_L50N_M1UDQSN
IO_1_L50P_M1UDQS
IO_1_L51N_M1DQ13
IO_1_L51P_M1DQ12
IO_1_L52N_M1DQ15
IO_1_L52P_M1DQ14
IO_1_L53N_VREF
IO_1_L53P
IO_1_L61N
IO_1_L61P
IO_1_L74N_DOUT_BUSY
IO_1_L74P_AWAKE
GSPG30072014DI1205

Schematic diagrams STEVAL-IME008V1
8/19 DocID026791 Rev 2
Figure 7. STEVAL-IME008V1 circuit schematic (7 of 16)
Place R7 (1%) close to the clock
source DS1088LU-66 device
PERIPHERRAL MODULE (PMOD)
66MHZ EXTERNAL OSCILLATOR
DX
SX
BACKUP OF U5
NOT ASSEMBLY
NOT ASSEMBLY
C26, C27, C30 and C31 Detail
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
PMOD2
PMOD1
66MHZ OSC
When using backup oscillator X1,
R126 have to be mounted and R6
must be unplaced.
FPGA_PMOD1_P2
FPGA_PMOD1_P4
FPGA_PMOD1_P1
FPGA_PMOD1_P3
FPGA_PMOD1_P7 FPGA_PMOD1_P8
FPGA_PMOD1_P10
FPGA_PMOD1_P9
FPGA_PMOD2_P2
FPGA_PMOD2_P4
FPGA_PMOD2_P1
FPGA_PMOD2_P3
FPGA_PMOD2_P7 FPGA_PMOD2_P8
FPGA_PMOD2_P10FPGA_PMOD2_P9
FPGA_CLK_66MHZ
MCU_FPGA_OSC_EN
MCU_FPGA_OSC_EN
+VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3 +VFPGA_IO_3V3
C28
100nF
J9
HEADER 6X2
2
4
6
8
10
12
1
3
5
7
9
11
X1
1OE ST
GND
2
4
VCC
3
OUT
C25
100nF
C27
10uF 10V 0805
C20
10nF
C29
100nF
C19
100nF
C30
R6
10uF 10V 0805
10K NM
C32
100nF
R7
33R2
R126
10k
C31
10uF 10V 0805
C26
10uF 10V 0805
U5
2VCC
DS1088LU-66
VCC
3
7n/c
n/c
8
1OUT
4
GND
5
GND
PDN 6
J8
HEADER 6X2
2
4
6
8
10
12
1
3
5
7
9
11
Two right-angle, 12-pin
(2 x 6 female) Peripheral
Module (PMOD) headers
(J8, J9) are interfaced to
the FPGA, with each
header providing 3.3 V
power, ground, and
eight I/O's. These headers
may be utilized as
general-purpose I/Os
or may be used to
interface to PMODs.
J6 and J8 are placed in
close proximity
(0'9" -centers) on the
PCB in order to
support dual PMODs.
GSPG30072014DI1210

DocID026791 Rev 2 9/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 8. STEVAL-IME008V1 circuit schematic (8 of 16)
SW2, SW3, SW4, Details RS (378-6527)
PUSHBUTTONS
CTRL LED
GREEN LED
Kingbright KP2012SURC
RS: 466-3778
Farnell: 8529906
LED 0805
Near START button
Near STOP button
IDLE state signal
ERROR signal
PROGRAM
STOP
FPGA RESET
START
IDLE
ERROR
RED LED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
CTRL_LED0
CTRL_LED2
CTRL_LED1
CTRL_LED3
FPGA_RESET
START_PB
SEL_PROG_PB
STOP_PB
+VFPGA_IO_3V3 +VFPGA_IO_3V3
+VFPGA_IO_3V3 +VFPGA_IO_3V3
D3
GREEN
R10
56R 0402
R9
10K 0402
R12
56R 0402
SW3
R11
SW PUSHBUTTON-DPST
56R 0402
C22
100nF
D4
GREEN
R5
10K 0402
C24
100nF
R8
10K 0402
R4
10K 0402
SW2
SW PUSHBUTTON-DPST
C21
100nF
D2
GREEN
R13
56R 0402
D5
RED
SW4
SW PUSHBUTTON-DPST
C23
100nF
SW5
SW PUSHBUTTON-DPST
GSPG30072014DI1215

Schematic diagrams STEVAL-IME008V1
10/19 DocID026791 Rev 2
Figure 9. STEVAL-IME008V1 circuit schematic (9 of 16)
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
PROG_LED10
PROG_LED11
PROG_LED2
PROG_LED3
PROG_LED6
PROG_LED7
PROG_LED0
PROG_LED1
PROG_LED4
PROG_LED5
PROG_LED8
PROG_LED9
FPGA_MODE0
CCLK
FPGA_SPI_MISO1
PROG_LED14
PROG_LED15
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
PROG_LED12
PROG_LED13
FPGA_SPI_MISO2
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_INIT_B
FPGA_SPI_MISO3
FPGA_MODE1
MCU_FPGA_GPIO[0:7]
MCU_FPGA_GPIO0
MCU_FPGA_GPIO1
MCU_FPGA_GPIO2
MCU_FPGA_GPIO3
MCU_FPGA_GPIO4
MCU_FPGA_GPIO5
MCU_FPGA_GPIO6
MCU_FPGA_GPIO7
MCU_FPGA_GPIO[0:7]
U4C
FPGA - Bank 2
XC6SLX16-2CSG324C
T15
R15
V16
U16
T13
R13
V15
U15
V14
T14
P12
N12
V13
U13
N11
M11
T11
R11
V12
T12
P11
N10
N9
M10
V11
U11
T10
R10
V10
U10
T8
R8
V9
T9
N8
M8
V8
U8
V7
U7
P8
N7
V6
T6
T7
R7
P7
N6
T5
R5
V5
U5
T3
R3
V4
T4
P6
N5
V3
U3
TP2
1
TEST POINT
IO_2_L01N_M0_CMPMISO
IO_2_L01P_CCLK
IO_2_L02N_CMPMOSI
IO_2_L02P_CMPCLK
IO_2_L03N_MOSI_CSI_B_MISO0
IO_2_L03P_D0_DIN_MISO_MISO1
IO_2_L05N
IO_2_L05P
IO_2_L12N_D2_MISO3
IO_2_L12P_D1_MISO2
IO_2_L13N_D10
IO_2_L13P_M1
IO_2_L14N_D12
IO_2_L14P_D11
IO_2_L15N
IO_2_L15P
IO_2_L16N_VREF
IO_2_L16P
IO_2_L19N
IO_2_L19P
IO_2_L20N
IO_2_L20P
IO_2_L22N
IO_2_L22P
IO_2_L23N
IO_2_L23P
IO_2_L29N_GCLK2
IO_2_L29P_GCLK3
IO_2_L30N_GCLK0_USERCCLK
IO_2_L30P_GCLK1_D13
IO_2_L31N_GCLK30_D15
IO_2_L31P_GCLK31_D14
IO_2_L32N_GCLK28
IO_2_L32P_GCLK29
IO_2_L40N
IO_2_L40P
IO_2_L41N_VREF
IO_2_L41P
IO_2_L43N
IO_2_L43P
IO_2_L44N
IO_2_L44P
IO_2_L45N
IO_2_L45P
IO_2_L46N
IO_2_L46P
IO_2_L47N
IO_2_L47P
IO_2_L48N_RDWR_B_VREF
IO_2_L48P_D7
IO_2_L49N_D4
IO_2_L49P_D3
IO_2_L62N_D6
IO_2_L62P_D5
IO_2_L63N
IO_2_L63P
IO_2_L64N_D9
IO_2_L64P_D8
IO_2_L65N_CSO_B
IO_2_L65P_INIT_B
GSPG30072014DI1220

DocID026791 Rev 2 11/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 10. STEVAL-IME008V1 circuit schematic (10 of 16)
SPI EXTERNAL PROGRAMMING HEADER
SPI FLASH CTRL SIGNALS
Place R38 close to the FPGA device
FPGA CONFIGURATION
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
TO CORRECT
EXT SPI
FLASH
Place D29
close to J10
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a configuration data
error has occurred.
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_MODE0
FPGA_INIT_B
FPGA_MODE1
FPGA_SPI_MISO3
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
+VFPGA_IO_3V3
+VFPGA_IO_3V3
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
D29
GREEN
R22
2K43 0402
56
R127
R38 33R2 0402
R21
R18
2K43 0402 DNP
J10
2K43 0402 DNP
CON10
10
1
2
3
4
5
6
7
8
9
C34
100nF
R17
2K43 0402
R16
10K 0402
R39
NA 0402
C33
10uF 10V 0805
R40
NA 0402
GSPG30072014DI1230

Schematic diagrams STEVAL-IME008V1
12/19 DocID026791 Rev 2
Figure 11. STEVAL-IME008V1 circuit schematic (11 of 16)
Kingbright KP-3216SYC
RS: 466-3942
LED 0805
PROGRAM SELECTOR LEDS
PROG 0
PROG 1
PROG 2
PROG 3
PROG 4
PROG 5
PROG 6
PROG 7
PROG 8
PROG 9
PROG 10
PROG 11
PROG 12
PROG 13
PROG 14
PROG 15
PROG_LED12
PROG_LED14
PROG_LED13
PROG_LED15
PROG_LED8
PROG_LED10
PROG_LED9
PROG_LED11
PROG_LED4
PROG_LED6
PROG_LED5
PROG_LED7
PROG_LED0
PROG_LED2
PROG_LED1
PROG_LED3
R24
68R 0402
D13
YELLOW
D11
YELLOW
D14
YELLOW
R15
68R 0402
R19
68R 0402
R31
68R 0402
D15
YELLOW
D18
YELLOW
R34
68R 0402
R27
68R 0402
D6
YELLOW
D21
YELLOW
D12
YELLOW
R23
68R 0402
D10
YELLOW
R14
68R 0402
R28
68R 0402
D17
YELLOW
R33
68R 0402
D20
YELLOW
R32
68R 0402
D19
YELLOW
R30
68R 0402
D9
YELLOW
R25
68R 0402
D16
YELLOW
R20
68R 0402
R26
68R 0402
R29
68R 0402
D7
YELLOW
D8
YELLOW
GSPG30072014DI1235

DocID026791 Rev 2 13/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 12. STEVAL-IME008V1 circuit schematic (12 of 16)
FPGA BANK 3
NOT USED
DONEPROGRAM_B
Jumper J12
FPGA into
1:2 to force
mode.
suspend mode. to control
2:3 (Default) to allow MCU
FPGA suspend
FPGA JTAG
0805
SUSPEND & CMPCS_B
4-Resistor Array 3.2x1.6mm Not Assembly
CON14A Xilinx Parallel IV Connector
2.0mm 7x2 shrouded header
Jumper J13 used to prevent FPGA from
programming from configuration source.
Set 1:2 to disable FPGA programming. Open (default) to enable FPGA programming.
C35, C40, C51, C58, C66 Details
Murata (GRM31CR60J107ME39L) - Digikey (490-4539-1-NDT)
Dimension 1206 - EIA 3216
near U3
near U6
To be placed
To be placed
RESDIP4X1206
NOT ASSEMBLY
NOT ASSEMBLY
SUSPEND
FPGA PROG DISABLE
DONE
FPGA JTAG
FPGA PROG
NOT ASSEMBLY
NOT ASSEMBLY
NOT ASSEMBLY NOT ASSEMBLY
XC6SLX16-3CSG324C
C36, C37, C38, C41, C42, C52, C53, C59, C60, C67, C68 Details
DK (C1608X5R0J475K) - Digikey (445-5178-2-ND)
Dimension 0603 - EIA 1608
FPGA_PROG
FPGA_DONE
FPGA_PROG
FPGA_SUSPEND
FPGA_DONE FPGA_CMP_CS_B
FPGA_TDI
FPGA_TMS
FPGA_TCK
+VFPGA_IO_3V3 +VFPGA_CORE_1V2
FPGA_TDO
MCU_FPGA_PROG
FPGA_MCU_DONE
MCU_FPGA_SUSPEND
+VFPGA_IO_3V3
+VFPGA_CORE_1V2
+VFPGA_IO_3V3
+VFPGA_IO_3V3 +VFPGA_IO_3V3
+VFPGA_IO_3V3 +VFPGA_CORE_1V2
+VFPGA_IO_3V3 +VFPGA_IO_3V3
+VFPGA_IO_3V3
+VFPGA_IO_3V3
R50
10K 0402
C36
C35
4.7uF 6.3V 0603
C64
100uF 6.3V 1206
C62
0.22uF 6.3V 0402
100nF
R49 10K 0402
C63
C38
0.22uF 6.3V 0402
C61
4.7uF 6.3V 0603
R52
0.22uF 6.3V 0402
330 0402
C60
R48
4.7uF 6.3V 0603
10K 0402
R51
56R
C56 0.22uF 6.3V 0402
D23
GREEN
C45
C55
0.22uF 6.3V 0402
C59
0.22uF 6.3V 0402
4.7uF 6.3V 0603
R44 49R 0402
C69
C53
0.22uF 6.3V 0402
0
R47
4.7uF 6.3V 0603
C48
C58
0.22uF 6.3V 0402
J12
100uF 6.3V 1206
Header 3
1
2
3
C54 C43 0.22uF 6.3V 0402
C52
0.22uF 6.3V 0402
C42
4.7uF 6.3V 0603
R45
4.7uF 6.3V 0603
10K 0402
C71
0.22uF 6.3V 0402
Q1 2N7002
C51 100uF 6.3V 1206
U6
1
74V1G32CTR
2
4
53
J13 JUMPER
1 2
C41
C47
4.7uF 6.3V 0603
C40
0.22uF 6.3V 0402
100uF 6.3V 1206
FPGA - Power & Configuration
TCK
A17
TMS
U4E
XC6SLX16-2CSG324C
B18
TDO
D16
TDI
D15
V2 PROGRAM_B_2
R16 SUSPEND
DONE_2
V17
P13 CMPCS_B_2
VCCO_0 B10
VCCO_0 B15
B5
VCCO_0 VCCO_0 D13
D7
VCCO_0 E10
VCCO_0
VCCO_1 E17
VCCO_1 G15
VCCO_1 J14
VCCO_1 J17
VCCO_1 M15
R17
VCCO_1
P9
VCCO_2
VCCO_2 R12
R6
VCCO_2
VCCO_2 U14
U4
VCCO_2 U9
VCCO_2
E2
VCCO_3 G4 VCCO_3 J2
VCCO_3 J5
VCCO_3 M4
VCCO_3 R2
VCCO_3
B1
VCCAUX
VCCAUX B17
VCCAUX E14
E5
VCCAUX E9
VCCAUX
VCCAUX G10
VCCAUX J12
K7
VCCAUX M9
VCCAUX
VCCAUX P10
VCCAUX P14
P5
VCCAUX
G7
VCCINT
VCCINT H11
H9
VCCINT
VCCINT J10
J8
VCCINT
VCCINT K11
K9
VCCINT
VCCINT L10
L8
VCCINT
VCCINT M12
M7
VCCINT
GND
A18
GND
B13
GND
C3
GND
D10
GND
D5
GND
B7
GND
C16
GND
G17
GND
G2
GND
G5
GND
H10
GND
H8
GND
J11
GND
J15
GND
J4
GND
E15
GND
G12
GND
K8
GND
L11
GND
L9
GND
M17
GND
M2
GND
M6
GND
N13
GND
R1
GND
R14
GND
R18
GND
R4
GND
R9
GND
T16
GND
U12
GND
U6
GND
V1
GND
V18
GND
K10
GND
J9
GND
A1
RST1
C70
RS (378-6527)
SW PUSHBUTTON-DPST
J11
0.22uF 6.3V 0402
12 3 4 5 6 7 8 910
11 12
13 14
C68
R46
4.7uF 6.3V 0603
10K 0402
C67
C72
4.7uF 6.3V 0603
U7
0.22uF 6.3V 0402
4
2
74LX1G08CTR
1
53
C73
100nF
C66
100uF 6.3V 1206
R41 49R 0402
C49
C65
0.22uF 6.3V 0402
0.22uF 6.3V 0402
RN1 RESISTOR DIP 4
1
2
3
4
8
7
6
5
R42 49R 0402
C44 C46
0.22uF 6.3V 0402
C57
0.22uF 6.3V 0402
0.22uF 6.3V 0402
R43 49R 0402
C50
C39
0.22uF 6.3V 0402
D22
0.22uF 6.3V 0402
STTH102A
C37
4.7uF 6.3V 0603
GSPG30072014DI1240

Schematic diagrams STEVAL-IME008V1
14/19 DocID026791 Rev 2
Figure 13. STEVAL-IME008V1 circuit schematic (13 of 16)
C77, C80, C111, C112 Details
DigiKey (490-1462-2-ND) Murata (GRM188R72A271KA01D)
J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401)
STHV749
THSD
XDCR_1
THSD
J16, J17, J22, J23, J25, J26, J29 and J30 Details Tyco Electronics (1-1337482-0) - RS (420-5401)
XDCR_2 XDCR_3 XDCR_4
LVOUT_1
LVOUT_2
LVOUT_3
CK
LVOUT_4
IN1_0
D1, D2, D3 ,D4, D5, D6, D7, D8 diode DFLS1200 rs-code 708-2324
IN1_1 IN2_0
IN2_1
IN3_0
IN3_1
IN4_0 IN4_1
HVP0
HVP_CW
DVDD
VDDP
VDDM
HVM0
HVM_CW
THSD_EN
DVDD THSD_EN
IN5_0
IN5_1
IN6_0 IN6_1
DVDD
CK
CW
HVP0
HVM0
CK
VDDM
HVP1 HVM1
HVM0
HVM1
IN2_2 IN2_1 IN2_0
IN1_2
IN1_1
IN1_0
CW
IN3_0 IN3_1 IN3_2
IN4_0
IN4_1 IN4_2
SEL
VDDP
SEL
HVP0
HVM0
HVP1
WW
CC
__MM
V V
HH
HVP0
HVP_CW
DVDD VDDP VDDM
CK
THSD_EN
IN1_0 IN1_1 CW IN1_2 IN2_0 IN2_1 IN2_2 IN3_0
IN3_1
IN3_2 IN4_0
IN4_1
IN4_2
HVP0
HVP_CW
HVM0
HVM_CW
HVP1 HVM1
SEL
B2S J17
1 2
C83
220n
C76 20p 0805
D34
DFLS1200 D33
DFLS1200
C93 220n
C90 220n
R54
100
C85 220n
R62
100
U8
STHV749
1XDCR_1
2XDCR_2
3GND_PWR
4HVM0
5HVM0 6HVM0
7HVM1
8HVM1
9HVM1
10 HVM_CW 11 XDCR_3 12 XDCR_4
13 GND_PWR
14 LVOUT_3
15 LVOUT_4
16 GND_PWR
17 IN3_0
18 IN3_1
19 IN3_2
20 IN4_0
21 IN4_1
IN4_2
22
THSD
23
VDDP
24
VDDP 25
AGND 26
VDDM 27
HVP1 28
HVP1 29 HVP1 30
HVP0 31
HVP0 32
HVP0 33
IN1_0 39
IN1_1 40
IN1_2 41
42
IN2_0
43
IN2_1
44
IN2_2
45
GND_PWR
46
LVOUT_1
47
LVOUT_2
48
GND_PWR
CW 38
34
HVP_CW
DGND 35
DVDD 36
CK 37
R55
100
TP3
1
TEST POINT
CX2 220n
CX10 220n
CX11 220n
C80
270p 100V 0603
CX3 220n
C91 220n
C113
270p 100V 0603
CX4 220n
C75 20p 0805
J31
B2S
12
D37
DFLS1200
Jlch4
BNC
1
2
Jch3 BNC
1
2
220n C97
Jlch3
BNC
1
2
D31
DFLS1200
220n CX12
D38
DFLS1200
B2S J16
12
Jlch2
BNC
1
2
B2S J15
12
C92 20p 0805
C87
220n
D36
DFLS1200
J28 B2S
12
D35
DFLS1200
J25
CON3
1
2
3
C86 220n
R59
100k
J20 B2S
1 2
CX8 220n
R58
10k
D32
DFLS1200
C89
220n
CX5 220n
CX7
220n
CX1 220n
C77
R53
100
270p 100V 0603
Jlch1
BNC
1
2
Jch1 BNC
1
2
B2S J14
12
C112
270p 100V 0603
CX6 220n
C102 220n
C101 220n
Jch2
BNC 1
2
C74 20p 0805
220n C95
J21
B2S
1 2
220n CX9
J24
CON3
1 2 3
C88 220n
Jch4
BNC 1
2
GSPG30072014DI1245

DocID026791 Rev 2 15/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 14. STEVAL-IME008V1 circuit schematic (14 of 16)
OPTIONAL FPGA I/O
OPTIONAL FPGA CONFIGURATION SIGNALS
FPGA_GPIO0
FPGA_GPIO1
FPGA_GPIO2
FPGA_GPIO3
FPGA_GPIO4
FPGA_GPIO5
FPGA_GPIO6
FPGA_GPIO7
STM32_GPIO_0
STM32_GPIO_1
STM32_GPIO_2
STM32_GPIO_3
STM32_GPIO_4
STM32_GPIO_5
STM32_GPIO_6
STM32_GPIO_7
FPGA_GPIO[0:7]
STM32_GPIO_8
STM32_GPIO_9
STM32_GPIO_10
STM32_GPIO_11
STM32_GPIO_12
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
STM32_GPIO_13
STM32_GPIO_14
FPGA_GPIO[0:7]
FPGA_MCU_AWAKE
FPGA_MCU_DONE
MCU_FPGA_OSC_EN
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
MCU_FPGA_PROG
MCU_FPGA_SUSPEND
R80 0R - N/A
R75 0R - N/A
R74 0R - N/A
R73 0R - N/A
R89 0R - N/A
R72 0R - N/A
R88 0R - N/A
R71 0R - N/A
R70 0R - N/A
R86 0R - N/A
R69 0R - N/A
R85 0R - N/A
R84 0R - N/A
R83 0R - N/A
R82 0R - N/A
JTAG/SWD
Male Connector 2x5
Pitch 1.27 mm
SAMTEC FTSH-105-01-F-D-K
MCU JTAG
JNTRST
JTDO
JTMS
JTDI
JTCK
RESET#
MCU_3V3
MCU_3V3
R79
10k
R77
10k
1
JP1 JUMPER
2
R76
10k
R78
10k
R87
10k
J40
1
2
SWD/JTAG
34
56
78
9
10
GSPG30072014DI1250

Schematic diagrams STEVAL-IME008V1
16/19 DocID026791 Rev 2
Figure 15. STEVAL-IME008V1 circuit schematic (15 of 16)
MCU
Place near MCU
SPI FLASH
INT SPI FLASH
FLASH DISABLE
C123 Details:
Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)
Package 0402
Use J38 to enable/disable power for SPI flash device.
J38 must be open when using external spi flash device on
connecto J10. Default value closed.
STM32F103
USER_LED1 USER_LED2
BOOT0
BOOT1
OSCIN
FLASH_nS
FLASH_C FLASH_DQ1
FLASH_DQ0 JTMS
JTCK
JTDI
JTDO
JNTRST
RESET#
OSCOUT
FLASH_DQ0 FLASH_DQ1
STM32_GPIO_10 STM32_GPIO_11 STM32_GPIO_12 STM32_GPIO_13
STM32_GPIO_14
STM32_GPIO_0
STM32_GPIO_1
STM32_GPIO_2 STM32_GPIO_3 STM32_GPIO_4
STM32_GPIO_5 STM32_GPIO_6 STM32_GPIO_7
STM32_GPIO_8 STM32_GPIO_9
VDDA
MCU_3V3
USB_DISCONNECT DM_STM32
DP_STM32
FLASH_3V3
FLASH_DQ2 FLASH_DQ3
FLASH_C
FLASH_nS FLASH_DQ2
FLASH_DQ3
FLASH_C FLASH_DQ0
FLASH_nS
FLASH_DQ2
FLASH_DQ3
FLASH_DQ1
USB_DISCONNECT
USB_DM
USB_DP
MCU_3V3
FLASH_3V3
MCU_3V3
MCU_3V3
FLASH_3V3
MCU_3V3
J38
2 1
R66 4K7
D30 REDC116
100nF
56
R128
C123
1uF 6.3V
U10
1
VBAT
STM32F103C8T6
2 3PC14-OSC32_IN
PC15-OSC32_OUT
PC13-Tamper-RTC
4
5
PD0 OSC_IN 6
PD1 OSC_OUT
7NRST
8VSSA
9VDDA
10 PA0-WKUP
PA1
11
PA2
12
PA3
13
PA4
14
PA5
15
PA6
16
PA7
17 PB0 18
PB1 19
20 PB2-BOOT1
PB10 21
PB11 22
VSS_1
23
VDD_1 24
PB12 25 PB13 26
PB14 27 PB15 28
PA8
29
PA9
30
PA10
31
PA11
32
PA12
33
34
PA13 JTMS
VSS_2
35
36
VDD_2
PA14 JTCK
PA15 JTDI 37
PB3 JTDO 38
PB4 JNTRST 39
40
PB5 41
PB6 42
PB7 43
44 BOOT0
PB8 45
PB9 46
VSS_3
47
VDD_3 48
C122
100nF
U9
VCC 8
N25Q032xSC
5DQ0
VSS
4
C
6
nS
1
3nW/Vpp/DQ2
7nHOLD/DQ3
DQ1 2
R131 4k7
C121
100nF
R64
0R - N/A
C118
100nF
R130
4k7
C119
100nF
R129
4k7
C120
100nF
R67
4K7
GSPG30072014DI1255

DocID026791 Rev 2 17/19
STEVAL-IME008V1 Schematic diagrams
19
Figure 16. STEVAL-IME008V1 circuit schematic (16 of 16)
Not Assembly
RS (505-9186)
C&K (Y78B22110FP)
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
RED
Kingbright KP2012SURC
RS: 466-3829
Farnell: 8529930
LED 0805
OSCILLATOR
Murata (CSTCE8M00G55-R0)
DigiKey (490-1195-1-ND)
RS: 283-961
Farnell: 1615352
MCU RESET
8MHZ OSC
DOWNLOAD
FLASH READY
RESET#
USER_LED1
USER_LED2
OSCOUTOSCIN
MCU_3V3
RST2
SW PUSHBUTTON-DPST
D24
Y1
8MHz
R81 56R
D25
R68 56R
R65
10K
C117
100nF
GSPG30072014DI1300

Revision history STEVAL-IME008V1
18/19 DocID026791 Rev 2
2 Revision history
Table 1. Document revision history
Date Revision Changes
06-Aug-2014 1 Initial release.
06-Aug-2015 2 Updated title on the cover page.

DocID026791 Rev 2 19/19
STEVAL-IME008V1
19
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