STMicroelectronics EVALSTGAP4S User manual

Introduction
The STGAP4S is a galvanically isolated single gate driver for IGBTs and SiC MOSFETs with advanced protection, configuration,
and diagnostic features. The architecture of the STGAP4S isolates the channel gate driving from the control and from the low
voltage interface circuitry through true galvanic isolation. The unique output architecture is designed to allow the use of an
external MOSFET push-pull stage giving flexibility in terms of current capability dimensioning and easing the use of several
power switches in parallel. The 2 pre-driver outputs are characterized by current capability and output voltage swing optimized
for that topology and allow the use of a negative gate driving supply.
The EVALSTGAP4S board allows to evaluate all the STGAP4S features. The board is equipped with two STGAP4S drivers
connected in an SPI daisy chain and with each high voltage side fed by its own flyback power supply, whose controller is
integrated in the driver itself. Each STGAP4S drives the gate of an SiC MOSFET in H2PAK-7 package having 650 V voltage
rating and connected in half-bridge.
Multiple EVALSTGAP4S boards can be connected together allowing the implementation of an SPI daisy chain with more than
two devices and also the evaluation of more complex topologies, as a full bridge inverter.
The use in combination with the STEVAL-PCC009V2 communication board allows the easy configuration of all the driver's
protection and control features, through the SPI interface, as well as access to the driver's status registers, offering an
advanced diagnostic. The board can be used also in standalone mode without a communication board using the default device
configuration at power-on.
Evaluation board for STGAP4S advanced galvanically isolated gate driver
UM3153
User manual
UM3153 - Rev 1 - May 2023
For further information contact your local STMicroelectronics sales office.
www.st.com

Figure 1. EVALSTGAP4S evaluation board
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1Safety and operating instructions
1.1 General terms
During assembly, testing, and operation, the evaluation board poses several inherent hazards, including
bare wires, moving or rotating parts and hot surfaces.
Danger: There is danger of serious personal injury, property damage or death due to electrical shock
and burn hazards if the kit or components are improperly used or installed incorrectly.
The kit is not electrically isolated from the high-voltage supply DC input. No insulation is ensured
between the accessible parts and the high voltage. All measuring equipment must use adequately
insulated probes, clamps, and connecting wires. Never touch the evaluation board while it is energized as
it can cause an electrical shock hazard.
When a tool is used to interface the board to a PC and the board is supplied (HV BUS) at a voltage outside
the ELV range, a proper insulation method such as a USB isolator must be used to operate the board.
All operations involving transportation, installation and use, and maintenance must be performed by skilled
technical personnel able to understand and implement national accident prevention regulations. For the purposes
of these basic safety instructions, “skilled technical personnel” are suitably qualified people who are familiar with
the installation, use, and maintenance of power electronic systems.
1.2 Intended use of evaluation board
The board is designed for evaluation purposes only and must not be used for electrical installations or machinery.
Technical data and information concerning the power supply conditions are detailed in the documentation and
should be strictly observed.
1.3 Installing the evaluation board
• The installation and cooling of the evaluation board must be in accordance with the specifications and
target application.
• The board must be protected against excessive strain. In particular, components should not be bent or
isolating distances altered during transportation or handling.
• No contact must be made with other electronic components and contacts.
• The board contains electrostatically-sensitive components that are prone to damage if used incorrectly. Do
not mechanically damage or destroy the electrical components (potential health risks).
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1.4 Operating the evaluation board
To properly operate the board, follow these safety rules.
1. Work area safety:
– The work area must be clean and tidy.
– Do not work alone when boards are energized.
– Protect against inadvertent access to the area where the board is energized using suitable barriers
and signs.
– A system architecture that supplies power to the evaluation board must be equipped with additional
control and protective devices in accordance with the applicable safety requirements (that is,
compliance with technical equipment and accident prevention rules).
– Use non-conductive and stable work surface.
– Use adequately insulated clamps and wires to attach measurement probes and instruments.
2. Electrical safety:
– Remove power supply from the board and electrical loads before performing any electrical
measurement.
– Proceed with the arrangement of measurement setup, wiring, or configuration paying attention to high
voltage sections.
– Once the setup is complete, energize the board.
– The kit is not electrically isolated from the AC/DC input. If a tool is used to interface the board with
a PC and the board is supplied (HV BUS) at a voltage outside the ELV range, a proper insulation
method such as a USB isolator must be used to operate the board.
Danger: Do not touch the board when it is energized or immediately after it has been
disconnected from the voltage supply as several parts and power terminals containing
potentially energized capacitors need time to discharge. Do not touch the boards after
disconnection from the voltage supply as several parts, included PCB, may still be very
hot. The kit is not electrically isolated from the DC input.
3. Personal safety
– Always wear suitable personal protective equipment such as insulating gloves and safety glasses.
– Take adequate precautions and install the board in such a way to prevent accidental touch. Use
protective shields such as an insulating box with interlocks if necessary.
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2Getting started
2.1 EVALSTGAP4S with STEVAL-PCC009V2 and evaluation software
The EVALSTGAP4S board, in combination with the STEVAL-PCC009V2 interface board and the STSW-STGAP4
software toolset, allows to easily evaluate the STGAP4S functionalities. Indeed, the evaluation software allows
to quickly configure the device parameters and to monitor the status flags as well as the diagnostic outputs.
Moreover, the software also allows to save a configuration set and recall it when needed, for instance after the
board power-on.
The PWM input signals must be provided to the dedicated connector using an external function generator.
2.1.1 Check list
•PC with Microsoft® Windows® 10 with a free USB port
• EVALSTGAP4S board
• STEVAL-PCC009V2 interface board (with installed the dedicated firmware STSW-STGAP4_FW.hex)
• STSW-STGAP4 GUI evaluation software
• 10-pin flat cable
• USB to Mini-USB cable
• Power supply for VCC supply voltage
• PWM function generator
For information about the installation of the STSW-STGAP4_FW.hex firmware in the STEVAL-PCC009V2
interface board and of the STSW-STGAP4 GUI evaluation software, see the STSW-STGAP4 toolset User
Manual.
2.1.2 Single board setup example
• Connect the EVALSTGAP4S J9 connector to the STEVAL-PCC009V2 10-pin connector using the flat
cable.
• Connect the EVALSTGAP4S VCC power supply, present on J1 connector, to a power supply keeping it off.
• Connect the STEVAL-PCC009V2 to the PC using the USB cable.
• Turn on the VCC power supply (8 V<VCC<24 V) of the EVALSTGAP4S. The DIAG1 and DIAG2 LEDs turn
on.
• Connect the input signals IN+_H, IN+_L of EVALSTGAP4S J3 connector to the PWM function generator
signals.
• Start the STSW-STGAP4 GUI evaluation software.
The board is ready to be used. See the STSW-STGAP4 toolset User Manual for details about the available
operations. The minimum operations to enable the PWM outputs are:
• Execute the ResetStatus, the fault flags are cleared and the DIAG1 and DIAG2 LEDs switch off.
• Set the SD high, the input to output PWM is now enabled.
2.1.3 Multiple board setup example
• Refer to Section 5 for the hardware setup of the EVALSTGAP4S boards.
• Connect the MASTER EVALSTGAP4S J9 connector to the STEVAL-PCC009V2 10-pin connector using the
flat cable.
• Connect the MASTER EVALSTGAP4S VCC power supply, present on J1 connector, to a power supply
keeping it off.
• Connect the STEVAL-PCC009V2 to the PC using the USB cable.
• Turn on the VCC power supply (8 V<VCC<24 V) of the MASTER EVALSTGAP4S. The DIAG1 and DIAG2
LEDs turn-on.
• Connect the input signals IN+_H, IN+_L of each EVALSTGAP4S J3 connector to the PWM function
generator signals.
• Start the STSW-STGAP4 GUI evaluation software.
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The board is ready to be used. See the STSW-STGAP4 toolset User Manual for details about the available
operations. The minimum operations to enable the PWM outputs are:
• Execute the ResetStatus, the fault flags are cleared and the DIAG1 and DIAG2 LEDs switch off.
• Set the SD high, the input to output PWM is now enabled.
2.2 EVALSTGAP4S in standalone mode
The board can also work without SPI programming using the STGAP4S default values at power-on.
2.2.1 Check list
• EVALSTGAP4S board
• Power supply for VCC supply voltage
• PWM function generator
2.2.2 Single board setup example
• Connect the EVALSTGAP4S VCC power supply, present on J1 connector, to a power supply and turn it on
(8 V<VCC<24 V). The DIAG1 and DIAG2 LEDs turn on.
• Connect the input signals IN+_H, IN+_L of EVALSTGAP4S J3 connector to the PWM function generator
signals.
• Set the SD pin low for at least 100 μs (J1 connector).
• Set the SD pin high value: the fault flags are cleared at the rise and the DIAG1 and DIAG2 LEDs switch off.
• The input to output PWM is now enabled.
2.2.3 Multiple board setup example
• Refer to Section 5 for the hardware setup of the EVALSTGAP4S boards.
• Connect the MASTER EVALSTGAP4S VCC power supply, present on J1 connector, to a power supply and
turn it on (8V<VCC<24V). The DIAG1 and DIAG2 LEDs turn on.
• Connect the input signals to IN+_H, IN+_L of EVALSTGAP4S J3 connector to the PWM function generator
signals.
• Connect the PWM input signals IN+_H, IN+_L of each EVALSTGAP4S J3 connector to the PWM function
generator signals.
• Set the SD pin low for at least 100 μs (J1 connector).
• Set the SD pin high value: the fault flags are cleared at the rise and the DIAG1 and DIAG2 LEDs switch off.
• The input to output PWM is now enabled.
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3Hardware description and configuration
The EVALSTGAP4S is provided with a ready-to-use hardware configuration.
The power stage is composed by two SiC MOSFETs in half-bridge configuration with a small capacitor bulk
connected to the HV BUS:
• SiC MOSFETs: SCTH100N65G2-7AG 650 V 20 mΩ - H7PAK
• Bulk capacitor: (2.2 uF//470 nF//470 nF) - 630 V (see Figure 16 for details)
• High-voltage rail up to 520 V: limited by MOSFETs and capacitor ratings
• Maximum working voltage across isolation: 1200 V
The EVALSTGAP4S is provided with a linear regulator supplied by the VCC voltage that generates the 3.3 V
supply for the low-voltage side of both the STGAP4S present on the board. The VCC voltage is also used to
supply the two isolated flyback power supplies (one for each driver) that are driven by the controller integrated in
each STGAP4S and generates the positive and negative voltages for the driving side. Thus, only the VCC voltage
is needed to fully supply the board (except for the HV BUS voltage):
• Only VCC voltage needed to supply the board
• On-board 3.3 V linear regulator for the LV side supply (common to both drivers)
• Isolated flyback for HV +18/-5 V driving supply (one for each driver)
The STGAP4S features an SPI interface that is used to set the device parameters, enable or disable the device
functions, and access the advanced diagnostic. The EVALSTGAP4S is suitable to be used in combination with
STEVAL-PCC009V2 (with the dedicated firmware STSW-STGAP4_FW.hex installed) and STSW-STGAP4 GUI
software. However, it is also possible to operate the STGAP4S without using the SPI interface. In this case, the
driver works with the default configuration values and protections.
Table 1. Connector description
Name Type Function
J1 Power supply VCC supply voltage to the flyback and to the 3.3V on-board linear regulator. Optional 3V3IN
supply for the logic control side.
J2 Board extension Connection to an optional slave EVALSTGAP4S board
J3 Control signal PWM logic inputs
J4 Board extension Connection to an optional master EVALSTGAP4S board
J5 Power supply Optional external VH and VL supplies for the HV side of the LOW-side driver
J6 Power supply Optional external VH and VL supplies for the HV side of the HIGH-side driver
J9 Control signal SPI and diagnostic interfacing.
Suitable for STEVAL-PCC009V2 interface board.
J10 Control signal Connector for SPI and diagnostic probing
HV Power connection Plated hole for connection to the positive pole of the high-voltage bus. Drain of the high-side
power MOSFET.
OUT Power connection Plated hole for connection to a load. Source of the high-side power MOSFET and drain of the
low-side power MOSFET.
GNDPWR Power connection Plated hole for connection to the negative pole of the high-voltage bus. Source of the low-side
power MOSFET.
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Figure 2. Connectors location
J2
J4
J9
J3 J10
J1
J6
J5
HV
OUT
GNDPWR
Table 2. Jumper resistor description
Name Side Driver Function
JR1 LV Both 3V3IN from on-board regulator
JR3, JR5 LV Both Slave board power supply
JR4, JR6 LV Both Master board power supply
JR7, JR8, JR9, JR10 LV Both Cumulative diagnostic (DIAG1, DIAG2)
JR11, JR12 LV Both Options for the SPI chain
JR13, JR14 LV Both PWM logic input configuration
JR17 HV Low-side VL to GNDSISO bypass
JR18, JR19 HV Low-side VH, VL on-board regulation disconnection
JR20 HV Low-side ASC to GNDSISO bypass
JR21 HV Low-side SENSE to GNDSISO bypass
JR22, JR23 HV Low-side DEFAULT pin setting
JR26 HV High-side VL to GNDSISO bypass
JR27, JR28 HV High-side VH, VL on-board regulation disconnection
JR29 HV High-side ASC to GNDSISO bypass
JR30 HV High-side SENSE to GNDSISO bypass
JR31, JR32 HV High-side DEFAULT pin setting
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Figure 3. Jumper location – TOP layer
JR1 JR11 JR3 JR5
JR10
JR9
JR7
JR8
JR14
JR13
JR28
JR27JR26
JR29 JR31
JR32
JR20
JR17
JR23
JR22
JR18
JR19
JR12 JR6
JR4
Figure 4. Jumper location – BOT layer
JR21
JR30
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Table 3. Jumper configuration of 3V3IN power supply source
Operating voltage Supply voltage source Jumper configurations Default configuration
3V3IN = 3.3V±5%
On-board regulator (from U3)
(VCC must be present, see
Table 4)
JR1 = CLOSE
JR3 = OPEN
JR4 = OPEN
X
External power supply (from J1)
JR1 = OPEN
JR3 = OPEN
JR4 = OPEN
External power supply (from
J1) and fed to board extension
connectors (to J2 and J4)
or
Supplied from board extension
connectors (from J2 or J4)
JR1 = OPEN
JR3 = CLOSE
JR4 = CLOSE
Table 4. Jumper configuration of VCC power supply source
Operating voltage Supply voltage source Jumper configuration Default configuration
8V < VCC < 24V
External power supply (from J1) JR5 = OPEN
JR6 = OPEN X
External power supply (from J1)
and feed to board extension
connectors (to J2 and J4)
or
Supply from board extension
connectors (from J2 or J4)
JR5 = CLOSE
JR6 = CLOSE
Table 5. Jumper configuration of LOW-side VH, VL power supply source
Operating voltage Supply voltage source Jumper configuration Default
configuration
VH_L = +18V
VL_L = -5V
On-board flyback with post regulator
(VCC must be present, see Table 4)
JR17 = OPEN
JR18 = CLOSE
JR19 = CLOSE
X
VH_L = +18V
VL_L = 0V
On-board flyback with post regulator
(VCC must be present, see Table 4)
JR17 = CLOSE
JR18 = CLOSE
JR19 = CLOSE
See STGAP4S Datasheet for
recommended values on www.st.com External power supply (from J5)
JR17 = DON’T CARE
JR18 = OPEN
JR19 = OPEN
Table 6. Jumper configuration of HIGH-side VH, VL power supply source
Operating voltage Supply voltage source Jumper configuration Default
configuration
VH_H = +18V
VL_H = -5V
On-board flyback with post regulator
(VCC must be present, see Table 4)
JR26 = OPEN
JR27 = CLOSE
JR28 = CLOSE
X
VH_H = +18V On-board flyback with post regulator JR26 = CLOSE
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