Sundance Technology SMT351T User manual

Sundance Multiprocessor Technology Limited Form : QCF42
SMT351T Date : 6 July 2006
Unit / Module Description: FPGA module
Unit / Module Number: SMT351T
Document Issue Number:
Issue Date:
Original Author: E.P
SMT351T User Guide
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
SMT351T User Guide Last Edited: 22/02/2008 18:00:00

Revision History
Issue Changes Made Date Initials
1.0.0 First release 28/01/08 E.P
Typo corrections, fixed broken Hyperlinks, added
chapter 4.2.7 FPGA Bitstream formatting.
Added references to MIG tools.
30/01/08 E.P
1.0.1
1.0.2 Updated Figure 3, updated RSL, SLB descriptions 30/01/08 E.P
1.0.3 updated number of RSL links available per FPGA,
Top and Bottom View, SLB warning considering its
voltage level
22/02/08 E.P
SMT351T User Guide Page 2 of 38 Last Edited: 22/02/2008 18:00:00

Table of Contents
1Introduction ................................................................................................................ 6
2Related Documents..................................................................................................... 7
2.1 Referenced Documents .............................................................................................7
2.2 Applicable Documents ..............................................................................................7
3Acronyms, Abbreviations and Definitions ................................................................. 7
3.1 Acronyms and Abbreviations ...................................................................................7
3.2 Definitions .................................................................................................................7
4Functional Description ............................................................................................... 9
4.1 Block Diagram...........................................................................................................9
4.2 Module Description.................................................................................................10
4.2.1 FPGA...................................................................................................................10
4.2.2 CPLD...................................................................................................................10
4.2.3 FLASH MEMORY..............................................................................................10
4.2.4 JTAG Header......................................................................................................11
4.2.5 FPGA Configuration schemes............................................................................11
4.2.6 FPGA Reset Scheme...........................................................................................12
4.2.7 FPGA Bitstream formatting ..............................................................................14
4.2.8 DDR2SDRAM .....................................................................................................14
4.2.9 Sundance Rocket io Serial Link ........................................................................16
4.2.10 Sundance Low voltage Bus ................................................................................16
4.2.11 TIM Connectors..................................................................................................17
4.2.12 DIP Switches ......................................................................................................17
4.2.13 Available clocks ..................................................................................................18
4.2.14 LEDs ...................................................................................................................20
4.2.15 Performance........................................................................................................20
4.3 Interface Description ..............................................................................................20
4.3.1 Power Budget .....................................................................................................20
5Footprint ....................................................................................................................22
5.1 Top View..................................................................................................................22
5.2 Bottom View............................................................................................................23
6Pinout.........................................................................................................................24
6.1 FPGA Pin allocation by bank .................................................................................24
6.2 SHB..........................................................................................................................33
6.3 SLB ..........................................................................................................................33
7Qualification Requirements ......................................................................................35
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7.1 Qualification Tests..................................................................................................35
7.1.1 Meet Sundance standard specifications............................................................35
7.1.2 Speed qualification tests ....................................................................................35
7.1.3 Integration qualification tests ...........................................................................35
8Support Packages ......................................................................................................35
9Physical Properties....................................................................................................36
10 Safety .........................................................................................................................37
11 EMC ...........................................................................................................................38
12 Ordering Information ................................................................................................38
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Table of Figures
Figure 1: Block Diagram ........................................................................................................9
Figure 2: CPLD state machine.............................................................................................13
Figure 3: FPGA connections to DDR2SDRAM....................................................................15
Figure 4: FPGA clock buffers usage.....................................................................................19
Figure 5: Top View................................................................................................................22
Figure 7: Bottom view ..........................................................................................................23
Table of Tables
Table 1: DIP switch SW1 position for special reset feature ...............................................17
Table 2: DIP switch SW1 position for the selection of the configuration bitstream source
.......................................................................................................................................18
Table 3: DIP switch SW1 position for the selection of the Flash erase & program
operations. .....................................................................................................................18
Table 4: Coolrunner II resources summary.........................................................................21
Table 5:Coolrunner II pin resources. ...................................................................................21
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1Introduction
The SMT351T is an FPGA TIM module designed to be integrated in modular
systems.
It is designed to connect to the huge range of other TIM modules and carriers
developed by Sundance.
Sundance modular solutions provide flexible and upgradeable systems.
The SMT351T is a TIM module aimed at completing the range of Sundance
Virtex4 and Virtex5 modules like SMT362, SMT339.
It provides a communications platform between an XC5VSXT/LXT device and
•2 banks of DDR2 SDRAM at a frequency of up to 250Mhz.
•4 RSL, connectors (up to 4 times .4 MGTs)
•LVDS connections for high speed parallel connections
•LVTTL connections and connectors.
This variety of connectors and interfaces provides a wide range of development
options for designers to explore the capabilities of the comprehensive Sundance
TIM modules family.
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & User’s guide) for single width modules.
It sits on a carrier board.
The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links
(Comport links or for some RSL links as well) between all the modules fitted and a
pathway to the host.
The SMT351T requires a 3.3V power supply (as present on all Sundance TIM
carrier boards), which must be provided by the two diagonally opposite mounting
holes.
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2Related Documents
2.1 Referenced Documents
Sundance SDB specification
SUNDANCE SHB specification
Sundance SLB specification
Micron DDR2SDRAM 1Gbit (MT47H64M16BT-37E) or
Micron DDR2SDRAM 2Gbit (MT47H128M16BT-37E) device
Spansion S29GLXXXN flash
2.2 Applicable Documents
TI TIM specification & User’s guide
Samtec QSH Catalogue page
Virtex 5 User Guide
3Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
TIM Texas Instruments Module
TI© DSP Texas Instrument Digital Signal Processor
Xilinx© FPGA Xilinx© Field Programmable Gate Array.
DDR2SDRAM Dual Data Rate 2 SDRAM
CP ComPort. Communication interface
RSL Rocket Serial Link
SHB Sundance High-Speed Bus. Communication interface
3.2 Definitions
DSP Module Typically a TIM module hosting a TI DSP and, a Xilinx FPGA.
FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all
functionality.
Firmware A proprietary FPGA design providing some sort of functionality.
Sundance Firmware is the firmware running in an FPGA of a DSP
module.
SMT351T User Guide Last Edited: 22/02/2008 18:00:00

SMT351T User Guide Page 8 of 38 Last Edited: 22/02/2008 18:00:00

4Functional Description
The SMT351T provides a Virtex 5 FPGA, memory and IO connectors to allow the
development of applications ranging from Software defined Radio to MIMO, video,
Signal processing.
Typically, an ADC/DAC mezzanine can be fitted on the SLB connector and memory is
used to store burst data between the outside world/host/other TIMs, while the FPGA
implements functions on that data.
4.1 Block Diagram
FPGA
Virtex-5 FF1136
XC5V
SX50T/LX50T/
SX95T/LX110T
1.0V Core
1.8V/2.5V/3.3V I/O
Xilinx Coolrunner II CPLD
XC2C256CP132 on
Comport3 and
Config&control
JTAG Header
J1 Top Primary TIM
Connector
ComPort/SDL 0 & 3
J2 Bottom Secondary TIM
Connector
ComPort/SDL 1 & 4
4 LEDs
JTAG
204 I/O pins
2 banks of
DDR2SDRAM
2x (64Mx16 or 128Mx16)
11 I/O pins
20 differential pairs
40 TTL IOs Sundance Lo
w
(1 C
o
RSL clock
Flash memory
Local clock
ONL
Y
LX
16 RocketIO links Sundance Ro
c
Serial Link (4
C
Switch
Figure 1: Block Diagram
SMT351T User Guide Last Edited: 22/02/2008 18:00:00

4.2 Module Description
Figure 1 presents colour coded blocks regrouping components according to their functionality or
their nature.
The following paragraphs will detail each one of them, but first, here is a global description of each
block.
•Block1 and Block6 Xilinx Virtex 5 XC5VSXT/LXT and configuration scheme for the FPGA.
•Block2: DDR2SDRAM memory banks.
•Block3: IO connectors for general purpose or dedicated interfaces.
•Block4: 50MHz or 125MHz clocks.
•Block5: LEDs for development and in-use monitoring and general purpose use.
4.2.1 FPGA
Xilinx Virtex 5 XC5VSX50T, XC5VLX50T, XC4VSX95T or XC5VLX110T FPGA.
This device is packaged in a FF1136-pin BGA package.
4.2.2 CPLD
Xilinx Coolrunner II device XC2C256-7CP132C.
This device is packaged in a 132-ball BGA type package with a -7 speed grade.
It can be used to configure the FGPA via Comport 3, or from a configuration stored in flash
memory.
The flash memory is programmed using the CPLD and via the ComPort3.
4.2.3 FLASH MEMORY
S29GL256N11TFI01 is a 256Mbit flash from Spansion.
It can be used to configure the FPGA at power up.
Flash accessed using Comport3 via the CPLD.
Flash programming selection via switch SW1 (See Table 3)
Software Library Support available from Sundance.
The code can run on Sundance DSP TIM or a Host.
All the flash functionalities are available.
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4.2.4 JTAG Header
The JTAG header is compatible with Xilinx Parallel-IV cable signals.
The header is a custom header that plugs onto a custom cable that must be ordered at time from
Sundance.
This cable then plugs into the Xilinx parallel cable pod.
It supports code download (for the FPGA), FPGA configuration, Hardware and Software
Debugging tools for the Virtex-5.
This cable connects the parallel port/USB port of an engineer's Workstation/PC to the JTAG
chain of the SMT351T Module.
All the Xilinx devices from block1 are chained and accessible via this JTAG header.
4.2.5 FPGA Configuration schemes
Different schemes are available to provide maximum flexibility in systems where the
SMT351T is involved:
The FPGA configuration bitstream source is
•On Comport 3:
The CPLD is connected to the Comport 3 link of the SMT351T TIM connector. (See block1).
A switch is used to select Comport 3 as the link that will be used to receive the bitstream.
The CPLD allows for FPGA configuration in slave SelectMAP mode.
•Using the on-board Flash memory.
The CPLD monitors the configuration data between the Flash and the FPGA.
The FPGA configuration is operated in Slave SelectMap mode.
A switch is used to select the Flash as the source for the configuration bitstream.
•Using the on-board JTAG header and Xilinx JTAG programming tools.
The JTAG header is a Parallel-IV Header.
Note: Using JTAG to configure the FPGA bypasses the CPLD which controls configuration.
The following section describes the CPLD role and the reset scheme used.
As the CPLD is bypassed when JTAG is used to configure the FPGA, it is necessary to adopt
one of the three following ways:
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•If your FPGA design does not implement comport3,
odo not use the Reset signal generated by the CPLD but use the TIM reset signal
as your design’s reset. You can use JTAG to configure your FPGA with your
application and the design will reset and run everytime you issue a new TIM
reset.
•If your design implements comport3
oSet the switch to configure the FPGA from flash after reset. In this way a default
bitstream being stored in flash will be loaded in the FPGA by the CPLD.
In this manner the CPLD has gone trhough the cycle of configuring the
FPGA and releases the reset (FPGAresetn)
Then you can reconfigure the FPGA via JTAG with your application.
oSet the switch to configure from comport 3. After reset, configure the FPGA via
JTAG and provide an end key word on comport 3 to the CPLD so that it releases
the Reset. (FPGAresetn).
4.2.6 FPGA Reset Scheme
The CPLD is connected to a TIM global Reset signal provided to the SMT351T via its primary
TIM connector pin 30. (See TI TIM specification & User’s guide).
This signal goes to the CPLD and the FPGA.
Nevertheless as a general rule for good practice, the FPGA should not use this reset but should
use the reset signal generated by the CPLD.
The CPLD provides another signal called FPGAResetn that offers a better Reset control over
the FPGA.
At power up or on reception of a low TIM global Reset pulse, the CPLD drives the
FPGAResetn signal low and keeps it low.
This is used to keep the FPGA design in reset.
A new FPGA configuration bitstream can then be downloaded.
When the ENDKEY has been received, the CPLD drives FPGAResetn high.
Use FPGAResetn for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also avoid
possible conflicts on ComPort 3 if your FPGA design implements it.
(Comport3 is a communication resource shared by the CPLD and the FPGA. But only 1 entity
is allowed to use it at a time).
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If you implement comport 3 in the FPGA you have to use
Fpgaresetn generated by the CPLD, as the comport is shared
between the two.
The Reset control is operated by the CPLD line FPGAResetn.
The following diagram shows the CPLD states after Reset.
Figure 2: CPLD state machine
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4.2.7 FPGA Bitstream formatting
If you generated you FPGA bitstream using Diamond FPGA, you do not need any other handling.
The .app file created can be used as is to configure the FPGA.
If you used Xilinx ISE and created a .bit file, you need to use the Sundance executable
“Getrawdata.exe” provided for free in the SMT6001 package.
Please read the SMT6001 help file at chapter: “Saving FPGA configuration data to file”.
The resulting file can be used as is to configure the FPGA.
4.2.8 DDR2SDRAM
There are 8 devices of DDR2 SDRAM connected to the FPGA providing up to 2GBytes of
storage.
The devices are grouped in two independent banks. The two banks are identical so we will
discuss only one.
A bank is made of four devices. Within a bank the devices share the same address and control
bus.
The data bus of each device is routed to the FPGA. This allows accessing all the chips in
parallel, at the same time.
The DDR2 memory runs at 200MHz with of the shelf controllers form MIG tools, but higher
performances can be reached if the designs are optimised.
Depending on the FPGA and design implemented, performances might vary.
Each bank is fully independent with separate address, control and data busses and arranged as
follows:
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Figure 3: FPGA connections to DDR2SDRAM
Xilinx MIG utility:
The Memory controllers generated by MIG1.72 and MIG2.0 have been successfully running at
200MHz.
4x
components
4x
components
The pinout was not generated using MIG2.0 but the controllers generated by MIG2.0 can be
used with the SMT351T pinout. Also see Xilinx AR#29313
The devices used are Micron DDR2SDRAM 1Gbit (MT47H64M16BT-37E) or
DDR2SDRAM 2Gbit (MT47H128M16BT-37E) devices.
Alternative part numbers, fully compatible can be fitted depending on availability at time of
order.
SMT351T User Guide Page 15 of 38 Last Edited: 22/02/2008 18:00:00

4.2.9 Sundance Rocket io Serial Link
Sundance boards can be interconnected using RSL connectors located on the front and back of
the board. The SMT351T has four connectors in total (two at the front and two at the back).
The boards connected via RSL use the RSL protocol to communicate. Refer to the Sundance
Help File for more details.
The underlying design of the RSL uses the MGT of the FPGA to transfer the data. Each FPGA
has a different amount or MGTs. Some FPGAs do not have any MGTs; boards using these
cannot use the RSL protocol.
The speed of the RSL depends on the frequency at which the MGTs are clocked. Sundance
uses 125Mhz, allowing data rate of 2.5Gbits/s per MGT.
Depending on the FPGA fitted on the SMT351T up to 16 RSL links may be available.
The LX50T and SX50T FPGAs provide 12 links
The LX110T and SX95T FPGAs provide 16 links.
4.2.10 Sundance Low voltage Bus
The SLB bus is used to extend the functionality of the SMT351T by connecting to it a daughter
board.
There are different types of daughter boards. Some provide ADCs, some DACs or a
combination of both.
Sundance provides examples and reference design combining the SMT351T to daughter
boards. These examples are usually designed with 3L Diamond tools.
Electrical details
Typically, this is an LVDS bus comprising data (2 x 16 bit buses, I & Q), clock, and control
signals.
Nevertheless, the SLB lines can also be used for single ended signalling.
They allow interfacing to Sundance mezzanine modules providing that you implement an SLB
interface in the FPGA. (See 2.1)
They allow interfacing to the outside world by implementing your own LVDS interface in the
FPGA.
In LVDS mode, all LVDS data pins (both I and Q) are connected to a 2.5V powered FPGA
bank (link selectable by jumper JP2).
The FPGA LVDS DIFF_TERM standard should be used instead of the DCI terminations when
LVDS standard is selected.
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DCI terminations are only available when a 2.5v standard is selected.
The LVDS Clock signals are also in these banks.
In LVTTL mode, all LVTTL signals are connected to a 3.3V powered FPGA bank.
(Link selectable by jumper JP2).
In case the SLB bus is to be used with a mezzanine, the SLB voltage
level must be set according to the mezzanine fitted on the module.
4.2.11 TIM Connectors
TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA.
The comports which are available on the SMT351T are CP0, CP1, CP3, and CP4.
They allow interfacing to Sundance TIM modules or to a Host PC providing that you
implement a Comport Interface inside the FPGA. (See 2.1)
The Comport interface is available in Sundance SMT6500 support package.
The FPGA io banks hosting the Comport signals are powered using Vcco = 3.3v.
The TIM connectors also provide power/ground, reset and various control signals.
References and specifications for these connectors are available in TI TIM specification &
user’s guide
4.2.12 DIP Switches
One four-position DIP switch is connected to the CPLD to provide control over the selection of
the configuration bitstream source and a special reset feature called “TIM Confign”.
SW1 pos 4 TIM Config
ON ENABLED
OFF DISABLED
Table 1: DIP switch SW1 position for special reset feature
SW1 pos 3,2, 1 JPC3 JPC2 JPC1
C3P OFF OFF OFF
Flash OFF OFF ON
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Table 2: DIP switch SW1 position for the selection of the configuration bitstream source
SW1 pos 3,2, 1 JPC3 JPC2 JPC1
Flash accesses ON OFF OFF
Table 3: DIP switch SW1 position for the selection of the Flash erase & program operations.
The Flash erase & program operations are operated by the CPLD.
Commands are provided via Comport3 from an application running on a Host or DSP.
Status information from the Flash is given over Comport3 as well.
4.2.13 Available clocks
Two onboard clocks:
•50mhz LVTTL oscillator. Used by the CPLD and connected to the FPGA.
•125mhz LVDS oscillator. Connected to the FPGA. Used to clock the MGTs.
An external clock can be input into the Virtex 5 FPGA via the SLB connector.
Sundance applies this scheme for ADC/DAC mezzanines.
SMT351T User Guide Page 18 of 38 Last Edited: 22/02/2008 18:00:00

k31
TIM Conn
PXICLK 50Mhz single ended
osc
BANK 5
BANK 20
BANK
3
BANK
1
BANK 12
BANK
2
BANK
4
BANK 18BANK 22
BANK 6
BANK
1
BANK 17 BANK 15 BANK 19
DDR2A
BANK 11
BANK
1
BANK 21 BANK 17 BANK 13 BANK 15
DDR2B
dqs2
dqs1
dqs0
h34k33
dqs3dqs6
g27h28e28
dqs5dqs4dqs7
Regional clock input, (for single ended
clocks, or for differential clocks, P side)
dqs4dqs7dqs5dqs3dqs6
af34ah34ad32
LEFT COLUMN MIDDLE
COLUMN RIGHT COLUMN
ag21
ag18
vclk_p
osc50
Global clock input, (for single ended
clocks, or for differential clocks, P side)
dqs0
dqs2
dqs1
dqs0
pxiclk
w6
Clkoutq_p j6
Clkouti_p
125MHz differential
oscillator
ak26ak29ak28
aa29
y28
m31
p31
BANK 23BANK 19BANK 15BANK 11
BANK 13BANK 17BANK 21
BANK 25
k31
Figure 4: FPGA clock buffers usage.
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4.2.14 LEDs
4 Red LEDs connect to the FPGA and are available to the User: D4, D5, D6, D7.
1 Green Led: D1, connects to the DONE pin of the FPGA and is lit to show that the FPGA is
configured. (depending on supply from manufacturer a red led can be fitted instead).
4.2.15 Performance
The FPGA features like speed grade and density dictate most performances.
The performances achievable by the other components are given in the chapters above and
the components respective data sheets.
4.3 Interface Description
For the TIM to carrier board or external world interfacing, see in Sundance Help file (that you
can download from the Sundance Wizzard)
4.3.1 Power Budget
The SMT351T draws its power from the 3.3v rail of the PCI.
The PCI specification stipulates that the maximum power for one card is 25W.
Therefore, the maximum current that the SMT351T could draw from +3.3V is 7.6A, assuming
zero current on all the other supply voltages.
But this limit is "system dependent," so a given system might not have the full 7.6A available
for a slot even if it is the only PCI card in the system.
A system might balance the power capabilities differently between the +5V and +3.3V (and +/-
12V) supplies, rather than making 25W available from +5V and 25W available from +3.3V.
As a result, check your main power supply ratings.
If your system is likely to reach 25W per power rail we advice that you provide extra power to
the carrier board using an external power supply.
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