Sundance Technology SMT351T User manual

Sundance Multiprocessor Technology Limited Form : QCF42
SMT351T Date : 6 July 2006
Unit / Module Description: FPGA module
Unit / Module Number: SMT351T
Document Issue Number:
Issue Date:
Original Author: E.P
SMT351T User Guide
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
SMT351T User Guide Last Edited: 22/02/2008 18:00:00

Revision History
Issue Changes Made Date Initials
1.0.0 First release 28/01/08 E.P
Typo corrections, fixed broken Hyperlinks, added
chapter 4.2.7 FPGA Bitstream formatting.
Added references to MIG tools.
30/01/08 E.P
1.0.1
1.0.2 Updated Figure 3, updated RSL, SLB descriptions 30/01/08 E.P
1.0.3 updated number of RSL links available per FPGA,
Top and Bottom View, SLB warning considering its
voltage level
22/02/08 E.P
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Table of Contents
1Introduction ................................................................................................................ 6
2Related Documents..................................................................................................... 7
2.1 Referenced Documents .............................................................................................7
2.2 Applicable Documents ..............................................................................................7
3Acronyms, Abbreviations and Definitions ................................................................. 7
3.1 Acronyms and Abbreviations ...................................................................................7
3.2 Definitions .................................................................................................................7
4Functional Description ............................................................................................... 9
4.1 Block Diagram...........................................................................................................9
4.2 Module Description.................................................................................................10
4.2.1 FPGA...................................................................................................................10
4.2.2 CPLD...................................................................................................................10
4.2.3 FLASH MEMORY..............................................................................................10
4.2.4 JTAG Header......................................................................................................11
4.2.5 FPGA Configuration schemes............................................................................11
4.2.6 FPGA Reset Scheme...........................................................................................12
4.2.7 FPGA Bitstream formatting ..............................................................................14
4.2.8 DDR2SDRAM .....................................................................................................14
4.2.9 Sundance Rocket io Serial Link ........................................................................16
4.2.10 Sundance Low voltage Bus ................................................................................16
4.2.11 TIM Connectors..................................................................................................17
4.2.12 DIP Switches ......................................................................................................17
4.2.13 Available clocks ..................................................................................................18
4.2.14 LEDs ...................................................................................................................20
4.2.15 Performance........................................................................................................20
4.3 Interface Description ..............................................................................................20
4.3.1 Power Budget .....................................................................................................20
5Footprint ....................................................................................................................22
5.1 Top View..................................................................................................................22
5.2 Bottom View............................................................................................................23
6Pinout.........................................................................................................................24
6.1 FPGA Pin allocation by bank .................................................................................24
6.2 SHB..........................................................................................................................33
6.3 SLB ..........................................................................................................................33
7Qualification Requirements ......................................................................................35
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7.1 Qualification Tests..................................................................................................35
7.1.1 Meet Sundance standard specifications............................................................35
7.1.2 Speed qualification tests ....................................................................................35
7.1.3 Integration qualification tests ...........................................................................35
8Support Packages ......................................................................................................35
9Physical Properties....................................................................................................36
10 Safety .........................................................................................................................37
11 EMC ...........................................................................................................................38
12 Ordering Information ................................................................................................38
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Table of Figures
Figure 1: Block Diagram ........................................................................................................9
Figure 2: CPLD state machine.............................................................................................13
Figure 3: FPGA connections to DDR2SDRAM....................................................................15
Figure 4: FPGA clock buffers usage.....................................................................................19
Figure 5: Top View................................................................................................................22
Figure 7: Bottom view ..........................................................................................................23
Table of Tables
Table 1: DIP switch SW1 position for special reset feature ...............................................17
Table 2: DIP switch SW1 position for the selection of the configuration bitstream source
.......................................................................................................................................18
Table 3: DIP switch SW1 position for the selection of the Flash erase & program
operations. .....................................................................................................................18
Table 4: Coolrunner II resources summary.........................................................................21
Table 5:Coolrunner II pin resources. ...................................................................................21
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1Introduction
The SMT351T is an FPGA TIM module designed to be integrated in modular
systems.
It is designed to connect to the huge range of other TIM modules and carriers
developed by Sundance.
Sundance modular solutions provide flexible and upgradeable systems.
The SMT351T is a TIM module aimed at completing the range of Sundance
Virtex4 and Virtex5 modules like SMT362, SMT339.
It provides a communications platform between an XC5VSXT/LXT device and
•2 banks of DDR2 SDRAM at a frequency of up to 250Mhz.
•4 RSL, connectors (up to 4 times .4 MGTs)
•LVDS connections for high speed parallel connections
•LVTTL connections and connectors.
This variety of connectors and interfaces provides a wide range of development
options for designers to explore the capabilities of the comprehensive Sundance
TIM modules family.
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & User’s guide) for single width modules.
It sits on a carrier board.
The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links
(Comport links or for some RSL links as well) between all the modules fitted and a
pathway to the host.
The SMT351T requires a 3.3V power supply (as present on all Sundance TIM
carrier boards), which must be provided by the two diagonally opposite mounting
holes.
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2Related Documents
2.1 Referenced Documents
Sundance SDB specification
SUNDANCE SHB specification
Sundance SLB specification
Micron DDR2SDRAM 1Gbit (MT47H64M16BT-37E) or
Micron DDR2SDRAM 2Gbit (MT47H128M16BT-37E) device
Spansion S29GLXXXN flash
2.2 Applicable Documents
TI TIM specification & User’s guide
Samtec QSH Catalogue page
Virtex 5 User Guide
3Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
TIM Texas Instruments Module
TI© DSP Texas Instrument Digital Signal Processor
Xilinx© FPGA Xilinx© Field Programmable Gate Array.
DDR2SDRAM Dual Data Rate 2 SDRAM
CP ComPort. Communication interface
RSL Rocket Serial Link
SHB Sundance High-Speed Bus. Communication interface
3.2 Definitions
DSP Module Typically a TIM module hosting a TI DSP and, a Xilinx FPGA.
FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all
functionality.
Firmware A proprietary FPGA design providing some sort of functionality.
Sundance Firmware is the firmware running in an FPGA of a DSP
module.
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4Functional Description
The SMT351T provides a Virtex 5 FPGA, memory and IO connectors to allow the
development of applications ranging from Software defined Radio to MIMO, video,
Signal processing.
Typically, an ADC/DAC mezzanine can be fitted on the SLB connector and memory is
used to store burst data between the outside world/host/other TIMs, while the FPGA
implements functions on that data.
4.1 Block Diagram
FPGA
Virtex-5 FF1136
XC5V
SX50T/LX50T/
SX95T/LX110T
1.0V Core
1.8V/2.5V/3.3V I/O
Xilinx Coolrunner II CPLD
XC2C256CP132 on
Comport3 and
Config&control
JTAG Header
J1 Top Primary TIM
Connector
ComPort/SDL 0 & 3
J2 Bottom Secondary TIM
Connector
ComPort/SDL 1 & 4
4 LEDs
JTAG
204 I/O pins
2 banks of
DDR2SDRAM
2x (64Mx16 or 128Mx16)
11 I/O pins
20 differential pairs
40 TTL IOs Sundance Lo
w
(1 C
o
RSL clock
Flash memory
Local clock
ONL
Y
LX
16 RocketIO links Sundance Ro
c
Serial Link (4
C
Switch
Figure 1: Block Diagram
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4.2 Module Description
Figure 1 presents colour coded blocks regrouping components according to their functionality or
their nature.
The following paragraphs will detail each one of them, but first, here is a global description of each
block.
•Block1 and Block6 Xilinx Virtex 5 XC5VSXT/LXT and configuration scheme for the FPGA.
•Block2: DDR2SDRAM memory banks.
•Block3: IO connectors for general purpose or dedicated interfaces.
•Block4: 50MHz or 125MHz clocks.
•Block5: LEDs for development and in-use monitoring and general purpose use.
4.2.1 FPGA
Xilinx Virtex 5 XC5VSX50T, XC5VLX50T, XC4VSX95T or XC5VLX110T FPGA.
This device is packaged in a FF1136-pin BGA package.
4.2.2 CPLD
Xilinx Coolrunner II device XC2C256-7CP132C.
This device is packaged in a 132-ball BGA type package with a -7 speed grade.
It can be used to configure the FGPA via Comport 3, or from a configuration stored in flash
memory.
The flash memory is programmed using the CPLD and via the ComPort3.
4.2.3 FLASH MEMORY
S29GL256N11TFI01 is a 256Mbit flash from Spansion.
It can be used to configure the FPGA at power up.
Flash accessed using Comport3 via the CPLD.
Flash programming selection via switch SW1 (See Table 3)
Software Library Support available from Sundance.
The code can run on Sundance DSP TIM or a Host.
All the flash functionalities are available.
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