SunPlus CPU6502 User manual

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CPU6502 Instruction Manual v2.1
©2005 Sunplus Technology, Co., Ltd.
ALL RIGHTS RESERVED
Sunplus Technology reserves the right to change this documentation without prior notice.
Information provided by Sunplus Technology is believed to be accurate and reliable.
However, Sunplus Technology makes no warranty for any errors which may appear in this
document. Contact Sunplus Technology to obtain the latest version of device specifications
before placing your order.
No responsibility is assumed by Sunplus Technology for any infringement of patent or other
rights of third parties which may result from its use. In addition, Sunplus products are not
authorized for use as critical components in life support devices/ systems or aviation
devices/systems, where a malfunction or failure of the product may reasonably be expected to
result in significant injury to the user, without the express written approval of Sunplus.
If you have suggestions on this documentation which can better serve your needs, please
contact:
Sunplus Technology
No. 19, Innovation Road 1, Science-Based Industrial Park,
Hsin-Chu, Taiwan, R.O.C.
FAX: [phone]

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CONTENT
Revision History.............................................................................................................5
General Description.......................................................................................................7
Register .........................................................................................................................8
Status Register (P) .................................................................................................9
Stack.....................................................................................................................10
Stack Pointer (SP)................................................................................................11
Addressing Mode.........................................................................................................12
Immediate addressing mode ................................................................................12
Absolute addressing mode...................................................................................13
Absolute indexed addressing mode......................................................................14
Zero Page Addressing Mode................................................................................15
Zero Page Indexed addressing Mode...................................................................16
Implied addressing mode......................................................................................17
Accumulator addressing mode .............................................................................17
Indexed indirect addressing mode........................................................................18
Indirect addressing mode .....................................................................................19
Indirect Indexed addressing mode........................................................................20
Relative addressing mode....................................................................................21
Format of Assembly Language Instruction...................................................................22
Instructions ..................................................................................................................23
ADC......................................................................................................................23
AND......................................................................................................................24
ASL.......................................................................................................................25
BCC/BCS/BEQ/BMI/BNE/BPL/BVC/BVS.............................................................26
BIT........................................................................................................................27
CLC ......................................................................................................................28
CLD ......................................................................................................................28
CLI........................................................................................................................28
CLR ......................................................................................................................28
CLV.......................................................................................................................30
CMP......................................................................................................................30
CPX......................................................................................................................31
CPY......................................................................................................................31
DEC......................................................................................................................32
DEX......................................................................................................................32
DEY......................................................................................................................33
EOR......................................................................................................................33

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INC .......................................................................................................................34
INV........................................................................................................................34
INX........................................................................................................................35
INY........................................................................................................................36
JMP ......................................................................................................................36
JSR.......................................................................................................................37
LDA.......................................................................................................................37
LDX.......................................................................................................................37
LDY.......................................................................................................................38
LSR.......................................................................................................................39
NOP......................................................................................................................39
ORA......................................................................................................................40
PHA......................................................................................................................40
PHP......................................................................................................................41
PLA.......................................................................................................................41
PLP.......................................................................................................................41
ROL......................................................................................................................42
ROR......................................................................................................................43
RTI........................................................................................................................43
RTS ......................................................................................................................43
SBC......................................................................................................................44
SEC......................................................................................................................45
SED......................................................................................................................45
SEI........................................................................................................................45
SET.......................................................................................................................45
STA.......................................................................................................................47
STX.......................................................................................................................47
STY.......................................................................................................................48
TAX.......................................................................................................................48
TAY.......................................................................................................................49
TST.......................................................................................................................49
TSX.......................................................................................................................49
TXA.......................................................................................................................50
TXS.......................................................................................................................50
TYA.......................................................................................................................50
Summary of Available Instruction set for each CPU Type ...........................................52

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Revision History
Revision Date By Remark
V2.1 09/13/2005 Joe Chuang 1. Added SPCP bodies in the 65N02 and CPU12 body lists (page.7)
2. Changed the name “Sunplus code＂to “CPU12＂in the tables of
the Instructions
V2.0 12/08/2004 Bean Wang Page 9: Remove B Flag of status register(P)
Was: P: {N,V,X,B,D,I,Z,C}. (X: Not Used)
Now: P: {N,V,X,X,D,I,Z,C}. (X: Not Used)
Page 27: Remove BRK instruction
Page 23~57: Add 65b02 instruction.
Page 25: ASL aaaa, X
Modify: No. Cycle of 65n02 from 7 to 6*.
Page 36: JMP(aaaa)
Modify: No. Cycle of 65n02, 65r02, 65s02, Sunplus Code from 3 to 6.
Page 39: LSR aaaa, X
Modify: No. Cycle of 65n02 from 7 to 6*.
Page 42: ROL aaaa, X
Modify: No. Cycle of 65n02 from 7 to 6*.
Page 43: ROR aaaa, X
Modify: No. Cycle of 65n02 from 7 to 6*.
V1.9 02/06/2004 J. K. Chen Page 30: CMP
Was: C: Set if a “borrow” not occurred. (A > M)
Now: C: Set if a “borrow” not occurred. (A > = M)
Page 31: CPX
Was: C: Set if a “borrow” occurred (data > X).
Now: C: Set if a “borrow” not occurred. (X > = data)
Page 31: CPY
Was: C: Set if a “borrow” occurred (data > Y).
Now: C: Set if a “borrow” not occurred. (Y > = data)
Page 7: remove the CPU type table
Page 38: LDX
Zero Page, (LDX aa, Y), Sunplus Opcode changed from E9H to B9H.
Page 38:
65r02 and Sunplus Code supports LDX aaaa.
Page 44: SBC
Was: C: Set if there is no “borrow” occurred. (M > A).
Now: C: Set if there is no “borrow” occurred. (A > M).
V1.8 12/25/2002 Michael Lin Page 27: BIT:
Set if the bit7 of the result is 1 Æset if the memory bit7 of the result is 1.
Set if the bit6 of the result is 1 Æset if the memory bit6 of the result is 1.
Correct the STA, STX, STY, TXS to no effect on status register
V1.7 01/07/2002 Michael Lin Page 41
Origin: “PLA” takes no effect on any status flag
Modified: “PLA” affect the “N” and “Z” flags.
Origin: “PLP” takes no effect on any status flag.
Modified: “PLP” affects all status flags.
V1.6 08/30/2001 Michael Lin Page 31
Modify:
From: C: Set if a “borrow” occurred. (M > A)
To: C: Set if a “borrow” not occurred (A > M)

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Revision Date By Remark
V1.5 03/19/2001 Michael Lin Modify:
From: ADC (aa), Y: 6502 Opcode = 1EH
To: ADC (aa), Y: 6502 Opcode = 71H
V1.4 12/12/2000 Michael Lin Page 44, SBC
Origin: C: Set if there is a “borrow” occurred. (M > A).
Modify to: C: Set if there is no “borrow” occurred. (M > A).
V1.3 09/08/2000 Michael Lin Page 7
Update the CPU type of IC. The X2s.,exe is updated to v2.78, 09/08/2000
V1.2 07/18/2000 Michael Lin Page 44
Origin:
SBC: (A-M -C) ÆA, C
Modify to:
SBC: (A-M - C) ÆA, C

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General Description
This manual intends to guide users through the 6502 Instruction sets. All 6502 instructions
are listed in alphabetical order. However, not all 6502 instructions or addressing modes are
available in all SUNPLUS CPUs. To list the types of SUNPLUS CPU, please obtain a tool,
named x2s.exe, and apply the following syntax in a DOS command line:
C:\>x2s /s
Patch-up Tool CopyRight(c) Sep 08 2000 by SUNPLUS.
2500AD Object Code Convert Program Ver 2.78
The corresponding Instruction Set to each body is:
65B02 (Full Set): SPMC652,ECMC653
65N02 (Full Set): (see note.2) SPL61A,SPL130A,SPL191A,
SPDC256A,SPDC512A,SPDC512B,
SPDC1000A,SPDC1000B
SPLB10A,
SPCP05A, SPCP06A, SPCP08A,
SPCP16A, SPCP18A, SPCP25A, SPCP26A,
SPCP825A, SPCP826A, SPCP835A
65R02 (Reduce+BIT+TXA+TAX): SPF02A,SPL02C,SPL02D,
SPL03B,SPL03C,
SPL05A,SPL05B,
SPL06A,SPL06B,
SPLB20A,SPLB20A1,
SPLB21A,SPLB22A,
SPLB23A,SPLB24A,
SPLB25A,SPLB26A
SPL128A,SPLG01
65S02 (Only Reduce Set): SPF06A1,SPF18A1,SPF20A,
SPF30A1,SPF30B,
SPL02A
CPU12 / CPU8: (Reduced instructions+BIT+TXA+TAX)
SPCxxx,SPCRxx,SPMCxx,
SPFA64A,SPFA120A,
SPL08A,SPL08A1,SPL081A,
SPL10A,SPL15A,SPL15B,
SPL25B,SPL25C,SPL30A,
SPL31A,SPL60A,SPL190A,
SPCP02A
Note:
1. Since x2s.exe is updated from time to time, be sure to use the newest version of x2s.exe
2. The CPU type 65N02 has two kinds of body, the one uses standard 6502 OP code, the
other one uses Sunplus OP code. Please refer to the programming guide of the individule
body.

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Register
7 0
A Accumulator
7 0
XIndex Register X
7 0
Y Index Register Y
15 8 7 0
PCH PCL Program Counter
7 0
SP Stack Pointer
7 0
PStatus Register
Register Size Description
Accumulator (A) 8 Bit
A
ccumulator is the only register that can be used for arithmetic or
logic operation such as ADD, SUB, AND, OR and EOR and store
the result in it.
Index Register X 8 Bit X is an index register which can be used as a memory buffer, a
offset, or a counter.
Index Register Y 8 Bit Y is an index register which can be used as a memory buffer, a
offset, or a counter.
Program
Counter(PC) 16 Bit PC is a 16-bit register. Program Counter points to an address location where an instruction is held and waits to be executed by
CPU next. When CPU fetches one instruction to execute, PC is
incremented to the next location in memory from which the next
instruction to be executed will be taken unless a branch is
occurred that will lead PC points to the specified address location.
Stack Pointer(SP) 8 Bit Stack Pointer is an 8-bit register. Normally, SP is used for
storing return address, data of status register or temporary data.
Status Register (P) 8 Bit Status Register usually offers information on result of previous
instruction executed.

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Status Register (P)
7 6 5 4 3 2 1 0
N V D I Z C
Carry Flag, If Carry flag is set, C=1
Zero Flag, If arithmetic or logic operation
resultstozero,Zissetto1;otherwise,
Z=0
Interrupt Disable Flag
If interrupt disable flag is set, I=1, CPU will
ignore interrupt signal.
If interrupt disable flag is clear, I=0, CPU will
accept interrupt signal.
In CPU6502, this is Decimal Mode Flag
In CPU12, this bit is not used.
Not Used
Not Used
OverFlow Flag
IfOverFlowisset,V=1
IfOverFlowisclear,V=0
Negative Flag
If arithmetic or logic operation results to negative, N is
set to 1. otherwise, N=0.
* Note: Not all instructions affect Status Register. A detailed instruction description will be
discussed in later section.

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Stack
In normal use, stack can be used as storing return address, temporary data or register‘s
content. A stack has the property that the last item placed on the stack will be the first item
removed. This property is commonly referred to as last in, first out, or simply LIFO. A
diagram is shown as follows:
In push activity, a value of 30 is pushed first. Then, a value of 40 is pushed. Thus, the value
of 40 is now stored on the top on stack. After all values stored in the stack, the value order is
60, 50, 40, 30.
Now, in pop activity, the value of 60 will be popped out first. Second, the value of 50 will be
popped. Then, 40 and 30 will be popped out in order. Stack is empty after all the values are
popped.
50 50
40 40 40
30 30 30 30
Stack (Push)
Push 30 Push 40 Push 50 Push 60
60
50
40 40
30 30 30
Stack (Pop)
POP 60 POP 50 POP 40 POP 30

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Stack Pointer (SP)
Stack Pointer is a pointer which usually points to an available location where can be stored
pushed data. Normally, stack pointer is extended from FF to 00 in CPU 12. When data is
pushed onto stack, stack pointer will decrease by 1. When data is pulled (popped) from stack,
stack pointer is increased by 1.
First of all, a data 0ABH is pushed onto stack; then, the stack pointer points to the address
location $FE. Second, a data of 0CDH is pushed onto stack and the stack pointer then points
to the address location $FD. Third, a data of 0EFH is pushed onto stack and the stack
pointer is now pointing to the address location $FC.
In the pop activity, the stack pointer will be increased by 1 first; then stack pops the value of
0EFH. The stack pointer is now pointing to the address location $FD. When pop acts again,
stack pointer will be increased by 1 again; then pops the value of 0CDH. At this moment, the
stack pointer is pointing to the address location $FE. Finally, the stack pointer is increased by
1 and pops the value of 0ABH. Now, the stack pointer is pointing to the original address
location $FF. Note that if stack now pops again, the stack pointer will point to location $00.
This is an illegal stack activity since the bottom of stack is $FF.
SP-->FC
SP-->$FD EF
SP-->$FE CD CD
AB AB AB
Stack Pointer, Push
Push AB Push CD Push EF
SP-->$FD
CD SP-->$FE
AB SP-->$FF
Stack Pointer, Pop
POP EF POP CD POP AB
AB

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Addressing Mode
Immediate addressing mode
There is one byte in an immediate addressing mode.
Operation: OP-code #dd
where #dd can be :
binary: #%00000001 or #00000001B
decimal: #01 or #01D
hexdecimal: #01H or #$01
Example:
AND #$08
N V D I Z C
! - - - ! -
Example:
Given: A=7EH
AND #88H
Result:
88 AND 7E Î08H
08H ÆA (08H stored in A)
xx
mm mm
A
SP
X
PC
mmmm+2
xx AND 08
Data Memory
54
08 mmmm
mmmm+1
mmmm+2
Program Memory

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Absolute addressing mode
The absolute addressing mode uses two bytes (adr 16) to specify a memory address. The
adr 16 may be the address of a byte of data or the beginning address for the next instruction.
Operation: OP-code Adr16
Example:
AND $0030
N V D I Z C
! - - - ! -
xx
mm mm
A
SP
X
PC
mmmm+2
xx AND yy
yy
Data Memory
15
30 mmmm
mmmm+1
mmmm+2
Program Memory
0030

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Absolute indexed addressing mode
The absolute indexed addressing mode uses two-part (adr 16 and X) to specify a memory
address.
Operation : OP-code Adr 16, X
Example:
LDA $0500,X
N V D I Z C
! - - - ! -
The new address is $500 + $02 = $502. This operation will copy the data of $502 to
Accumulator. Therefore, Accumulator contains A8.
A8
02
mm mm
A
SP
X
PC
mmmm+3
$500 + $02
A8
Data Memory
0502

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Zero Page Addressing Mode
The zero page addressing mode uses the low-order byte of the address in page zero (adr 08)
to specify a memory address.
Operation: OP-Code Adr 08
Example:
LDA $28
N V D I Z C
! - - - ! -
Copy data from location $28 to Accumulator.
B6
02
mm mm
A
SP
X
PC
B6
Data Memory
0028

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Zero Page Indexed addressing Mode
The zero page indexed addressing mode uses two-part (adr 08 and X) to specify a memory
address.
Operation: OP-Code Adr 08, X
Example:
LDX #$20
LDA #$77
STA $60, X
The new address = $60 + $20 = $80
Store #77H into $80.
77
02
mm mm
A
SP
X
PC 77
B6
Data Memory
0060
0080
36
$20 + $60 = $80

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Implied addressing mode
The implied addressing mode does not have any address.
Operation: OP-Code
Example:
TAX ; To transfer data from accumulator to register X.
CLC ; To clear carry
Accumulator addressing mode
The accumulator addressing mode does not have any address. The instruction operates on
the data in the accumulator.
Operation: OP-Code
Example:
ROLRotate Left with Carry
ROR Rotate Right with Carry
7 6 5 4 3 2 1 0 C
ROL
7 6 5 4 3 2 1 0 C
ROR

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Indexed indirect addressing mode
The pre-indexed indirect addressing mode uses “ (adr 08 and X)” to specify a memory address.
Only register X can be used in this mode. The pre-indexed indirect address is a zero-page
indexed direct address. Thus, the valid address must be on page zero.
Operation : OP-Code (Adr 08, X)
Example:
AND ($20, X)
N V D I Z C
! - - - ! -
xx
rr
mm mm
A
SP
X
PC
qq
yy
pp
Data Memory
ppqq
00rr+20
00rr+21
xx AND yy
+
20
21
mmmm+1
mmmm+2
mmmm+2
1
2
Program Memory

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Indirect addressing mode
Index addressing mode can only use JMP instruction.
Operation: JMP (Adr)
Example:
JMP ($31FE)
PC=ppqq
xx
rr
pp qq
A
SP
X
PC
pp
77
B6
Data Memory
31FE
31FF
qq

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Indirect Indexed addressing mode
Indirect Indexed addressing mode can only be applied for Y index register.
Operation: Opcode (aa), Y
Example:
LDA ($20), Y
N V D I Z C
! - - - ! -
B6
01
02
mm mm
A
SP
X
PC
B6
Data Memory
0713
Y
12
07 0020
0021
0712 + 01 = 0713