Synopsys DesignWare ARC AXC003 User manual

DesignWare ARC AXC003 CPU Card
User Guide
Version 6323-018 May 2017

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Synopsys, Inc. Version 6323-018
May 2017
Copyright Notice and Proprietary Information Notice
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and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys, Inc.
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Mountain View, CA 94043
www.synopsys.com

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Version 6323-018 Synopsys, Inc.
May 2017
Contents
Contents................................................................................................................................................3
List of Figures .......................................................................................................................................7
List of Tables.........................................................................................................................................9
1 Package Contents............................................................................................................................10
1.1 DesignWare ARC AXS103 Software Development Platform ...................................................10
1.2 DesignWare ARC AXC003 CPU Card (Standalone)................................................................11
2 Getting Started.................................................................................................................................12
2.1 Mounting the CPU Card...........................................................................................................12
2.2 Performing a Self-Test .............................................................................................................12
3 Default Board Settings.....................................................................................................................15
3.1 Default Jumper Settings on the AXC003 CPU Card ................................................................15
3.2Default Boot-Mode Settings on the ARC SDP Mainboard........................................................16
4 CPU Core Selection.........................................................................................................................17
4.1 Supported CPU Cores..............................................................................................................17
4.2 Core Selection..........................................................................................................................17
ARC HS36 CPU................................................................................................................18
ARC HS34 CPU................................................................................................................18
ARC HS38 Core 0.............................................................................................................18
ARC HS38 Core 1.............................................................................................................18
5 Self-Tests.........................................................................................................................................19
5.1 Self-Test Overview...................................................................................................................19
5.2 Executing the Self-Test of the ARC HS36 Core.......................................................................22
5.3 Executing the Self-Test of the ARC HS38x2 Core ...................................................................23
5.4 Restoring the Self-Tests in the SPI Flash.................................................................................25
6 Hardware Functional Description.....................................................................................................27
6.1 Board Overview........................................................................................................................27
6.2 Board Interface Overview.........................................................................................................30
Power Supply Connector ..................................................................................................30
HapsTrak II Connectors (Bottom)......................................................................................30
HapsTrak II Connectors (Top)...........................................................................................31
Mictor Connectors.............................................................................................................31
6.3 Jumpers ...................................................................................................................................31
6.4 LEDs ........................................................................................................................................32
6.5 Pushbutton...............................................................................................................................33
6.6 Seven-Segment Displays.........................................................................................................34
6.7 AXC003 Processor FPGA Overview........................................................................................35
Main Features of the ARC Cores......................................................................................35
PAE...................................................................................................................................37
I/O Coherency...................................................................................................................38
Interrupts...........................................................................................................................39
Clock.................................................................................................................................46
Reset.................................................................................................................................48

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DesignWare ARC AXC003 CPU Card User Guide Contents
Synopsys, Inc. Version 6323-018
May 2017
Debug ...............................................................................................................................49
Control Registers ..............................................................................................................50
GPIO Registers.................................................................................................................52
DIP Switches for FPGA Image Selection..........................................................................55
ARC HS34 Emulation........................................................................................................56
6.8 Memories on the AXC003 CPU Card.......................................................................................57
6.9 Power Supply...........................................................................................................................58
6.10Audio Support ..........................................................................................................................59
6.11Usage of ARC SDP Mainboard Resources..............................................................................59
Usage of the Mainboard DIP Switches..............................................................................59
Usage of the Mainboard Pushbuttons...............................................................................62
Usage of the Mainboard LEDs..........................................................................................63
7 System Memory Map.......................................................................................................................65
7.1 System Memory Map After a Reset..........................................................................................65
7.2 System Memory Map After Pre-Bootloader Execution.............................................................65
7.3 Controlling the Memory Map....................................................................................................67
Setting Up the AXI Masters on the AXC003 CPU Card ....................................................67
Setting Up the AXI Masters on the ARC SDP Mainboard.................................................68
Example Register Settings for the Default Memory Map...................................................69
7.4 Memory Map of the Local Peripherals......................................................................................71
8 Programmer’s Reference .................................................................................................................72
8.1 Supported Tools and Operating Systems.................................................................................72
8.2 Boot Modes..............................................................................................................................72
Common Boot Modes .......................................................................................................72
ARC HS36 Booting from ICCM0.......................................................................................73
8.3 Pre-Boot...................................................................................................................................74
Pre-Boot Overview............................................................................................................74
8.4 Drivers......................................................................................................................................77
Drivers for Bare-Metal Applications...................................................................................77
7.4.2 Drivers for MQX..................................................................................................................78
8.5 Bare-Metal Package.................................................................................................................78
Overview...........................................................................................................................78
Building Bare-Metal Applications Using the MetaWare IDE..............................................79
Building Bare-Metal Applications Using gmake.................................................................83
Hardware Setup for Debugging.........................................................................................85
Running a Bare-Metal Application in the MetaWare IDE Debugger..................................87
Running a Bare-Metal Application in the MetaWare Debugger.........................................90
Storing an Image in the SPI Flash and Running the Application.......................................94
8.6 MQX Package..........................................................................................................................96
Overview...........................................................................................................................96
Building MQX Applications Using gmake..........................................................................97
Hardware Setup for Debugging.........................................................................................98
Running MQX Applications in the MetaWare Debugger ...................................................98
8.7 Linux and U-Boot Packages.....................................................................................................99
Overview...........................................................................................................................99
Hardware Setup for Debugging.......................................................................................100

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Contents DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
Executing the Linux Image with U-Boot ..........................................................................100
8.8 ARCv2 Instruction Set: Usage Limitations..............................................................................107
9 Software Interfaces........................................................................................................................108
9.1 Clock-Generation Registers...................................................................................................108
TUNNEL PLL ..................................................................................................................108
ARC PLL.........................................................................................................................111
9.2 AXI Tunnel Address Decoder Registers.................................................................................114
TUN_A_SLV0: AXI Tunnel Slave Select Register 0........................................................114
TUN_A_SLV1: AXI Tunnel Slave Select Register 1........................................................114
TUN_A_OFFSET0: AXI Tunnel Address Offset Register 0.............................................115
TUN_A_OFFSET1: AXI Tunnel Address Offset Register 1.............................................116
TUN_A_UPDATE: AXI Tunnel Update Register .............................................................116
9.3 ARC CPU Address Decoder Registers ..................................................................................117
CPU_A_SLV0: ARC CPU Slave Select Register 0.........................................................117
CPU_A_SLV1: ARC CPU Slave Select Register 1.........................................................117
CPU_A_OFFSET0: ARC CPU Address Offset Register 0..............................................118
CPU_A_OFFSET1: ARC CPU Address Offset Register 1..............................................119
CPU_A_UPDATE: ARC CPU Update Register...............................................................119
9.4 ARC RTT Address Decoder Registers...................................................................................120
RTT_A_SLV0: ARC RTT Slave Select Register 0 ..........................................................120
RTT_A_SLV1: ARC RTT Slave Select Register 1 ..........................................................120
RTT_A_OFFSET0: ARC RTT Address Offset Register 0...............................................121
RTT_A_OFFSET1: ARC RTT Address Offset Register 1...............................................122
RTT_A_UPDATE: ARC RTT Update Register................................................................122
9.5 PAE Registers........................................................................................................................123
PAE: PAE Register .........................................................................................................123
PAE_UPDATE: PAE Update Register ............................................................................123
9.6 CPU Start Registers...............................................................................................................124
CPU_START: ARC CPU Start Register..........................................................................124
CPU_0_ENTRY: ARC CPU-0 Kernel Entry Point Register.............................................125
CPU_1_ENTRY: ARC CPU-1 Kernel Entry Point Register.............................................125
CPU_BOOT: Boot Register.............................................................................................125
9.7 AXI Tunnel Registers .............................................................................................................126
TUN_CTRL Register.......................................................................................................126
TUN_STAT Register.......................................................................................................126
9.8 GPIO Registers......................................................................................................................127
GPIO_SWPORTA_DR: GPIO Port A Output Register....................................................127
GPIO_SWPORTB_DR: GPIO Port B Output Register....................................................128
GPIO_EXT_PORTA: GPIO Port A Input Register...........................................................129
GPIO_EXT_PORTB: GPIO Port B Input Register...........................................................130
Appendix A........................................................................................................................................132
A.1 Mounting the AXC003 CPU Card...........................................................................................132
Appendix B........................................................................................................................................134
B.1 Installing and Configuring PuTTY...........................................................................................134
Appendix C .......................................................................................................................................137
C.1 Detailed Core Configurations.................................................................................................137

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DesignWare ARC AXC003 CPU Card User Guide Contents
Synopsys, Inc. Version 6323-018
May 2017
Glossary and References .................................................................................................................144
Glossary........................................................................................................................................144
References....................................................................................................................................145

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Version 6323-018 Synopsys, Inc.
May 2017
List of Figures
DesignWare ARC AXS103 Software Development Platform..........................................................10
DesignWare ARC AXC003 CPU Card............................................................................................11
Location of the ARC SDP Mainboard Power Supply and Power Switch.........................................13
ARC SDP Mainboard Status LEDs After Power-On .......................................................................13
AXC003 CPU Card Power-Control LEDs After Power-On..............................................................14
Default Jumper Settings on the AXC003 CPU Card.......................................................................15
Default Settings of the DIP Switches on the ARC SDP Mainboard ................................................16
Location of the CPU LEDs on the ARC SDP Mainboard................................................................21
Location of the LED121x on the AXC003 CPU Card......................................................................21
Location of the ARC SDP Mainboard’s Power Supply and Power Switch ......................................22
Location of the CPU Start Button SW2504 for the ARC HS36 Core...............................................22
ARC HS36 Self-Test.......................................................................................................................23
Location of the RESET Button on the ARC SDP Mainboard ..........................................................23
Location of the ARC SDP Mainboard’s Power Supply and Power Switch ......................................24
Location of the CPU Start Button SW2504 for the ARC HS38x2 Core...........................................24
Screen-Shot of ARC HS38x2 Self-Test ..........................................................................................25
Location of the RESET Button on the ARC SDP Mainboard ..........................................................25
Hardware Block Diagram (HS36)....................................................................................................28
Hardware Block Diagram (HS38x2)................................................................................................29
Location of the Power Control LEDs on the AXC003 CPU Card ....................................................32
Location of the User LEDs on the AXC003 CPU Card ...................................................................32
Location of the Pushbutton on the AXC003 CPU Card...................................................................34
AXC003 Memory Map.....................................................................................................................37
AXC003 I/O Coherency Architecture ..............................................................................................38
I/O Coherency and PAE..................................................................................................................39
HS36 Interrupt Architecture.............................................................................................................41
HS38x2 Interrupt Architecture.........................................................................................................42
Clock Architecture...........................................................................................................................47
Location of the RESET Button on the ARC SDP Mainboard ..........................................................48
JTAG Daisy-Chain ..........................................................................................................................49
Pinout of the Power Supply Connector (Bottom View)....................................................................59
Location of the Power Control LEDs on the AXC003 CPU Card....................................................59
Function and Default Settings of the DIP Switches on the ARC SDP Mainboard...........................62
Location of the CPU Start Buttons on the ARC SDP Mainboard. ...................................................63
Location of the CPU LEDs on the ARC SDP Mainboard................................................................64
Default settings of the DIP Switches on the ARC SDP Mainboard.................................................75
Pre-Boot Mechanism.......................................................................................................................76
MetaWare IDE - Select Workspace Directory.................................................................................80
MetaWare IDE –Importing Existing Projects..................................................................................80
MetaWare IDE - Set Active Build Configurations............................................................................81
MetaWare IDE –Build Results in Console Window........................................................................82
Build Script Options.........................................................................................................................83
Settings of the DIP Switches on the ARC SDP Mainboard for Using the Debugger.......................85
Location of the Debug Interfaces and the Corresponding Jumpers................................................86
Location of the ARC SDP Mainboard’s Power Supply and Power Switch ......................................86
Location of the CPU Start Buttons on the ARC SDP Mainboard. ...................................................87

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DesignWare ARC AXC003 CPU Card List of Figures
Synopsys, Inc. Version 6323-018
May 2017
Creating a New Process .................................................................................................................90
Debugger options –Command-Line Options..................................................................................91
Debugger Options –Target Selection.............................................................................................92
Specifying a Path to the .elf File......................................................................................................92
Debugger Status.............................................................................................................................93
HyperTerminal Output.....................................................................................................................94
DIP Switch Settings for Autonomous Code Execution on the ARC Core .......................................96
Default Settings of the DIP Switches on the ARC SDP Mainboard. .............................................133
Identification of COM Port.............................................................................................................135
PuTTY Configuration.....................................................................................................................136

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Version 6323-018 Synopsys, Inc.
May 2017
List of Tables
Table 1 Self-Test Start Buttons....................................................................................................................20
Table 2 Characters on the Seven-Segment Display During the Self-Test...................................................21
Table 3 Jumper Functionality.......................................................................................................................31
Table 4 LED Control Bits..............................................................................................................................33
Table 5 Control Bits of the Seven-Segment Displays..................................................................................35
Table 6 Main Features of the ARC Cores....................................................................................................36
Table 7 Interrupt Mapping for ARC HS36....................................................................................................43
Table 8 Interrupt Mapping for ARC HS38....................................................................................................44
Table 9 Mainboard ICTL Interrupt Mapping .................................................................................................45
Table 10 Clock Frequencies ..........................................................................................................................48
Table 11 JTAG ID Codes...............................................................................................................................49
Table 12 Control Register Memory Map........................................................................................................50
Table 13 GPIO Register Memory Map...........................................................................................................52
Table 14 GPIO Port A Output Register Bit Function (SWPORTA_DR).........................................................52
Table 15 GPIO port A Input Register Function (EXT_PORTA)......................................................................53
Table 16 GPIO port B Output Register Function (SWPORTB_DR)...............................................................54
Table 17 GPIO port B input register function (EXT_PORTB) ........................................................................55
Table 18 Memory mapping for ARC HS36.....................................................................................................56
Table 19 Memory mapping for HS34 Emulation ............................................................................................57
Table 20 Pinout of the Power-Supply Connector...........................................................................................58
Table 21 ARC Core Boot Configuration (Mainboard DIP Switch SW2501) ...................................................60
Table 22 Multicore Configuration (Mainboard DIP Switch SW2503) .............................................................61
Table 23 Usage of the CPU Start Buttons of the ARC SDP Mainboard ........................................................63
Table 24 Control Bits of the CPU LEDs on the ARC SDP Mainboard ...........................................................64
Table 25 ARC CPU Memory Map After Pre-Bootloader Execution ...............................................................65
Table 26 AXI Tunnel Memory Map After Pre-Bootloader Execution (ARC HS34 / HS36).............................67
Table 27 AXI Tunnel Memory Map After Pre-Bootloader Execution (ARC HS38).........................................67
Table 28 AXC003 CPU Card Target Slaves ..................................................................................................68
Table 29 ARC SDP Mainboard Target Slaves...............................................................................................68
Table 30 ARC CPU Memory Map Pre-Boot Programming on the AXC003 CPU Card .................................69
Table 31 Memory Map Pre-Boot Programming for All Masters on the ARC SDP Mainboard .......................70
Table 32 Peripheral Memory Map..................................................................................................................71
Table 33 Meaning of the Left Character of the Seven-Segment Display.......................................................76
Table 34 Meaning of the Right Character of the Seven-Segment Display.....................................................77
Table 35 baremetal Folder Contents..............................................................................................................78
Table 36 Build Options...................................................................................................................................81
Table 37 Command Line Options for build.bat...............................................................................................83
Table 38 CPU Start Buttons and Display Values for Running Applications in the Debugger ........................87
Table 39 Property Arguments for Selecting the CPU Core in the Debugger .................................................91
Table 40 MQX folder Contents.......................................................................................................................97
Table 41 GPIO port A Output Register (GPIO_SWPORTA_DR).................................................................127
Table 42 GPIO port B output Register (GPIO_SWPORTB_DR) .................................................................128
Table 43 GPIO Port A Input Register (GPIO_EXT_PORTA).......................................................................129
Table 44 GPIO Port B Input Register (GPIO_EXT_PORTB).......................................................................130

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Synopsys, Inc. Version 6323-018
May 2017
1
Package Contents
1.1 DesignWare ARC AXS103 Software Development
Platform
The DesignWare ARC AXS103 Software Development Platform package contains the
following items:
DesignWare ARC AXC003 CPU Card mounted on ARC SDP Mainboard
100-240V AC power adapter (including power cables for U.S., UK, and EU outlets)
USB cable
Pen-sized plastic dipstick for actuating DIP switches
DesignWare ARC AXS103 Software Development Platform
Warning
The AXC003 CPU Card and the ARC SDP Mainboard contain static-sensitive devices.