Alinx KINTEX-7FPGA User manual

KINTEX-7 FPGA
Development Board
AX7325B
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.1
2022-08-30
Rachel Zhou
First Release

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Table of Contents
Version Record .............................................................................................2
Part 1: FPGA Development Board Introduction .......................................... 5
Part 2: FPGA Chip ....................................................................................... 8
Part 3:DDR3 DRAM ...................................................................................10
Part 4:SODIMM memory module interface ............................................... 16
Part 5: QSPI Flash .....................................................................................21
Part 6: Clock configuration ........................................................................ 23
Part7: USB to Serial Port ...........................................................................24
Part 8: SFP Interface ................................................................................. 25
Part 9: QSFP+ Fiber interface ................................................................... 28
Part 10: PCIe slot .......................................................................................30
Part 11: Temperature Sensor .....................................................................32
Part 12: SD Card Slot ................................................................................ 33
Part 13: FMC connector .............................................................................35
Part 14: Expansion Header ....................................................................... 39
Part 15: LED Light ......................................................................................41
Part16: User Buttons ................................................................................. 43
Part 17: JTAG Interface ............................................................................. 44
Part 18: Power Supply ............................................................................... 45
Part19: Fan ................................................................................................ 47
Part 20: Structure Diagram ........................................................................49

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The AX7325B FPGA development board, it is the XILINX KINTEX-7 FPGA
development platform.
The AX7325B FPGA development platform uses XILINX's KINTEX-7 chip
XC7K325 solution. The FPGA development board mounts four pieces of
512MB high-speed DDR3 SDRAM chips, and a SODIMM interface on the
board is used to expand the memory strip of DDR3. FPGA chip configuration
uses a 128Mb QSPI FLASH chip
In the design of expansion board, we have extended a wealth of interfaces
for users, such as 1 PCIex8 interface, 4 10G SFP interface, 1 40G QSFP+
optical interface, 1 UART serial port, 1 SD card slot, 1 FMC extension port, 1
40-pin expansion ports. It meets users' requirements for high-speed data
exchange, data storage, video transmission processing and industrial control. It
is a "professional" FPGA development platform, for high-speed data
transmission and exchange, pre-verification and post-application of data
processing is possible. This product is very suitable for students, engineers and
other groups engaged in KINTEX-7FPGA development.

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Part 1: FPGA Development Board Introduction
The AX7325B FPGA development board is mainly composed of KINTEX-7
main chip, 4 DDR3, 1 memory stick SODIMM interface, 1 QSPI FLASH and
some peripheral interfaces. The FPGA development board uses Xilinx's
KINTEX-7 series of chips, model number XC7K325TFFG900. Four DDR3
memory chips are connected to the HP port of the FPGA chip, each with a
DDR3 capacity of up to 512M bytes, which makes up 64-bit data bandwidth. A
SODIMM interface is connected to the HR port of the FPGA to fit a 64-bit DDR3
memory module. A 128Mb QSPI FLASH is used to statically store configuration
files or other user data of the FPGA chip.
The AX7325B development board expands the rich peripheral interface,
including one PCIex8 interface, four 10G optical SFP interfaces, one 40G
optical fiber + QSFP interface, one UART serial interface, one SD card
interface, and one FMC expansion interface. 1 40-pin expansion port and some
button LEDs.

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Figure 1-1: The Schematic Diagram of the AX7325B
Through this diagram, you can see the interfaces and functions that the
AX7325B FPGA Development Board contains:
Xilinx KINTEX-7 FPGA chip XC7K325TFFG900
DDR3
With four large-capacity 512 Mbytes (2 GB total) high-speed DDR3
SDRAM, used as FPGA data storage, image analysis cache, data
processing.
QSPI FLASH
A 128Mbit QSPI FLASH memory chip can be used as a storage for
FPGA chip configuration files and user data;
PCIe x8 interface
A standard PCIEx8 interface for PCIE communication with computer
motherboards, supports the PCI Express 2.0 standard, and

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single-channel communication rates up to 5Gbps.
4 SFP interfaces
The four high-speed transceivers of the GTX transceiver of the FPGA
are connected to the transmission and reception of four optical modules
to realize four high-speed optical fiber communication interfaces. Each
fiber optic data communication receives and transmits at speeds of up
to 10 Gb/s.
1 QSFP + optical interface
The four high-speed transceivers of the GTX transceiver of the FPGA
are connected to the optical module interface of a QSPF+, to implement
the optical communication interface of the QSFP+. Fiber optic data
communications receive and transmit at speeds of up to 40 Gb/s.
DDR3 memory module interface
One SODIMM memory module interface is used to assemble a DDR3
memory module, and the DDR3 data width of the interface is 64 bits.
The memory stick SODIMM interface expands the storage space and
data bandwidth for the FPGA development board.
USB Uart interface
1-channel Uart to USB interface for communication with the computer
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
Micro SD slot
1 Micro SD card slot
Temperature and humidity sensor
Onboard a temperature and humidity sensor chip LM75 for detecting
the temperature and humidity of the environment around the board
FMC expansion ports
A standard FMC LPC expansion port can be connected to various FMC

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modules of XILINX or ALINX (HDMI input/output module, binocular
camera module, high-speed AD module etc.)
JTAG Interface
A 10-pin0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download FPGAs through
XILINX downloader.
Clock
2 * 200Mhz differential crysta, A 156.25Mhz and A 125Mhz on the
board .
LED Light
6LEDs, 1 power indicator, 1 DONE configuration indicator, 4 FPGA
control indicators
Button
2 user buttons, connect to the normal IO of the FPGA.
Part 2: FPGA Chip
The FPGA development board uses Xilinx's KINTEX-7 FPGA chip, model
number XC7K325T-2FFG900I. The speed class is 2 and the temperature class
is industrial. This model is a FGG900 package with 900 pins and a 1.0mm pitch.
The chip naming rules for Xilinx KINTEX-7 FPGA are shown in Figure 2-1
below:
Figure 2-1: The Specific Chip Model Definition of KINTEX-7 Series

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Figure 2-2: FPGA chip XC7K325T on board
The main parameters of the FPGA chip XC7K325T are as follows
Name
Specific parameters
Logic Cells
33,280
Slices
5,200
CLB flip-flops
41,600
Block RAM（kb）
1,800
DSP48 Slices
90
PCIe Gen2
1
XADC
12bit, 1Mbps AD
GTP Transceiver
16，12.5Gb/s max
Speed Grade
-2
Temperature Grade
Industrial
FPGA power supply system
KINTEX-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO VCCO,
VMGTAVCC and VMGTAVTT. VCCINT is the FPGA core power supply pin, which needs to
be connected to 1.0V; VCCBRAM is the power supply pin of FPGA Block RAM,
connect to 1.0V; VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO

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is the voltage of each BANK of FPGA, including BANK0, BANK12~18,
BANK32~34. On the AX7325B development board, BANK12~13 is connected
to the FMC connector. The default voltage of VCCO is 2.5V, which enables IO to
support LVDS interface. BANK16~18, BANK33~35 need to connect DDR3
memory and DDR3 chip, BANK voltage is 1.5V, other BANK voltage is 3.3V.
VMGTAVCC is the supply voltage of the internal GTP transceiver of the FPGA,
connected to 1.0V, VMGTAVTT is the termination voltage of the GTP transceiver,
connected to 1.2V.
The KINTEX-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX and finally VCCO. If VCCINT and VCCBRAM
have the same voltage, they can be powered up at the same time. The order of
power outages is reversed. The power-up sequence of the GTP transceiver is
VCCINT, then VMGTAVCC, then VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage,
they can be powered up at the same time. The power-off sequence is just the
opposite of the power-on sequence.
Part 3:DDR3 DRAM
TheAX7325B FPGA development board is equipped with four 512MB
DDR3 chips, model MT41K256M16HA-125 (Compatible with
MT41J256M16HA-125). Four DDR3 SDRAMs form a 64-bit bus width.
Because four DDR3 chips are connected to the HP port of the FPGA, the
DDR3 SDRAM can run at speeds up to 800MHz (data rate 1600Mbps), and
four DDR3 memory systems are directly connected to the BANK32, BANK33,
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
Bit Number
Chip Model
Capacity
Factory
U3,U4,U6,U7
MT41K256M16HA-125
Or
MT41J256M16HA-125
256M x 16bit
Micron

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Table 3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of
signal integrity. We have fully considered the matching resistor/terminal
resistance, trace impedance control, and trace length control in circuit
design and PCB design to ensure high-speed and stable operation of
DDR3.
Figure 3-1: The DDR3 DRAM Schematic

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Figure 3-2: The DDR3 on the FPGA Board
4 DDR3 DRAM pin assignments:
Signal Name
FPGA Pin Name
FPGA Pin
DDR3_D0
IO_L13P_T2_MRCC_32
AD18
DDR3_D1
IO_L16N_T2_32
AB18
DDR3_D2
IO_L14P_T2_SRCC_32
AD17
DDR3_D3
IO_L17P_T2_32
AB19
DDR3_D4
IO_L14N_T2_SRCC_32
AD16
DDR3_D5
IO_L17N_T2_32
AC19
DDR3_D6
IO_L13N_T2_MRCC_32
AE18
DDR3_D7
IO_L18P_T2_32
AB17
DDR3_D8
IO_L8P_T1_32
AG19
DDR3_D9
IO_L7N_T1_32
AK19
DDR3_D10
IO_L10P_T1_32
AD19
DDR3_D11
IO_L7P_T1_32
AJ19
DDR3_D12
IO_L11P_T1_SRCC_32
AF18
DDR3_D13
IO_L8N_T1_32
AH19

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DDR3_D14
IO_L10N_T1_32
AE19
DDR3_D15
IO_L11N_T1_SRCC_32
AG18
DDR3_D16
IO_L1N_T0_32
AK15
DDR3_D17
IO_L5N_T0_32
AJ17
DDR3_D18
IO_L2N_T0_32
AH15
DDR3_D19
IO_L4P_T0_32
AF15
DDR3_D20
IO_L4N_T0_32
AG14
DDR3_D21
IO_L5P_T0_32
AH17
DDR3_D22
IO_L2P_T0_32
AG15
DDR3_D23
IO_L1P_T0_32
AK16
DDR3_D24
IO_L19P_T3_32
AE15
DDR3_D25
IO_L24P_T3_32
Y16
DDR3_D26
IO_L22P_T3_32
AC14
DDR3_D27
IO_L20P_T3_32
AA15
DDR3_D28
IO_L23P_T3_32
AA17
DDR3_D29
IO_L22N_T3_32
AD14
DDR3_D30
IO_L23N_T3_32
AA16
DDR3_D31
IO_L20N_T3_32
AB15
DDR3_D32
IO_L22N_T3_34
AK6
DDR3_D33
IO_L23P_T3_34
AJ8
DDR3_D34
IO_L22P_T3_34
AJ6
DDR3_D35
IO_L19P_T3_34
AF8
DDR3_D36
IO_L24N_T3_34
AK4
DDR3_D37
IO_L23N_T3_34
AK8
DDR3_D38
IO_L24P_T3_34
AK5
DDR3_D39
IO_L20N_T3_34
AG7
DDR3_D40
IO_L10P_T1_34
AE4
DDR3_D41
IO_L8N_T1_34
AF1
DDR3_D42
IO_L11P_T1_SRCC_34
AE5
DDR3_D43
IO_L8P_T1_34
AE1
DDR3_D44
IO_L12P_T1_MRCC_34
AF6
DDR3_D45
IO_L10N_T1_34
AE3
DDR3_D46
IO_L11N_T1_SRCC_34
AF5
DDR3_D47
IO_L7N_T1_34
AF2

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DDR3_D48
IO_L13P_T2_MRCC_34
AH4
DDR3_D49
IO_L16N_T2_34
AJ2
DDR3_D50
IO_L14N_T2_SRCC_34
AH5
DDR3_D51
IO_L13N_T2_MRCC_34
AJ4
DDR3_D52
IO_L16P_T2_34
AH2
DDR3_D53
IO_L17N_T2_34
AK1
DDR3_D54
IO_L14P_T2_SRCC_34
AH6
DDR3_D55
IO_L17P_T2_34
AJ1
DDR3_D56
IO_L2P_T0_34
AC2
DDR3_D57
IO_L4P_T0_34
AC5
DDR3_D58
IO_L1N_T0_34
AD3
DDR3_D59
IO_L6P_T0_34
AC7
DDR3_D60
IO_L5N_T0_34
AE6
DDR3_D61
IO_L5P_T0_34
AD6
DDR3_D62
IO_L2N_T0_34
AC1
DDR3_D63
IO_L4N_T0_34
AC4
DDR3_DM0
IO_L16P_T2_32
AA18
DDR3_DM1
IO_L12P_T1_MRCC_32
AF17
DDR3_DM2
IO_L6P_T0_32
AE16
DDR3_DM3
IO_L24N_T3_32
Y15
DDR3_DM4
IO_L20P_T3_34
AF7
DDR3_DM5
IO_L7P_T1_34
AF3
DDR3_DM6
IO_L18P_T2_34
AJ3
DDR3_DM7
IO_L1P_T0_34
AD4
DDR3_DQS0_P
IO_L15P_T2_DQS_32
Y19
DDR3_DQS0_N
IO_L15N_T2_DQS_32
Y18
DDR3_DQS1_P
IO_L9P_T1_DQS_32
AJ18
DDR3_DQS1_N
IO_L9N_T1_DQS_32
AK18
DDR3_DQS2_P
IO_L3P_T0_DQS_32
AH16
DDR3_DQS2_N
IO_L3N_T0_DQS_32
AJ16
DDR3_DQS3_P
IO_L21P_T3_DQS_32
AC16
DDR3_DQS3_N
IO_L21N_T3_DQS_32
AC15
DDR3_DQS4_P
IO_L21P_T3_DQS_34
AH7
DDR3_DQS4_N
IO_L21N_T3_DQS_34
AJ7

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DDR3_DQS5_P
IO_L9P_T1_DQS_34
AG4
DDR3_DQS5_N
IO_L9N_T1_DQS_34
AG3
DDR3_DQS6_P
IO_L15P_T2_DQS_34
AG2
DDR3_DQS6_N
IO_L15N_T2_DQS_34
AH1
DDR3_DQS7_P
IO_L3P_T0_DQS_34
AD2
DDR3_DQS7_N
IO_L3N_T0_DQS_34
AD1
DDR3_A0
IO_L1P_T0_33
AA12
DDR3_A1
IO_L1N_T0_33
AB12
DDR3_A2
IO_L2P_T0_33
AA8
DDR3_A3
IO_L2N_T0_33
AB8
DDR3_A4
IO_L3P_T0_DQS_33
AB9
DDR3_A5
IO_L3N_T0_DQS_33
AC9
DDR3_A6
IO_L6N_T0_VREF_33
AB13
DDR3_A7
IO_L4N_T0_33
Y10
DDR3_A8
IO_L5P_T0_33
AA11
DDR3_A9
IO_L5N_T0_33
AA10
DDR3_A10
IO_L6P_T0_33
AA13
DDR3_A11
IO_L8P_T1_33
AD8
DDR3_A12
IO_L7P_T1_33
AB10
DDR3_A13
IO_L7N_T1_33
AC10
DDR3_A14
IO_L15P_T2_DQS_33
AJ9
DDR3_BA0
IO_L8N_T1_33
AE8
DDR3_BA1
IO_L9P_T1_DQS_33
AC12
DDR3_BA2
IO_L9N_T1_DQS_33
AC11
DDR3_WE
IO_L10P_T1_33
AD9
DDR3_RAS
IO_L10N_T1_33
AE9
DDR3_CAS
IO_L11P_T1_SRCC_33
AE11
DDR3_S0
IO_L11N_T1_SRCC_33
AF11
DDR3_CKE0
IO_L12P_T1_MRCC_33
AD12
DDR3_ODT
IO_L12N_T1_MRCC_33
AD11
DDR3_CLK0_P
IO_L13P_T2_MRCC_33
AG10
DDR3_CLK0_N
IO_L13N_T2_MRCC_33
AH10
DDR3_RESET
IO_L4P_T0_33
Y11

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Part 4:SODIMM memory module interface
The AX7325B development board has a 204PIN SODIMM memory socket
that expands the board's storage and data bandwidth and supports up to 8GB
of Micron SODIMM DDR3 memory. The FPGA and SODIMM DDR3 memory
banks have a data width of 64 bits and a maximum operating speed of 400
MHz (data rate 800 Mbps). By default, the SODIMM memory module is not
included. If you need to test it, you need to prepare it yourself. The following
Figure 4-1 detailed the 2GB Micron SODIMM memory strip we tested.
Figure 4-1: SODIMM memory test sample
The SODIMM memory module interface is directly connected to the
interface of BANK16, BANK17 and BANK18 of FPGA. The hardware
connection mode of FPGA and SODIMM DDR3 is shown in Figure 4-2.

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Figure 4-2: SODIMM interface Connection Diagram
Figure 4-3: SODIMM slot on the FPGA Board

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SODIMM slot pin assignments:
Signal Name
FPGA Pin Name
FPGA Pin
DIMM_DDR3_D0
IO_L2P_T0_18
L15
DIMM_DDR3_D1
IO_L5P_T0_18
K14
DIMM_DDR3_D2
IO_L5N_T0_18
J14
DIMM_DDR3_D3
IO_L6P_T0_18
L11
DIMM_DDR3_D4
IO_L2N_T0_18
K15
DIMM_DDR3_D5
IO_L1P_T0_18
L16
DIMM_DDR3_D6
IO_L4N_T0_18
J13
DIMM_DDR3_D7
IO_L1N_T0_18
K16
DIMM_DDR3_D8
IO_L8N_T1_18
J12
DIMM_DDR3_D9
IO_L8P_T1_18
J11
DIMM_DDR3_D10
IO_L7P_T1_18
H15
DIMM_DDR3_D11
IO_L11N_T1_SRCC_18
G14
DIMM_DDR3_D12
IO_L10P_T1_18
H11
DIMM_DDR3_D13
IO_L10N_T1_18
H12
DIMM_DDR3_D14
IO_L12P_T1_MRCC_18
G13
DIMM_DDR3_D15
IO_L7N_T1_18
G15
DIMM_DDR3_D16
IO_L13P_T2_MRCC_18
D12
DIMM_DDR3_D17
IO_L17P_T2_18
A11
DIMM_DDR3_D18
IO_L13N_T2_MRCC_18
D13
DIMM_DDR3_D19
IO_L14N_T2_SRCC_18
E13
DIMM_DDR3_D20
IO_L16P_T2_18
F11
DIMM_DDR3_D21
IO_L16N_T2_18
E11
DIMM_DDR3_D22
IO_L17N_T2_18
A12
DIMM_DDR3_D23
IO_L14P_T2_SRCC_18
F12
DIMM_DDR3_D24
IO_L22P_T3_18
B13
DIMM_DDR3_D25
IO_L22N_T3_18
A13
DIMM_DDR3_D26
IO_L23N_T3_18
B15
DIMM_DDR3_D27
IO_L23P_T3_18
C15
DIMM_DDR3_D28
IO_L24P_T3_18
B14
DIMM_DDR3_D29
IO_L24N_T3_18
A15
DIMM_DDR3_D30
IO_L20N_T3_18
E15
DIMM_DDR3_D31
IO_L19P_T3_18
F15

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DIMM_DDR3_D32
IO_L1N_T0_16
A23
DIMM_DDR3_D33
IO_L4N_T0_16
D24
DIMM_DDR3_D34
IO_L4P_T0_16
E24
DIMM_DDR3_D35
IO_L5N_T0_16
E26
DIMM_DDR3_D36
IO_L2P_T0_16
E23
DIMM_DDR3_D37
IO_L1P_T0_16
B23
DIMM_DDR3_D38
IO_L2N_T0_16
D23
DIMM_DDR3_D39
IO_L6P_T0_16
G23
DIMM_DDR3_D40
IO_L8N_T1_16
B24
DIMM_DDR3_D41
IO_L8P_T1_16
C24
DIMM_DDR3_D42
IO_L11N_T1_SRCC_16
C26
DIMM_DDR3_D43
IO_L7N_T1_16
A27
DIMM_DDR3_D44
IO_L10P_T1_16
A25
DIMM_DDR3_D45
IO_L10N_T1_16
A26
DIMM_DDR3_D46
IO_L7P_T1_16
B27
DIMM_DDR3_D47
IO_L11P_T1_SRCC_16
D26
DIMM_DDR3_D48
IO_L13P_T2_MRCC_16
D27
DIMM_DDR3_D49
IO_L17N_T2_16
A30
DIMM_DDR3_D50
IO_L16N_T2_16
C30
DIMM_DDR3_D51
IO_L16P_T2_16
D29
DIMM_DDR3_D52
IO_L13N_T2_MRCC_16
C27
DIMM_DDR3_D53
IO_L17P_T2_16
B30
DIMM_DDR3_D54
IO_L18P_T2_16
E29
DIMM_DDR3_D55
IO_L14P_T2_SRCC_16
E28
DIMM_DDR3_D56
IO_L20N_T3_16
F28
DIMM_DDR3_D57
IO_L22N_T3_16
F30
DIMM_DDR3_D58
IO_L24P_T3_16
H30
DIMM_DDR3_D59
IO_L20P_T3_16
G28
DIMM_DDR3_D60
IO_L19P_T3_16
H24
DIMM_DDR3_D61
IO_L22P_T3_16
G29
DIMM_DDR3_D62
IO_L23N_T3_16
H27
DIMM_DDR3_D63
IO_L23P_T3_16
H26
DIMM_DDR3_DM0
IO_L4P_T0_18
K13
DIMM_DDR3_DM1
IO_L11P_T1_SRCC_18
H14

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DIMM_DDR3_DM2
IO_L18P_T2_18
D11
DIMM_DDR3_DM3
IO_L20P_T3_18
E14
DIMM_DDR3_DM4
IO_L5P_T0_16
F26
DIMM_DDR3_DM5
IO_L12P_T1_MRCC_16
C25
DIMM_DDR3_DM6
IO_L14N_T2_SRCC_16
D28
DIMM_DDR3_DM7
IO_L24N_T3_16
G30
DIMM_DDR3_DQS0_P
IO_L3P_T0_DQS_18
L12
DIMM_DDR3_DQS0_N
IO_L3N_T0_DQS_18
L13
DIMM_DDR3_DQS1_P
IO_L9P_T1_DQS_18
J16
DIMM_DDR3_DQS1_N
IO_L9N_T1_DQS_18
H16
DIMM_DDR3_DQS2_P
IO_L15P_T2_DQS_18
C12
DIMM_DDR3_DQS2_N
IO_L15N_T2_DQS_18
B12
DIMM_DDR3_DQS3_P
IO_L21P_T3_DQS_18
D14
DIMM_DDR3_DQS3_N
IO_L21N_T3_DQS_18
C14
DIMM_DDR3_DQS4_P
IO_L3P_T0_DQS_16
F25
DIMM_DDR3_DQS4_N
IO_L3N_T0_DQS_16
E25
DIMM_DDR3_DQS5_P
IO_L9P_T1_DQS_16
B28
DIMM_DDR3_DQS5_N
IO_L9N_T1_DQS_16
A28
DIMM_DDR3_DQS6_P
IO_L15P_T2_DQS_16
C29
DIMM_DDR3_DQS6_N
IO_L15N_T2_DQS_16
B29
DIMM_DDR3_DQS7_P
IO_L21P_T3_DQS_16
G27
DIMM_DDR3_DQS7_N
IO_L21N_T3_DQS_16
F27
DIMM_DDR3_A0
IO_L11P_T1_SRCC_17
F21
DIMM_DDR3_A1
IO_L8P_T1_17
D21
DIMM_DDR3_A2
IO_L11N_T1_SRCC_17
E21
DIMM_DDR3_A3
IO_L16N_T2_17
F18
DIMM_DDR3_A4
IO_L3N_T0_DQS_17
H17
DIMM_DDR3_A5
IO_L17N_T2_17
B17
DIMM_DDR3_A6
IO_L4P_T0_17
J19
DIMM_DDR3_A7
IO_L17P_T2_17
C17
DIMM_DDR3_A8
IO_L1N_T0_17
J18
DIMM_DDR3_A9
IO_L15N_T2_DQS_17
C16
DIMM_DDR3_A10
IO_L6P_T0_17
K19
DIMM_DDR3_A11
IO_L16P_T2_17
G18