Vaisala MPU112 Use and care manual

TECHNICAL REFERENCE
Main Processor Unit
MPU112
M210829EN-A

PUBLISHED BY
Vaisala Oyj Phone (int.): [phone]
P.O. Box 26 Fax: [phone]
FIN-00421 Helsinki
Finland
Visit our Internet pages at http://www.vaisala.com/
© Vaisala 2007
No part of this manual may be reproduced in any form or by any means, electronic or
mechanical (including photocopying), nor may its contents be communicated to a third
party without prior written permission of the copyright holder.
The contents are subject to change without prior notice.
Please observe that this manual does not create any legally binding obligations for
Vaisala towards the customer or end user. All legally binding commitments and
agreements are included exclusively in the applicable supply contract or Conditions of
Sale.

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VAISALA ________________________________________________________________________ 1
Table of Contents
CHAPTER 1
GENERAL INFORMATION............................................................................ 3
About This Manual ................................................................... 3
Contents of This Manual ....................................................... 3
Feedback............................................................................... 4
Safety......................................................................................... 4
General Safety Considerations ............................................. 4
ESD Protection...................................................................... 5
Recycling .................................................................................. 5
CHAPTER 2
PRODUCT OVERVIEW.................................................................................. 7
Introduction to MPU112 Main Processor Unit....................... 7
CHAPTER 3
FUNCTIONAL DESCRIPTION....................................................................... 9
PC Core module ....................................................................... 9
Flash Disk ............................................................................... 10
CHAPTER 4
SYSTEM LOGIC PLD................................................................................... 11
Programmable Logic Device (PLD) ...................................... 11
ISA Bus Interface ................................................................ 12
Address Decoders............................................................... 12
Serial Channels 3 and 4...................................................... 13
Interrupt Line Selectors ....................................................... 13
ARCNET Filter .................................................................... 13
Data Output Registers......................................................... 13
Device Registers and Slot/Rack Codes .............................. 13
CHAPTER 5
EXTERNAL COMMUNICATION INTERFACES.......................................... 15
Ethernet Controller................................................................. 15
Ethernet Switch ...................................................................... 16
ARCNET Line Interface.......................................................... 17
Serial Channels ...................................................................... 18
CHAPTER 6
SUPPORT LOGIC ........................................................................................ 19
Reset Circuit ........................................................................... 19

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PLL Clock Multipliers .............................................................19
Voltage Regulators.................................................................20
Test Input.................................................................................20
LED Lamp................................................................................20
CHAPTER 7
TEST PROGRAM .........................................................................................21
Test Program Overview .........................................................21
CHAPTER 8
TECHNICAL DATA ......................................................................................23
Control Processor ..................................................................23
General ....................................................................................24
Connector Signal Layout .......................................................25
CHAPTER 9
DIAGRAMS AND BOARD LAYOUTS .........................................................27
Main Processor MPU112........................................................27
CHAPTER 10
PARTS LIST .................................................................................................37
APPENDIX A
CONNECTOR SIGNAL LIST........................................................................41
APPENDIX B
FRONT PANEL CONNECTORS..................................................................45
COM1 Connector ....................................................................45
ETH1 and ETH2 Connectors..................................................45
APPENDIX C
LIST OF SIGNALS .......................................................................................47

Chapter 1 ________________________________________________________ General Information
VAISALA ________________________________________________________________________ 3
CHAPTER 1
GENERAL INFORMATION
This chapter provides general notes for the product.
About This Manual
This manual provides information for the Vaisala Main Processor Unit
MPU112.
Contents of This Manual
This manual consists of the following chapters:
- Chapter 1, General Information, provides general notes for the
product.
- Chapter 2, Product Overview, explains the operation and basic
structure of the Vaisala Main Processor Unit MPU112.
- Chapter 3, Functional Description, describes the functionality of
the product.
- Chapter 4, System Logic PLD, provides information about the
Programmable Logic Devices of the MPU112.
- Chapter 5, External Communication Interfaces provides
information about the Ethernet and ARCNET local area network
interfaces and about asynchronous serial channels.
- Chapter 6, Support Logic describes the support logic blocks and
voltage regulators.
- Chapter 7, Test Program describes the test program operation.
- Chapter 8, Technical Data contains the MPU112 technical
specifications.

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- Chapter 9, Diagrams and Board Layouts, contains the technical
drawings.
- Chapter 10, Parts List lists the MPU112 parts.
- Appendix A, Connector Signal List contains the system connector
signal list.
- Appendix B, Front Panel Connectors describes the MPU112
connectors.
- Appendix C, List of Signals lists the signals used in the MPU112.
Feedback
Vaisala Customer Documentation Team welcomes your comments
and suggestions on the quality and usefulness of this publication. If
you find errors or have other suggestions for improvement, please
indicate the chapter, section, and page number. You can send
comments to us by e-mail: [email protected]
Safety
General Safety Considerations
Throughout the manual, important safety considerations are
highlighted as follows:
WARNING Warning alerts you to a serious hazard. If you do not read and follow
instructions very carefully at this point, there is a risk of injury or
even death.
CAUTION Caution warns you of a potential hazard. If you do not read and
follow instructions carefully at this point, the product could be
damaged or important data could be lost.
NOTE Note highlights important information on using the product.

Chapter 1 ________________________________________________________ General Information
VAISALA ________________________________________________________________________ 5
ESD Protection
Electrostatic Discharge (ESD) can cause immediate or latent damage
to electronic circuits. Vaisala products are adequately protected
against ESD for their intended use. However, it is possible to damage
the product by delivering electrostatic discharges when touching,
removing, or inserting any objects inside the equipment housing.
To make sure you are not delivering high static voltages yourself:
- Handle ESD sensitive components on a properly grounded and
protected ESD workbench. When this is not possible, ground
yourself to the equipment chassis before touching the boards.
Ground yourself with a wrist strap and a resistive connection cord.
When neither of the above is possible, touch a conductive part of
the equipment chassis with your other hand before touching the
boards.
- Always hold the boards by the edges and avoid touching the
component contacts.
Recycling
Recycle all applicable material.
Dispose of batteries and the unit according to statutory regulations.
Do not dispose of with regular household refuse.

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Chapter 2 __________________________________________________________ Product Overview
VAISALA ________________________________________________________________________ 7
CHAPTER 2
PRODUCT OVERVIEW
This chapter explains the operation and basic structure of the Vaisala
Main Processor Unit MPU112.
Introduction to MPU112 Main Processor Unit
The MPU112 is an E1-sized module that controls the system functions
and external communication. It comprises an E1-sized main circuit
board and a Computer Module which is installed on the Carrier Board.
The Computer Module is a PC-compatible core module. It contains a
PC-compatible CPU and basic PC interfaces, from which the COM1
and COM2 communication ports are used in MPU112.
The Carrier Board contains an Ethernet communication interface, a
Compact Flash type disk memory, a Programmable Logic Device
(PLD), two serial communication channels (in addition to COM1 and
COM2), ARCNET type local area network, and a battery for the
calendar clock of the CPU.
The Ethernet communication interface consists of an Ethernet
controller and a five channel Ethernet switch. The four switch
channels are available for external connections at 10 or 100 Mbit/s
line speed.
The Compact Flash disk memory is a 1 GB ATA/IDE compatible
device.
All timing and interface logic functions are implemented in
Programmable Logic Device (PLD). The configuration (program)
code of the PLD is stored in the program memory of the CPU, and the
configuration takes place during system start-up.

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Serial communication channels COM1-4 are used for external
communication. The COM1-2 channels are from Computer module
and COM3-4 channels are from PLD logic.
ARCNET type local area network is used for the connection to other
sounding system units.

Chapter 3 ______________________________________________________ Functional Description
VAISALA ________________________________________________________________________ 9
CHAPTER 3
FUNCTIONAL DESCRIPTION
This chapter describes the functionality of the product.
PC Core module
The PC Core Module is a complete PC compatible computer module.
It contains the following main parts:
- CPU
- SDRAM controller and memory
- PCI bus interface
- ISA bus interface
- IDE bus interface
- Serial channels COM1 and COM2
CPU is a Pentium III processor.
The SDRAM memory is a 512 MB DDR SODIMM.
The PCI bus is used to connect to the10/100 Mbps Ethernet controller.
The ISA bus is used for a flash type BIOS memory and system logic
PLD connections.
The IDE bus connects to an onboard ATA flash disk memory.
The serial channel COM1 is used for diagnostics and the channel
COM2 is used as a system interface.

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After reset, the processor starts the operation by executing the BIOS
code in its internal flash memory. First, the BIOS code verifies the
correct operation of the main system components. Then it transfers the
further code execution to the SDRAM system memory.
After BIOS is complete, the processor boots from ATA flash disk
memory, loads code to PLD (Programmable Logic Device), and starts
the execution of the actual application program.
Flash Disk
The ATA/IDE compatible flash disk is a Compact Flash (CF) type
memory card. It has a built-in intelligent ATA/IDE controller and
built-in embedded flash file system. It has a capacity of 1 Gbytes.

Chapter 4 _________________________________________________________ System Logic PLD
VAISALA _______________________________________________________________________ 11
CHAPTER 4
SYSTEM LOGIC PLD
This chapter provides information about the Programmable Logic
Devices of the MPU112.
Programmable Logic Device (PLD)
The MPU112 contains two Programmable Logic Devices (PLDs) D14
and D17. Both devices are in-circuit configurable. The main device is
D14 which is used to implement all required custom logic functions.
The D17 is used only to control the code loading of the D14. In
addition, the configuration memory D16 contains the power-up code
for D14.
At power-up, the initial D14 code is automatically loaded from the
code memory D16. Later in the system power-up, the final code is
loaded from the system disk memory by the CPU processor.
The codes for D16 and D17 are loaded during unit manufacturing
phase via the JTAG chain connection with the signals JTCK, JTMS,
JTDI, CMDO and JTDO. The signal CMDO is the data output from
D16 and it is connected via D17 to the JTAG output signal JTDO.
At power-up the operation starts with the loading of initial code as
follows:
- The pull-down resistors R66, R71 program the D14 to operate with
a serial configuration device.
- The configuring starts when the D16 OE input is released to high
level.
- The code is programmed serially from the D16 DATA output to
D14 D0CONF input by a D16 DCLK clock signal.

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- The D14 output CONFD goes to high level to indicate properly
completed configuration cycle.
- The D14 enters user mode and starts to operate according to the
loaded code.
The initial code allows the operating system of the Computer Module
to recognize the logic devices in the PLD. The code loading continues
when the boot sequence of the Computer Module is completed.
Then the final code is loaded as follows:
- The select signals PLDMSEL0, PLDMSEL1 of the programming
mode are set to high level to select the passive parallel
configuration mode.
- The signal PLDCONFIG# is pulsed low to start the configuration.
- The PLD code is loaded in byte serial format using control signals
PLDCS#, IOWR#, IORD# and data bus PLDD0CONF (data bit 0),
SD01, ..., SD07 (data bit 7).
- The D14 output CONFD goes to high level to indicate properly
completed configuration cycle.
The signal PLDD0CONF is used for data bit 0 only during
configuration. Later in the operation, the signal SD00 is used as data
0.
The resistors R64, R65, R79 and R73, R90, R94 are used to allow
overriding of D16 outputs.
The PLD D14 is used to implement the main timing, control, and
interface logic functions in the MPU112.
The PLD D14 includes the following main functions:
ISA Bus Interface
ISA bus control, data, and address signals are connected from the
CPU ISA bus to the PLD for ARCNET, additional serial channels,
and general purpose I/O functions.
Address Decoders
Address lines SA00 ... SA11 together with I/O control signals IOWR#
and IORD# are used to select the desired control functions in the PLD.

Chapter 4 _________________________________________________________ System Logic PLD
VAISALA _______________________________________________________________________ 13
Serial Channels 3 and 4
Additional serial asynchronous data receiver and transmitter with a
programmable baud rate generator are provided for the channel 3 and
channel 4.
Interrupt Line Selectors
The interrupt line selector logic provides programmable connections
from device interrupts to CPU interrupt request lines.
ARCNET Filter
A digital data filter for the incoming serial ARCNET data signal is
provided. See chapter ARCNET Interface for additional information.
Data Output Registers
Control signals for the LED lamp and general purpose I/O lines are
provided.
Device Registers and Slot/Rack
Codes
The PLD D14 contains a register for the device code (fixed to 13 hex)
of the MPU112. The slot code and rack code of the MPU112 are read
from the D14 inputs. The slot and rack codes depend on the external
connections and are used to define the ARCNET node address of the
MPU112.

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Chapter 5 ____________________________________________ External Communication Interfaces
VAISALA _______________________________________________________________________ 15
CHAPTER 5
EXTERNAL COMMUNICATION
INTERFACES
This chapter provides information about the Ethernet and ARCNET
local area network interfaces and about asynchronous serial channels.
Ethernet Controller
The AM79C973 (D21) is a single-chip PCI-to-Wire Fast Ethernet
controller. It contains the following main functional blocks or
features:
- 32-bit glueless PCI host interface
- Fully Integrated 10/100 Mbps Physical Layer Interface (PHY)
- Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access
Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue
Book Ethernet standards
- Large independent internal TX and RX FIFOs
- EEPROM interface supports jumperless design and provides
through-chip programming
- Extensive programmable internal/external loopback capabilities
In the circuit diagram the controller is divided into three parts: D21-A
for PCI bus connection; D21-B for Ethernet line connections; and
D21-C for power connections.
The controller is directly connected to the PCI bus of the Computer
Module. The 25 MHz clock is connected from the 25 MHz clock
oscillator Z2.

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The receive (E5ATD+/-) and transmit (E5ARD+/-) pairs of the
Ethernet line are connected directly to the port 5 of the Ethernet
switch.
The EEPROM D11 is for programmable initialization parameters,
which are automatically loaded to the controller registers at system
reset or power up.
The power connections include extensive filtering of the analog
supply voltages.
Ethernet Switch
The KS8995 (D5) is a five port integrated Ethernet switch. It contains
five 10/100 physical layer transceivers, five MAC (Media Access
Control) units with an integrated layer 2 switch.
In the circuit diagram, the D5 is divided into three parts: D5-A is for
common control and port five connections; D5-B is for port 1 to 4
connections; and part D5-C is for power connections.
Ports 1 and 2 are for external connections that are connected through
transformers T1 and T2 to the front panel connectors ETH1 and
ETH2. Ports 3 and 4 are connected via transformers to the system
connector for internal use. Port 5 is connected to the Ethernet
controller.
The operation of each port is identical and includes the following
main functions:
- The 100BaseTX transmit function performs parallel to serial
conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion,
three level (MLT3) encoding and transmission.
- The 100BaseTX receiver function performs adaptive equalization,
DC restoration, MLT3 to NRZI conversion, data and clock
recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B
decoding and serial to parallel conversion.
- In the 10BaseT transmit operation, the output of the 10BaseT
driver is incorporated into the 100BaseT driver to allow
transmission with the same magnetics. The outputs are internally
wave-shaped and have a typical 2.3 V amplitude.

Chapter 5 ____________________________________________ External Communication Interfaces
VAISALA _______________________________________________________________________ 17
- In the 10BaseT Receive operation, the input buffer and level
detecting squelch circuits are employed. A differential input
receiver circuit and a PLL perform the decoding function. The
Manchester-encoded data stream is separated into clock signal and
NRZ data, the PLL locks onto the incoming signal and the KS8995
decodes a data frame.
The PLL clock synthesizer in the KS8995 generates 125, 50, 25 and
10 MHz clocks for internal system timing. Internal clocks are
generated from an external 25 MHz clock input.
The power connections include extensive filtering for the analog
supply voltages.
ARCNET Line Interface
ARCNET Controller D1 contains an internal microsequencer that
performs all of the control operations necessary to carry out the
ARCNET token passing protocol and network configuration.
The processor transmits data by loading the data packed along with its
destination node number into the RAM buffer of the Controller and by
issuing a command to enable the transmitter. First, the Controller
waits for a token, then it sends an enquiry to the destination node. If
the node is free to receive, it responds with an acknowledgment and
the Controller performs the transmit sequence. If the transmit
sequence is completed successfully, the receiving node sends another
acknowledgment to the transmitter and alerts its control processor by
interrupt signal. The processor then reads the received data from the
RAM buffer of the Controller.
Timing signal 20 MHz to D1 comes from oscillator Z2 through PLL
clock multiplier D8. The controller chip D1 is selected with the PCS#
line and its registers are selected for processor access with address
lines PA0, PA1 and PA2. The internal 2-kbyte buffer memory is
accessed indirectly through these registers. PLD D14 PRD# and
PWR# controls determine the data direction on the bus. Interrupt
signal PINT# is connected to the PLD D14.
The controller is connected to the network through the bi-directional
differential Line Transceiver D2. The line is protected against voltage
transients by bi-directional transient suppressors.

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In the receive mode, the driver section of the transceiver is disabled by
the 1-state of the controller TXEN output, which is inverted via D14
PLD and connected to the transceiver pin 3. The receiver section of
the transceiver is permanently enabled and the received data
ARCRXINP is connected through D14 to the controller RXIN input.
The D14 contains a data filter, which is used to filter out short
transient states from the incoming serial data. The filter length is
approximately 320 ns.
During the transmit sequence, the controller enables the transmitter by
driving pin 3 high and the inverted transmit data from output pin P1 is
driven to the line by the transmitter. The enable and data signals
(ARCTXEN# and ARCTX) are connected to the transmitter via PLD
D14.
Serial Channels
The MPU112 has four serial channels for external serial
communication. All channels have RS232 compatible line drivers and
receivers.
- Channels 1 and 2 are provided by the Computer Module. Both
channels are supported by the internal baud rate generators.
- Channel 1 is used for testing and is connected to the front panel
connector and system connector.
- Channel 2 is the main system channel and is connected to the
system connector pins a30 (TXD2) and a31 (RXD2) with
handshake signals (DTR2, RTS2, DSR2 and CTS2). This channel
is normally used for main external RS232 compatible connection.
- Channels 3 and 4 are provided by the PLD D14. The channels have
programmable baud rate generators. Only two 8 bit modes of data
widths are supported: 8 bit data with no parity or 7 bit data with
even/odd parity. Receivers have 8 byte FIFOs, but the fifo control
mode is not used.