Intel BX80613I7980 User manual

Document # 323252-003
Intel®Core™ i7-900 Desktop
Processor Extreme Edition Series
and Intel®Core™ i7-900 Desktop
Processor Series on 32-nm Process
Datasheet, Volume 1
June 2011

2Datasheet, Volume 1
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel®Core™ i7-900 desktop processor Extreme Edition series on 32-nm process may contain design defects or errors known
as errata which may cause the product to deviate from published specifications.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-
enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For
more information including details on which processors support HT Technology, see
http://www.intel.com/products/ht/hyperthreading_more.htm
Intel®64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled
for Intel®64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See www.intel.com/info/em64t for more information including details on
which processors support Intel®64 or consult with your system vendor for more information.
± Intel®Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and
for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on
hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel® SpeedStep Technology. See the Processor Spec Finder or contact your Intel representative for more information.
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Intel SpeedStep, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010–2011 Intel Corporation.

Datasheet, Volume 1 3
Contents
1Introduction..............................................................................................................9
1.1 Terminology .....................................................................................................10
1.2 References .......................................................................................................11
2 Electrical Specifications........................................................................................... 13
2.1 Intel®QuickPath Interconnect (Intel®QPI) Differential Signaling.............................13
2.2 Power and Ground Lands....................................................................................13
2.3 Decoupling Guidelines........................................................................................13
2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling.............................................................14
2.4 Processor Clocking (BCLK_DP, BCLK_DN) ............................................................. 14
2.4.1 PLL Power Supply...................................................................................14
2.5 Voltage Identification (VID) ................................................................................ 15
2.6 Reserved or Unused Signals................................................................................18
2.7 Signal Groups...................................................................................................19
2.8 Test Access Port (TAP) Connection.......................................................................20
2.9 Platform Environmental Control Interface (PECI) DC Specifications...........................21
2.9.1 DC Characteristics..................................................................................21
2.9.2 Input Device Hysteresis .......................................................................... 22
2.10 Absolute Maximum and Minimum Ratings.............................................................22
2.11 Processor DC Specifications ................................................................................23
2.11.1 DC Voltage and Current Specification........................................................24
2.11.2 VCC Overshoot Specification.....................................................................31
2.11.3 Die Voltage Validation............................................................................. 31
2.12 Intel®QuickPath Interconnect (Intel®QPI) Specifications.......................................32
3 Package Mechanical Specifications .......................................................................... 35
3.1 Package Mechanical Drawing...............................................................................35
3.2 Processor Component Keep-Out Zones.................................................................38
3.3 Package Loading Specifications ........................................................................... 38
3.4 Package Handling Guidelines...............................................................................38
3.5 Package Insertion Specifications..........................................................................38
3.6 Processor Mass Specification...............................................................................39
3.7 Processor Materials............................................................................................39
3.8 Processor Markings............................................................................................39
3.9 Processor Land Coordinates................................................................................40
4LandListing.............................................................................................................41
5 Signal Descriptions..................................................................................................71
6 Thermal Specifications ............................................................................................ 75
6.1 Package Thermal Specifications...........................................................................75
6.1.1 Thermal Specifications ............................................................................ 75
6.1.1.1 Specification for Operation Where Digital Thermal Sensor
Exceeds TCONTROL .....................................................................79
6.1.2 Thermal Metrology .................................................................................80
6.2 Processor Thermal Features................................................................................ 81
6.2.1 Processor Temperature ........................................................................... 81
6.2.2 Adaptive Thermal Monitor........................................................................81
6.2.2.1 Frequency/VID Control ..............................................................82
6.2.2.2 Clock Modulation ......................................................................83
6.2.2.3 Immediate Transiton to combined TM1 and TM2 ...........................83
6.2.2.4 Critical Temperature Flag...........................................................83
6.2.2.5 PROCHOT# Signal.....................................................................83
6.2.3 THERMTRIP# Signal ...............................................................................84

4Datasheet, Volume 1
6.3 Platform Environment Control Interface (PECI) ......................................................84
6.3.1 Introduction...........................................................................................84
6.3.1.1 Fan Speed Control with Digital Thermal Sensor .............................85
6.3.1.2 Processor Thermal Data Sample Rate and Filtering.........................85
6.3.2 PECI Specifications .................................................................................86
6.3.2.1 PECI Device Address..................................................................86
6.3.2.2 PECI Command Support.............................................................86
6.3.2.3 PECI Fault Handling Requirements...............................................86
6.3.2.4 PECI GetTemp0() Error Code Support ..........................................86
6.4 Storage Conditions Specifications.........................................................................87
7Features..................................................................................................................89
7.1 Power-On Configuration (POC).............................................................................89
7.2 Clock Control and Low Power States.....................................................................89
7.2.1 Thread and Core Power State Descriptions .................................................90
7.2.1.1 C0 State ..................................................................................90
7.2.1.2 C1/C1E State............................................................................90
7.2.1.3 C3 State ..................................................................................91
7.2.1.4 C6 State ..................................................................................91
7.2.2 Package Power State Descriptions.............................................................91
7.2.2.1 Package C0 State......................................................................91
7.2.2.2 Package C1/C1E State ...............................................................91
7.2.2.3 Package C3 State......................................................................91
7.2.2.4 Package C6 State......................................................................92
7.3 Sleep States .....................................................................................................92
7.4 ACPI P-States (Intel®Turbo Boost Technology) .....................................................92
7.5 Enhanced Intel SpeedStep®Technology ...............................................................93
8 Boxed Processor Specifications................................................................................95
8.1 Introduction......................................................................................................95
8.2 Mechanical Specifications....................................................................................96
8.2.1 Boxed Processor Cooling Solution Dimensions.............................................96
8.2.2 Boxed Processor Fan Heatsink Weight .......................................................98
8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....98
8.3 Electrical Requirements ......................................................................................98
8.3.1 Fan Heatsink Power Supply ......................................................................98
8.4 Thermal Specifications........................................................................................99
8.4.1 Boxed Processor Cooling Requirements......................................................99
8.4.2 Variable Speed Fan...............................................................................101

Datasheet, Volume 1 5
Figures
1-1 High-Level View of Processor Interfaces .................................................................9
2-1 Active ODT for a Differential Link Example............................................................13
2-2 Input Device Hysteresis .....................................................................................22
2-3 VCC Static and Transient Tolerance Load Lines.......................................................26
2-4 VTT Static and Transient Tolerance Load Line ........................................................28
2-5 VCC Overshoot Example Waveform ......................................................................31
3-1 Processor Package Assembly Sketch ....................................................................35
3-2 Processor Package Drawing (Sheet 1 of 2)............................................................36
3-3 Processor Package Drawing (Sheet 2 of 2)............................................................37
3-4 Processor Top-side Markings............................................................................... 39
3-5 Processor Land Coordinates and Quadrants, Top View ............................................40
6-1 Intel®Core™ i7-900 Desktop Processor Extreme Edition Series Thermal Profile......... 77
6-2 Intel®Core™ i7-900 Desktop Processor Series Thermal Profile................................78
6-3 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location........... 80
6-4 Frequency and Voltage Ordering..........................................................................82
7-1 Power State......................................................................................................90
8-1 Mechanical Representation of the Boxed Processor.................................................95
8-2 Space Requirements for the Boxed Processor (side view)........................................96
8-3 Space Requirements for the Boxed Processor (top view).........................................97
8-4 Space Requirements for the Boxed Processor (overall view)....................................97
8-5 Boxed Processor Fan Heatsink Power Cable Connector Description ...........................98
8-6 Baseboard Power Header Placement Relative to Processor Socket ............................99
8-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) .............. 100
8-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) ............. 100
8-9 Boxed Processor Fan Heatsink Set Points............................................................ 101

6Datasheet, Volume 1
Tables
1-1 References........................................................................................................11
2-1 Voltage Identification Definition ...........................................................................16
2-2 Market Segment Selection Truth Table for MS_ID[2:0] ...........................................18
2-3 Signal Groups ...................................................................................................19
2-4 Signals with ODT ...............................................................................................20
2-5 PECI DC Electrical Limits.....................................................................................21
2-6 Processor Absolute Minimum and Maximum Ratings ...............................................23
2-7 Voltage and Current Specifications.......................................................................24
2-8 VCC Static and Transient Tolerance.......................................................................25
2-9 VTT Voltage Identification (VID) Definition.............................................................26
2-10 VTT Static and Transient Tolerance ......................................................................27
2-11 DDR3 Signal Group DC Specifications ...................................................................28
2-12 RESET# Signal DC Specifications .........................................................................29
2-13 TAP Signal Group DC Specifications......................................................................29
2-14 PWRGOOD Signal Group DC Specifications ............................................................30
2-15 Control Sideband Signal Group DC Specifications ...................................................30
2-16 VCC Overshoot Specifications..............................................................................31
2-17 Intel®QuickPath Interconnect (Intel QPI) Specifications .........................................32
2-18 Parameter Values for Intel®QuickPath Interconnect (Intel QPI) Channel at 6.4 GT/s ..33
3-1 Processor Loading Specifications..........................................................................38
3-2 Package Handling Guidelines...............................................................................38
3-3 Processor Materials............................................................................................39
4-1 Land Listing by Land Name .................................................................................41
4-2 Land Listing by Land Number ..............................................................................56
5-1 Signal Definitions...............................................................................................71
6-1 Processor Thermal Specifications ........................................................................76
6-2 Intel®Core™ i7-900 Desktop Processor Extreme Edition Series Thermal Profile .........77
6-3 Intel®Core™ i7-900 Desktop Processor Series Thermal Profile ................................78
6-4 Thermal Solution Performance above TCONTROL ......................................................79
6-5 Supported PECI Command Functions and Codes ....................................................86
6-6 GetTemp0() Error Codes.....................................................................................86
6-7 Storage Condition Ratings...................................................................................87
7-1 Power On Configuration Signal Options.................................................................89
7-2 Coordination of Thread Power States at the Core Level ...........................................90
7-3 Processor S-States.............................................................................................92
8-1 Fan Heatsink Power and Signal Specifications ........................................................99
8-2 Fan Heatsink Power and Signal Specifications ......................................................101

Datasheet, Volume 1 7
Revision History
§
Revision
Number Description Date
001 • Initial release March 2010
002 • Added Intel®Core™ i7-970 desktop processor series July 2010
003 • Added Intel®Core™ i7-990X desktop processor Extreme Edition
• Added Intel®Core™ i7-980 desktop processor June 2011

8Datasheet, Volume 1

Datasheet, Volume 1 9
Introduction
1Introduction
The Intel®Core™ i7-900 desktop processor Extreme Edition series and Intel®Core™
i7-900 desktop processor series on 32-nm process processor is intended for high
performance, high-end desktop systems. Several architectural and microarchitectural
enhancements have been added to this processor including six processor cores in the
processor package and increased shared cache.
The Intel®Core™ i7-900 desktop processor Extreme Edition series and and Intel®
Core™ i7-970 desktop processor series on 32-nm process is a desktop multi-core
processor with these key technologies:
• Integrated memory controller
• Point-to-point link interface based on Intel QuickPath Interconnect (Intel QPI)
Figure 1-1 shows the interfaces used with these new technologies.
Note: In this document the Intel®Core™ i7-900 desktop processor Extreme Edition series on
32-nm process will be referred to as “the processor.”
Note: The Intel®Core™ i7-900 desktop processor Extreme Edition series on 32-nm process
refers to the Intel®Core™ i7-980X and i7-990X desktop processor Extreme Edition.
Note: The Intel®Core™ i7-900 desktop processor series on 32-nm process refers to the
Intel®Core™ i7-980 and i7-970 desktop processors.
The processor is optimized for performance with the power efficiency of a low-power
microarchitecture.
This document provides DC electrical specifications, differential signaling specifications,
pinout and signal definitions, package mechanical specifications and thermal
requirements, and additional features pertinent to the implementation and operation of
the processor.
The processor is a multi-core processor built on the 32-nm process technology, that
uses up to 130 W thermal design power (TDP). The processor features an Intel QPI
point-to-point link capable of up to 6.4 GT/s, 12 MB Level 3 cache, and an integrated
memory controller.
Figure 1-1. High-Level View of Processor Interfaces
Processor
Intel®QuickPath
Interconnect (Intel®QPI)
CH 0
CH 1
CH 2
System
Memory
(DDR3)

Introduction
10 Datasheet, Volume 1
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The
processor supports several Advanced Technologies: Intel®64 Technology (Intel®64),
Enhanced Intel SpeedStep®Technology, Intel®Virtualization Technology (Intel®VT),
Turbo Boost Technology, and Hyper-Threading Technology.
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when VTTPWRGOOD is high, the VTT power rail is
stable.
‘_N’ and ‘_P’ after a signal name refers to a differential pair.
Commonly used terms are explained here for clarification:
•Intel®Core™ i7-900 desktop processor Extreme Edition series and Intel®
Core™ i7-900 desktop processor series on 32-nm process — The entire
product, including processor substrate and integrated heat spreader (IHS).
•1366-land LGA package — The processor is available in a Flip-Chip Land Grid
Array (FC-LGA) package, consisting of the processor mounted on a land grid array
substrate with an integrated heat spreader (IHS).
•LGA1366 Socket — The processor (in the LGA 1366 package) mates with the
system board through this surface mount, 1366-contact socket.
•DDR3 — Double Data Rate 3 Synchronous Dynamic Random Access Memory
(SDRAM) is the name of the new DDR memory standard that is being developed as
the successor to DDR2 SRDRAM.
•Intel®QuickPath Interconnect (Intel® QPI)— Intel QPI is a cache-coherent,
point-to-point link-based electrical interconnect specification for Intel processors
and chipsets.
•Intel®QuickPath Technology Memory Controller — A memory controller that
is integrated into the processor die.
•Integrated Heat Spreader (IHS) — A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
•Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, signal quality, mechanical, and thermal,
are satisfied.
•Enhanced Intel SpeedStep®Technology — Enhanced Intel SpeedStep
Technology allows the operating system to reduce power consumption when
performance is not needed.
•Execute Disable Bit — Execute Disable allows memory to be marked as
executable or non-executable when combined with a supporting operating system.
If code attempts to run in non-executable memory, the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel®Architecture Software Developer's Manual
for more detailed information. Refer to http://developer.intel.com/ for future
reference on up to date nomenclatures.
•Intel®64 Architecture — An enhancement to the Intel IA-32 architecture,
allowing the processor to execute operating systems and applications written to

Datasheet, Volume 1 11
Introduction
take advantage of Intel 64. Further details on the Intel 64 architecture and
programming model can be found at
http://developer.intel.com/technology/intel64/.
•Intel®Virtualization Technology (Intel®VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel®VT provides a foundation for widely-deployed virtualization
solutions and enables a more robust hardware assisted virtualization solution. More
information can be found at: http://www.intel.com/technology/virtualization/
•Unit Interval (UI) — Signaling convention that is binary and unidirectional. In
this binary signaling, one bit is sent for every edge of the forwarded clock, whether
it is a rising edge or a falling edge. If a number of edges are collected at instances
t1, t2, tn,...., tk then the UI at instance “n” is defined as:
UI n= t n – t n – 1
•Jitter — Any timing variation of a transition edge or edges from the defined Unit
Interval.
•Storage Conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
•OEM —Original Equipment Manufacturer.
1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document.
Notes:
1. Contact your Intel representative to receive the latest revisions of these documents.
2. Document is available publicly at http://developer.intel.com.
3. Document not available at time of printing.
4. The LGA1366 Socket and Heatsink Keepout Zones – Mechanical Models will be made available
electronically.
Table 1-1. References
Document Location
Intel®Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel®Core™ i7-900 Desktop Processor Series on 32-nm Process
Specification Update http://www.intel.com/Assets/PDF/spe
cupdate/323254.pdf
Intel®Core™ i7-900 Desktop Processor Extreme Edition Series on
32-nm Process Datasheet, Volume 2 http://download.intel.com/design/pro
cessor/datashts/323253.pdf
Intel®Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel®Core™ i7-900 Desktop Processor Series and LGA1366 Socket
Thermal and Mechanical Design Guide http://download.intel.com/design/pro
cessor/designex/320837.pdf
Intel X58 Express Chipset Datasheet http://www.intel.com/Assets/PDF/dat
asheet/320838.pdf
AP-485, Intel® Processor Identification and the CPUID Instruction http://www.intel.com/design/processo
r/applnots/241618.htm
IA-32 Intel®Architecture Software Developer's Manual
•Volume 1: Basic Architecture
•Volume 2A: Instruction Set Reference, A-M
•Volume 2B: Instruction Set Reference, N-Z
•Volume 3A: System Programming Guide, Part 1
•Volume 3B: Systems Programming Guide, Part 2
http://www.intel.com/products/proces
sor/manuals/

Introduction
12 Datasheet, Volume 1
§

Datasheet, Volume 1 13
Electrical Specifications
2Electrical Specifications
2.1 Intel®QuickPath Interconnect (Intel®QPI)
Differential Signaling
The processor provides an Intel QPI port for high speed serial transfer between other
Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links
(for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of
opposite-polarity (D_P, D_N) signals are used.
On-die termination (ODT) provided on the processor silicon and termination is to VSS.
Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QPI
links on the system board.
Intel strongly recommends performing analog simulations of the Intel QPI interface.
Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and
Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the
differential signal group.
2.2 Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 210 VCC pads
and 119 VSS pads associated with VCC; 8 VTTA pads and 5 VSS pads associated with
VTTA; 28 VTTD pads and 17 VSS pads associated with VTTD, 28 VDDQ pads and 17 VSS
pads associated with VDDQ; and 3 VCCPLL pads. All VCCP, VTTA, VTTD, VDDQ, and
VCCPLL lands must be connected to their respective processor power planes, while all
VSS lands must be connected to the system ground plane. The processor VCC lands
must be supplied with the voltage determined by the processor Voltage IDentification
(VID) signals. Table 2-1 specifies the voltage level for the various VIDs.
2.3 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply
current during longer lasting changes in current demand; such as, coming out of an idle
condition. Similarly, capacitors act as a storage well for current when entering an idle
Figure 2-1. Active ODT for a Differential Link Example
TXRX
RTT RTT
RTT RTT
Signal
Signal

Electrical Specifications
14 Datasheet, Volume 1
condition from a running condition. Care must be taken in the baseboard design to
ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of
the processor.
2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling
Voltage regulator solutions need to provide bulk capacitance and the baseboard
designer must assure a low interconnect resistance from the regulator to the LGA1366
socket. Bulk decoupling must be provided on the baseboard to handle large current
swings. The power delivery solution must insure the voltage and current specifications
are met (as defined in Table 2-7).
2.4 Processor Clocking (BCLK_DP, BCLK_DN)
The processor core, Intel QPI, and integrated memory controller frequencies are
generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side
bus architecture, there is no direct link between core frequency and Intel QPI link
frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum
core frequency, Intel QPI link frequency and integrated memory controller frequency,
are set during manufacturing. It is possible to override the processor core frequency
setting using software. This permits operation at lower core frequencies than the
factory set maximum core frequency.
The processor’s maximum non-turbo core frequency is configured during power-on
reset by using values stored internally during manufacturing. The stored value sets the
highest core multiplier at which the particular processor can operate. If lower maximum
non-turbo speeds are desired, the appropriate ratio can be configured using the
CLOCK_FLEX_MAX MSR.
The processor uses differential clocks (BCLK_DP, BCLK_DN). Clock multiplying within
the processor is provided by the internal phase locked loop (PLL) that requires a
constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum
clocking. The processor core frequency is determined by multiplying the ratio by
133 MHz.
2.4.1 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 2-7 for DC
specifications.

Datasheet, Volume 1 15
Electrical Specifications
2.5 Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator Down (VRD) 11.1 Design Guidelines. The voltage set by the VID signals is
the reference voltage regulator output voltage to be delivered to the processor VCC
pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC
specifications for these signals. The VID codes will change due to temperature and/or
current load changes in order to minimize the power of the part. A voltage range is
provided in Table 2-7. The specifications have been set such that one voltage regulator
can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing such that two devices
at the same core frequency may have different default VID settings. This is reflected by
the VID range values provided in Table 2-1.
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of
VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low
voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines for
further details.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the
loadline. It should be noted that a low-to-high or high-to-low voltage state change will
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the maximum specified VID are not permitted. Table 2-8 includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained
as shown in Table 2-8.
The VR used must be capable of regulating its output to the value defined by the new
VID. DC specifications for dynamic VID transitions are included in Table 2-7 and
Table 2-8. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for
further details.

Electrical Specifications
16 Datasheet, Volume 1
Table 2-1. Voltage Identification Definition (Sheet 1 of 2)
VID
7VID 6VID 5VID 4VID 3VID 2VID 1VID 0VCC_MAX VID 7VID 6VID 5VID 4VID 3VID 2VID 1VID 0VCC_MAX
0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1.04375
0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1.03750
0 0 0 0 0 0 1 0 1.60000 0 1 0 1 1 1 0 1 1.03125
0 0 0 0 0 0 1 1 1.59375 0 1 0 1 1 1 1 0 1.02500
0 0 0 0 0 1 0 0 1.58750 0 1 0 1 1 1 1 1 1.01875
0 0 0 0 0 1 0 1 1.58125 0 1 1 0 0 0 0 0 1.01250
0 0 0 0 0 1 1 0 1.57500 0 1 1 0 0 0 0 1 1.00625
00000111 1.56875 0 1 1 0 0 0 1 0 1.00000
00001000 1.56250 0 1 1 0 0 0 1 1 0.99375
0 0 0 0 1 0 0 1 1.55625 0 1 1 0 0 1 0 0 0.98750
0 0 0 0 1 0 1 0 1.55000 0 1 1 0 0 1 0 1 0.98125
0 0 0 0 1 0 1 1 1.54375 0 1 1 0 0 1 1 0 0.97500
0 0 0 0 1 1 0 0 1.53750 0 1 1 0 0 1 1 1 0.96875
0 0 0 0 1 1 0 1 1.53125 0 1 1 0 1 0 0 0 0.96250
0 0 0 0 1 1 1 0 1.52500 0 1 1 0 1 0 0 1 0.95626
0 0 0 0 1 1 1 1 1.51875 0 1 1 0 1 0 1 0 0.95000
0 0 0 1 0 0 0 0 1.51250 0 1 1 0 1 0 1 1 0.94375
0 0 0 1 0 0 0 1 1.50625 0 1 1 0 1 1 0 0 0.93750
0 0 0 1 0 0 1 0 1.50000 0 1 1 0 1 1 0 1 0.93125
0 0 0 1 0 0 1 1 1.49375 0 1 1 0 1 1 1 0 0.92500
0 0 0 1 0 1 0 0 1.48750 0 1 1 0 1 1 1 1 0.91875
0 0 0 1 0 1 0 1 1.48125 0 1 1 1 0 0 0 0 0.91250
0 0 0 1 0 1 1 0 1.47500 0 1 1 1 0 0 0 1 0.90625
0 0 0 1 0 1 1 1 1.46875 0 1 1 1 0 0 1 0 0.90000
0 0 0 1 1 0 0 0 1.46250 0 1 1 1 0 0 1 1 0.89375
0 0 0 1 1 0 0 1 1.45625 0 1 1 1 0 1 0 0 0.88750
0 0 0 1 1 0 1 0 1.45000 0 1 1 1 0 1 0 1 0.88125
0 0 0 1 1 0 1 1 1.44375 0 1 1 1 0 1 1 0 0.87500
0 0 0 1 1 1 0 0 1.43750 0 1 1 1 0 1 1 1 0.86875
0 0 0 1 1 1 0 1 1.43125 0 1 1 1 1 0 0 0 0.86250
0 0 0 1 1 1 1 0 1.42500 0 1 1 1 1 0 0 1 0.85625
0 0 0 1 1 1 1 1 1.41875 0 1 1 1 1 0 1 0 0.85000
0 0 1 0 0 0 0 0 1.41250 0 1 1 1 1 0 1 1 0.84374
0 0 1 0 0 0 0 1 1.40625 0 1 1 1 1 1 0 0 0.83750
0 0 1 0 0 0 1 0 1.40000 0 1 1 1 1 1 0 1 0.83125
0 0 1 0 0 0 1 1 1.39375 0 1 1 1 1 1 1 0 0.82500
0 0 1 0 0 1 0 0 1.38750 0 1 1 1 1 1 1 1 0.81875
0 0 1 0 0 1 0 1 1.38125 1 0 0 0 0 0 0 0 0.81250
0 0 1 0 0 1 1 0 1.37500 1 0 0 0 0 0 0 1 0.80625
0 0 1 0 0 1 1 1 1.36875 1 0 0 0 0 0 1 0 0.80000
0 0 1 0 1 0 0 0 1.36250 1 0 0 0 0 0 1 1 0.79375
0 0 1 0 1 0 0 1 1.35625 1 0 0 0 0 1 0 0 0.78750
0 0 1 0 1 0 1 0 1.35000 1 0 0 0 0 1 0 1 0.78125
0 0 1 0 1 0 1 1 1.34375 1 0 0 0 0 1 1 0 0.77500
0 0 1 0 1 1 0 0 1.33750 1 0 0 0 0 1 1 1 0.76875
0 0 1 0 1 1 0 1 1.33125 1 0 0 0 1 0 0 0 0.76250
0 0 1 0 1 1 1 0 1.32500 1 0 0 0 1 0 0 1 0.75625
0 0 1 0 1 1 1 1 1.31875 1 0 0 0 1 0 1 0 0.75000

Datasheet, Volume 1 17
Electrical Specifications
0 0 1 1 0 0 0 0 1.31250 1 0 0 0 1 0 1 1 0.74375
0 0 1 1 0 0 0 1 1.30625 1 0 0 0 1 1 0 0 0.73750
0 0 1 1 0 0 1 0 1.30000 1 0 0 0 1 1 0 1 0.73125
0 0 1 1 0 0 1 1 1.29375 1 0 0 0 1 1 1 0 0.72500
0 0 1 1 0 1 0 0 1.28750 1 0 0 0 1 1 1 1 0.71875
0 0 1 1 0 1 0 1 1.28125 1 0 0 1 0 0 0 0 0.71250
0 0 1 1 0 1 1 0 1.27500 1 0 0 1 0 0 0 1 0.70625
0 0 1 1 0 1 1 1 1.26875 1 0 0 1 0 0 1 0 0.70000
0 0 1 1 1 0 0 0 1.26250 1 0 0 1 0 0 1 1 0.69375
0 0 1 1 1 0 0 1 1.25625 1 0 0 1 0 1 0 0 0.68750
0 0 1 1 1 0 1 0 1.25000 1 0 0 1 0 1 0 1 0.68125
0 0 1 1 1 0 1 1 1.24375 1 0 0 1 0 1 1 0 0.67500
0 0 1 1 1 1 0 0 1.23750 1 0 0 1 0 1 1 1 0.66875
0 0 1 1 1 1 0 1 1.23125 1 0 0 1 1 0 0 0 0.66250
0 0 1 1 1 1 1 0 1.22500 1 0 0 1 1 0 0 1 0.65625
0 0 1 1 1 1 1 1 1.21875 1 0 0 1 1 0 1 0 0.65000
0 1 0 0 0 0 0 0 1.21250 1 0 0 1 1 0 1 1 0.64375
0 1 0 0 0 0 0 1 1.20625 1 0 0 1 1 1 0 0 0.63750
0 1 0 0 0 0 1 0 1.20000 1 0 0 1 1 1 0 1 0.63125
0 1 0 0 0 0 1 1 1.19375 1 0 0 1 1 1 1 0 0.62500
0 1 0 0 0 1 0 0 1.18750 1 0 0 1 1 1 1 1 0.61875
0 1 0 0 0 1 0 1 1.18125 1 0 1 0 0 0 0 0 0.61250
0 1 0 0 0 1 1 0 1.17500 1 0 1 0 0 0 0 1 0.60625
0 1 0 0 0 1 1 1 1.16875 1 0 1 0 0 0 1 0 0.60000
0 1 0 0 1 0 0 0 1.16250 1 0 1 0 0 0 1 1 0.59375
0 1 0 0 1 0 0 1 1.15625 1 0 1 0 0 1 0 0 0.58750
0 1 0 0 1 0 1 0 1.15000 1 0 1 0 0 1 0 1 0.58125
0 1 0 0 1 0 1 1 1.14375 1 0 1 0 0 1 1 0 0.57500
0 1 0 0 1 1 0 0 1.13750 1 0 1 0 0 1 1 1 0.56875
0 1 0 0 1 1 0 1 1.13125 1 0 1 0 1 0 0 0 0.56250
0 1 0 0 1 1 1 0 1.12500 1 0 1 0 1 0 0 1 0.55625
0 1 0 0 1 1 1 1 1.11875 1 0 1 0 1 0 1 0 0.55000
0 1 0 1 0 0 0 0 1.11250 1 0 1 0 1 0 1 1 0.54375
0 1 0 1 0 0 0 1 1.10625 1 0 1 0 1 1 0 0 0.53750
0 1 0 1 0 0 1 0 1.10000 1 0 1 0 1 1 0 1 0.53125
0 1 0 1 0 0 1 1 1.09375 1 0 1 0 1 1 1 0 0.52500
0 1 0 1 0 1 0 0 1.08750 1 0 1 0 1 1 1 1 0.51875
0 1 0 1 0 1 0 1 1.08125 1 0 1 1 0 0 0 0 0.51250
0 1 0 1 0 1 1 0 1.07500 1 0 1 1 0 0 0 1 0.50625
0 1 0 1 0 1 1 1 1.06875 1 0 1 1 0 0 1 0 0.50000
0 1 0 1 1 0 0 0 1.06250 1 1 1 1 1 1 1 0 OFF
0 1 0 1 1 0 0 1 1.05625 1 1 1 1 1 1 1 1 OFF
0 1 0 1 1 0 1 0 1.05000
Table 2-1. Voltage Identification Definition (Sheet 2 of 2)
VID
7VID 6VID 5VID 4VID 3VID 2VID 1VID 0VCC_MAX VID 7VID 6VID 5VID 4VID 3VID 2VID 1VID 0VCC_MAX

Electrical Specifications
18 Datasheet, Volume 1
2.6 Reserved or Unused Signals
All Reserved (RSVD) signals must remain unconnected. Connection of these signals to
VCC, VTTA, VTTD, VDDQ, VCCPLL, VSS, or to any other signal (including each other) can
result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level, except for unused integrated memory controller inputs,
outputs, and bi-directional pins that may be left floating. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs may be left
unconnected; however, this may interfere with some Test Access Port (TAP) functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bi-directional signals to power or ground. When tying any signal to power or
ground, a resistor will also allow for system testability.
Table 2-2. Market Segment Selection Truth Table for MS_ID[2:0]
MSID2 MSID1 MSID0 Description1
Notes:
1. The MSID[2:0] signals are provided to indicate the market segment for the processor and may be used for
future processor compatibility or for keying.
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
110
Intel®Core™ i7-900 desktop processor Extreme Edition series and
Intel®Core™ i7-900 desktop processor series on 32-nm process
1 1 1 Reserved

Datasheet, Volume 1 19
Electrical Specifications
2.7 Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board. The signals that have ODT are listed in Table 2-4.
Table 2-3. Signal Groups (Sheet 1 of 2)
Signal Group Type Signals1,2
System Reference Clock
Differential Clock Input BCLK_DP, BCLK_DN
Intel QPI Signal Groups
Differential Intel QPI Input QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP,
QPI_CLKRX_DN
Differential Intel QPI Output QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP,
QPI_CLKTX_DN
DDR3 Reference Clocks
Differential DDR3 Output DDR{0/1/2}_CLK[D/P][3:0]
DDR3 Command Signals
Single ended CMOS Output DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#, DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0],
DDR{0/1/2}_BA[2:0]
Single ended Asynchronous Output DDR{0/1/2}_RESET#
DDR3 Control Signals
Single ended CMOS Output DDR{0/1/2}_CS#[5:4], DDR{0/1/2}_CS#[1:0],
DDR{0/1/2}_ODT[3:0], DDR{0/1/2}_CKE[3:0]
DDR3 Data Signals
Single ended CMOS Bi-directional DDR{0/1/2}_DQ[63:0]
Differential CMOS Bi-directional DDR{0/1/2}_DQS_[N/P][7:0]
TAP
Single ended TAP Input TCK, TDI, TMS, TRST#
Single ended GTL Output TDO
Control Sideband
Single ended Asynchronous GTL Output PRDY#
Single ended Asynchronous GTL Input PREQ#
Single ended GTL Bi-directional CAT_ERR#, BPM#[7:0]
Single Ended Asynchronous Bi-directional PECI
Single Ended Analog Input COMP0, QPI_CMP[0], DDR_COMP[2:0]
Single ended Asynchronous GTL Bi-
directional PROCHOT#
Single ended Asynchronous GTL Output THERMTRIP#
Single ended CMOS Input/Output
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
VTT_VID[4:2]

Electrical Specifications
20 Datasheet, Volume 1
Note:
1. Unless otherwise specified, signals have ODT in the package with 50 pulldown to VSS.
2. PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 pullup to VTT.
3. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 kto 20 kpulldown
to VSS.
4. TRST# has ODT in package with a 1 kto 5 kpullup to VTT.
5. All DDR signals are terminated to VDDQ/2
6. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
7. While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 k
resistor to VTT
8. While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kresistor to
VSS.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least eight BCLKs for the processor to recognize the proper signal state. See
Section 2.11 for the DC specifications. See Chapter 6 for additional timing
requirements for entering and leaving the low power states.
2.8 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
Single ended CMOS Output VTT_VID[4:2]
Single ended Analog Input ISENSE
Reset Signal
Single ended Reset Input RESET#
PWRGOOD Signals
Single ended Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD
Power/Other
Power VCC, VTTA, VTTD, VCCPLL, VDDQ
Asynchronous CMOS Output PSI#
Sense Points VCC_SENSE, VSS_SENSE
Other SKTOCC#, DBR#
Notes:
1. Refer to Chapter 5 for signal descriptions.
2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
Table 2-4. Signals with ODT
• QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P],
QPI_CLKTX_D[N/P]
• DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD
• BCLK_ITP_D[N/P]
•PECI
• BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD
Table 2-3. Signal Groups (Sheet 2 of 2)
Signal Group Type Signals1,2