System Level Solutions USB20SR User manual

System Level Solutions, Inc. (USA)
14100 Murphy Avenue
San Martin, CA 95046
(408) 852 - 0067
http://www.slscorp.com
IP Core Version: 1.3
Document Version: 1.3
Document Date: January 2013
USB 2.0 (USB20SR)
Device IP Core
User Guide

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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
IP Usage Note
The Intellectual Property (IP) core is intended solely for our clients for physical integration into their own technical products
after careful examination by experienced technical personnel for its suitability for the intended purpose.
The IP was not developed for or intended for use in any specific customer application. The firmware/software of the device
may have to be adapted to the specific intended modalities of use or even replaced by other firmware/software in order to
ensure flawless function in the respective areas of application.
Performance data may depend on the operating environment, the area of application, the configuration, and method of
control, as well as on other conditions of use; these may deviate from the technical specifications, the Design Guide speci-
fications, or other product documentation. The actual performance characteristics can be determined only by measure-
ments subsequent to integration.
The reference designs were tested in a reference environment for compliance with the legal requirements applicable to the
reference environment.
No representation is made regarding the compliance with legal, regulatory, or other requirements in other environments. No
representation can be made and no warranty can be assumed regarding the suitability of the device for a specific purpose
as defined by our customers.
SLS reserves the right to make changes to the hardware or firmware or software or to the specifications without prior notice
or to replace the IP with a successor model to improve performance or design of the IP. Of course, any changes to the
hardware or firmware or software of any IP for which we have entered into an agreement with our customers will be made
only if, and only to the extent that, such changes can reasonably be expected to be acceptable to our customers.
Copyright©2013, System Level Solutions, Inc. (SLS) All rights reserved. SLS, an Embedded systems company, the styl-
ized SLS logo, specific device designations, and all other words and logos that are identified as trademarks and/or service
marks are, unless noted otherwise, the trademarks and service marks of SLS in India and other countries. All other prod-
ucts or service names are the property of their respective holders. SLS products are protected under numerous U.S. and
foreign patents and pending applications, mask working rights, and copyrights. SLS reserves the right to make changes to
any products and services at any time without notice. SLS assumes no responsibility or liability arising out of the application
or use of any information, products, or service described herein except as expressly agreed to in writing by SLS. SLS cus-
tomers are advised to obtain the latest version of specifications before relying on any published information and before
orders for products or services.
ug_ipusb20sr_1.3

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USB 2.0 (USB20SR) Device IP Core User Guide
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About this Guide
Introduction This guide helps users to know about the basics of USB 2.0 (USB20SR), the
software based enumeration device IP Core.
Table below shows the revision history of this user guide.
How To Find
Information
•The Adobe Acrobat Find feature allows you to search the contents of a
PDF file. Use Ctrl + F to open the Find dialog box. Use Shift + Ctrl + N
to open to the Go To Page dialog box.
•Bookmarks serve as an additional table of contents.
•Thumbnail icons, which provide miniature preview of each page, pro-
vide a link to the pages.
•Numerous links shown in Navy Blue color allow you to jump to related
information.
Version Date Description
1.3 January 2013 •Added DCVERSION register
•Changed offset of MAIN_CSR and
FRM_NAT registers
•Changed range (0x00 to 0xFF) of Phy
register address in ULPI_REG_ACCESS
1.2 July 2011 Replace EPn_INT with EPn_IMS in
Chapter 4
1.1 February 2010 Added 7th and 29th bit description in
EPn_IMS register as per new IP core version
1.0 July 2009 First Publication of USB20SR,Software
based enumeration device IP Core

How to Contact SLS
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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
How to Contact
SLS
For the most up-to-date information about SLS products, go to the SLS
worldwide website at http://www.slscorp.com. For additional information
about SLS products, consult the source shown below.
Information Type E-mail
Product literature services, SLS liter-
ature services, Non-technical cus-
tomer services, Technical support.
[e-mail]

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Typographic
Conventions
The user guide uses the typographic conventions as shown below:
Visual Cue Meaning
Bold Type with Initial Capital
letters All headings and Sub headings Titles in a document are displayed in
bold type with initial capital letters; Example: Core Architecture,
Operation.
Bold Type with Italic Letters All Definitions, Figure and Table Headings are displayed in Italics.
Examples: Table 4-1. Register Details, Figure 2-1. USB 20SR IP
Core Architecture
Italic type Variable names are enclosed in angle brackets (< >) and shown in italic
type. Example: <USB20SR Installation Path>.
1., 2. Numbered steps are used in a list of items, when the sequence of items
is important. such as steps listed in procedure.
•Bullets are used in a list of items when the sequence of items is not
important.
The hand points to special information that requires special attention
The caution indicates required information that needs special consider-
ation and understanding and should be read prior to starting or continu-
ing with the procedure or process.
The warning indicates information that should be read prior to starting
or continuing the procedure or processes.
The feet direct you to more information on a particular topic.

viSystem Level Solutions
Contents
About this Guide ................................................................................................................ iii
Introduction..............................................................................................................................................iii
How To Find Information ........................................................................................................................iii
How to Contact SLS ................................................................................................................................iv
Typographic Conventions .........................................................................................................................v
1. Introduction...............................................................................................................................1
Features.....................................................................................................................................................2
Core Resources .........................................................................................................................................2
Further Information...................................................................................................................................3
2. Core Architecture......................................................................................................................4
ULPI PHY.................................................................................................................................................5
ULPI Interface...........................................................................................................................................5
Protocol Layer...........................................................................................................................................5
EndPoint Registers....................................................................................................................................5
EP0 Controller...........................................................................................................................................5
On Chip RAM...........................................................................................................................................6
Micro Controller/Processor Interface........................................................................................................6
3. Operation...................................................................................................................................7
EndPoints ..................................................................................................................................................8
Buffer Pointers...................................................................................................................................8
Data Organization..............................................................................................................................8
Interrupts...................................................................................................................................................9
Timing................................................................................................................................................9
Software Interaction...........................................................................................................................9
4. Core Registers.........................................................................................................................11
DCVERSION..........................................................................................................................................14
FUNC_ADR............................................................................................................................................15

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INT_MSK ...............................................................................................................................................15
INT_SRC ................................................................................................................................................16
MAIN_CSR ............................................................................................................................................21
FRM_NAT ..............................................................................................................................................23
TEST MODE ..........................................................................................................................................24
SETUP_PACK_1....................................................................................................................................25
SETUP_PACK_2....................................................................................................................................25
ULPI_PHY_CS.......................................................................................................................................25
ULPI_REG_ACCESS.............................................................................................................................26
D_SPEED_SEL ......................................................................................................................................27
D_CNCT.................................................................................................................................................28
Endpoint Registers..................................................................................................................................28
EPn_CSR ................................................................................................................................................28
EPn_IMS.................................................................................................................................................31
EPn_BUF ................................................................................................................................................33
5. Core IOs...................................................................................................................................36
6. Using USB20SR IP in SOPC Builder .....................................................................................37

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1. Introduction
The USB 2.0 Device IP Core (USB20SR) is a RAM based, 32-bit Avalon
interface and ULPI interface support. The core supports both High Speed
(480 Mbps) and Full Speed (12 Mbps) functionality. The core supports three
endpoints Control, IN and OUT. Support of up to 15 endpoints can be added
inside the IP Core as per customer request. Endpoint can be used for IN or
OUT operation at a time. Support of IN and OUT operation on a single
endpoint can be added as per customer request to add support of 15 IN and 15
OUT endpoint. Each endpoint has an endpoint controller that supports
interrupt, bulk, and isochronous transfers.
The core is an RTL design in Verilog that implements an USB device
controller on an ASIC or FPGA. The core has been optimized for popular
FPGA devices and its functionality has been verified on the real hardware. It
is provided as Altera Quartus II Mega function (Altera SOPC Builder ready
component) and integrates easily into any SOPC Builder generated system
using Nios®II Avalon bus.
This user guide will provide you with some basic technical details of
USB20SR device core acting as an Avalon slave in Altera’s SOPC builder.
SOPC builder isa software tool that allows for thecreation ofa NiosII system
module or a more general multi master System On A Programmable Chip
module. A complete Nios II system module contains a Nios II (soft core 32
bit RISC) processor and its associated system peripherals.
For development kits lacking USB interface, SLS has ULPI interface Snap
On Board available, along with a USB 2.0 device IP core integrated into
SOPC builder. The Snap On Board snaps on to the Altera Standard Santa
Cruz header, therefore, now your Nios development kit is with USB 2.0
interface without any extra effort. So now using SOPC builder one can build
a system with USB interface in just a few minutes.
To develop your Embedded System using USB 2.0 ULPI interface refer to
USB 2.0 On-The-Go (ULPI) Snap On Board Reference Manual. You can also

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Introduction
refer to CoreCommander Reference Manual.
Features Following are the USB20SR Device IP core features:
USB 2.0 USB IF high-speed certified
Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)
High speed or Full speed operation selection through Software
Low speed (1.5 Mbps) support also available on special request.
ULPI Interface support
Pre configured for 3 endpoints
•CONTROL
•IN
•OUT
Configurable for up to 15 IN/OUT endpoints which can support Bulk,
Interrupt, Isochronous functionality on each endpoint on customer
request at additional cost.
Fully software controlled CONTROL, IN and OUT endpoints
Avalon Bus compliant
Optimized LE count
Core Resources Table 1-1 shows the LE usage of the Core.
Table 1-1. Core LE Usage Summary
Supported Devices LEs Memory Bits M4k/M9k Blocks Performance
(fmax) MHz
Cyclone 2533 32768 8 m4k 83Mhz
Cyclone II 2527 32768 8 M4K 72Mhz
Cyclone III 2530 32768 8 M9K 90Mhz
Cyclone IV 2532 32768 8 M9K 92Mhz
Stratix 2534 32768 8 M9K 81Mhz
Stratix II 1652 32768 8 M9K 96Mhz
Please contact [email protected] for more details

Further Information
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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
Further
Information
For information about USB20SR IP Core installation directory
structure and its content, licensing, component implementation and its
support, refer readme.html located at <USB20SR Installation Path>\
usb20sr. <USB20SR Installation Path> is the installation directory. The
defaultinstallationdirectory isc:\altera\<version#>\ip\sls.Where version no.
is Quartus setup version.’

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2. Core Architecture
The USB 2.0 Device communicates through two differential lines
(D+ & D-) that connect to a transceiver. The transceiver or physical interface,
in turn, connects to the core via interface signals. Since the core supports all
the transfer types - Control, Bulk, Isochronous and Interrupt, each transfer
type retains a separate pipe for OUT and IN operation. Figure 2-1. illustrates
overall architecture of the USB20SR IP core.
Figure 2-1.USB20SR Device IP Core Architecture
Each of the blocks is described in detail below:
The Micro Controller/Processor interface provides a bridge between Host
Interfaces (ex. Nios II Processor) and internal data memory and control
registers.
Protocol
Layer
ULPI
Interface
ULPI
PHY
MicroController/Processor Interface
(ex. AVALON BUS INTERFACE)
EndPoint
Registers
D+
D-
External
On Chip RAM
USB2.0 System Top
EP0
Controller

ULPI PHY
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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
ULPI PHY The ULPI PHY chip is the external chip that provides a link between USB2.0
IP and the physical USB data lines D+ & D-. The maximum clock from the
PHY is 60MHz in 8 bit mode. All the blocks of USB IP Core related to USB
activity run from the clock provided by the ULPI PHY for synchronization.
ULPI Interface The ULPI block connects through the external PHY. It controls speed negoti-
ation as well as handles all functions related to the line signals. It also handles
the ULPI PHY chip configuration for device operation.
Protocol Layer This block De assembles/Assembles the packet, handles all the standard
USB 2.0 protocol handshakes and control correspondence. Proto layer also
handles all error conditions of USB protocol.
EndPoint
Registers
This block has control and status registers for each endpoints. One can
configure any specific endpoint through these registers via Avalon interface.
Detail description of each register as well as it’s bit is given inside the
Table 4-1 Register Description.
EP0 Controller This module will be implemented fully inside the hardware when the IP Core
is enabled in debug mode. IP Core can be switched into debug mode in place
of normal mode to verify the ULPI Phy chip interface functionality with the
HOST PC.
The section below explains the steps to verify the ULPI PHY chip
functionality with the host PC.
1. Open the usb20sr_debug.v file located at <USB20SR Installation
Path>\hardware\component\hdl.
2. Disable the "‘define SR_ENABLE" line inside the file.
3. Recompile your design.
4. Download the .sof file on your board.
5. Connect the device with the Host PC through the USB 2.0 compliant
cable.
6. The default SLS device should be enumerated on the Host PC without
running a Nios II project.
7. If the device enumeration fails with the host PC, then there will be an
error in generating the reference design or PHY interface on the board.

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Core Architecture
On Chip RAM This memory is used to store transmitted as well as received data for End-
Points. Size of this memory is 2Kbyte for IN and 2Kbyte for OUT endpoints
in default configuration of the IP Core. Microcontroller and deviceinterfaces
with this memory through two different memory ports with separate clock for
each. Size of this memory should be increased through SOPC builder
parameter settings, if number of endpoint increases to use separate memory
buffers for each endpoint.
Micro Controller/
Processor
Interface
This block provides a consistent core interface between the internal functions
of the core and the function-specific host or micro controller.

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3. Operation
This core has been designed to compatible with avalon specific interface. The
Figure 3-1. below shows how the core connects to the function micro
controller and HOST.
IP core functionality is controlled by function controller as shown in
Figure 3-1. through endpoint registers.
Figure 3-1.Operational Block Diagram
The USB core uses onchip memory (512*32) for IN operation as well as
(512*32) for OUT operation separately. IN and OUT memory starts from the
same location inside the IP Core (0x20000).
IN memory is write only memory and OUT memory is read only memory for
processor. For device OUT memory is write only memory and IN memory is
read only memory.No software intervention is needed between endpoint
access. Double buffer mechanism is used for reducing the latency
requirement on the software, and increasing USB throughput.
ULPI
PHY
Core
Logic
Host
Or
Hub
EP0
EP2
(
F
u
n
c
t
i
o
n
S
uP )
F
u
n
c
t
i
o
n
S
(uP )
EP1

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Operation
EndPoints This USB core supports 3 endpoints (Control, IN, OUT). The function
controller must set up the endpoints by writing to the endpoint register:
EPn_CSR. EPn_IMS, EPn_BUFx.
Buffer Pointers
The buffer pointers point to the input/output data structure in memory. If all
buffers are not allocated, the core will respond with NAK acknowledge to the
USB host.
This core supports a double buffering feature which reduces the latency
requirements on the functions micro controller and driver software. Data is
being retrieved/filled from/to the buffers in a round robin fashion. When data
is sent to/from an endpoint, first buffer0 is used. When the first buffer is
empty/full, the function controller, may be notified via an interrupt. The
function controller can refill/empty buffer0 now. Thecore will now use buffer
1 for the next operation. When the second buffer is full/empty, the function
controller is interrupted, and the core will use buffer0 again, and so on. A
buffer that has the used bit set cause the core for replying with NAK/NYET
acknowledgments to the host.
The Buffer’s Used bits indicate when a buffer has been used (this information
is also provided in the Interrupt Source Register). The function controller
must clear these bits after it has emptied/refilled the buffer.
Data Organization
Since the buffer memory is 32 bits wide and USB defines all transactions on
byte boundaries it is important to understand the relationship of data in the
buffer to actual USB byte sequence. This USB core supports Little Endian
byte ordering.

Interrupts
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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
Figure 3-2.Data Organization
The buffer pointer always point to byte 0. The USB core always fetches four
bytes from the buffer memory. The actual final byte that is transmitted in the
Nth transaction depends on the Buffer Size. The MaxPacketSize must always
be a multiple of 4 bytes.
Interrupts The USB core provides interrupt outputs. The output is fully programmable.
The usage of the interrupt is up to the system into which the USB core is
incorporated.
The interrupt mechanism in the USB core consists of a two level hierarchy:
1. The main interrupt source register (INT_SRC) indicates interrupts
that are endpoint independent. These interrupts indicate overall events
that have either global meaning for all endpoints or can not be associated
with an endpoint because of an error condition.
2. The endpoint interrupt source register indicates events that are
specific to an endpoint.
Timing
The interrupt output are asserted when the condition that is enabled in the
interrupt mask occurs. They remain asserted until the main interrupt register
is read.
Software Interaction
An interrupt handler should first read the main interrupt source register
(INT_SRC) to determine the source of an interrupt. It must remember the
value that was read until it is done processing of each interrupt source. If any
ofthe bits15 to 0are set,the interrupthandler should also readthe appropriate
Config/Status Bits
Interrupt Mask
Buffer 0 Pointer
Buffer 1 Pointer
EPn _CSR:
EPn_IMS:
EPn_BUF0:
EPn_BUF1:
Interrupt Source
Buffer 1 Size
UsedBit
UsedBit
0
16173031
Buffer 0 Size

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Operation
endpoint interrupt register to determine endpoint specific events. Multiple
interrupt sources may be indicated at any given time. Software should be
prepared to handle every interrupt source it cares about.
A care must be taken not to lose interrupt sources, as the main interrupt source
register is cleared after interrupt source register read operation.

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4. Core Registers
This section describes all the registers inside the USB20SR Core. The
Register field describes the name of the register. The Offset field describes
the offset of register in USB IP. The Access field describes the type of access
to the register that is read or write. Description field describes the type and
function of register. Table 4-1 shows the register details.
Table 4-1. Register Description
Sr.
No. Register Offset Width Access Description
1DCVERSION 0x00 32 RO IP Core Version/Product ID description register
2FUNC_ADR 0x04 8RW USB function address register
3INT_MSK 0x08 16 RW Interrupt Mask for endpoint independent interrupt
sources
4INT_SRC 0x0c 32 ROC Interrupt source register
5MAIN_CSR 0x10 8RW Control/Status register
6FRM_NAT 0x14 32 RO Frame number and time
7TEST_MODE 0x20 8RW Test mode register for enabling test mode inside
the IP Core
8SETUP_PACK_1 0x30 32 RO First four bytes of received setup packet
9SETUP_PACK_2 0x34 32 RO Second four bytes of received setup packet
10 ULPI_PHY_CS 0x1f0 8RW ULPI PHY Chip enable or disable register
11 ULPI_REG_
ACCESS 0x1f4 32 RW ULPI PHY Chip register read/write register
12 D_SPEED_SEL 0x1f8 8RW Device IP Core speed select register
13 D_CNCT 0x1fc 8RW Device Connect/Disconnect register
14 EP0_CSR 0x40 32 RW EndPoint 0 (Control Endpoint): CSR Register
15 EP0_IMS 0x44 32 ROC EndPoint 0 (Control Endpoint): Interrupt Register
16 EP0_BUFFER0 0x48 32 RW EndPoint 0 (Control Endpoint): Buffer0 Register

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Core Registers
17 EP0_BUFFER1 0x4c 32 RW EndPoint 0 (Control Endpoint): Buffer1 Register
18 EP1_CSR 0x50 32 RW EndPoint 1 CSR Register
19 EP1_IMS 0x54 32 RW and
ROC EndPoint 1 Interrupt Register
20 EP1_BUFFER0 0x58 32 RW EndPoint 1 Buffer0 Register
21 EP1_BUFFER1 0x5c 32 RW EndPoint 1 Buffer1 Register
22 EP2_CSR 0x60 32 RW EndPoint 2 CSR Register
23 EP2_IMS 0x64 32 ROC EndPoint 2 Interrupt Register
24 EP2_BUFFER0 0x68 32 RW EndPoint 2 Buffer0 Register
25 EP2_BUFFER1 0x6c 32 RW EndPoint 2 Buffer1 Register
26 EP3_CSR 0x70 32 RW EndPoint 3 CSR Register
27 EP3_IMS 0x74 32 ROC EndPoint 3 Interrupt Register
28 EP3_BUFFER0 0x78 32 RW EndPoint 3 Buffer0 Register
29 EP3_BUFFER1 0x7c 32 RW EndPoint 3 Buffer1 Register
30 EP4_CSR 0x80 32 RW EndPoint 4 CSR Register
31 EP4_IMS 0x84 32 ROC EndPoint 4 Interrupt Register
32 EP4_BUFFER0 0x88 32 RW EndPoint 4 Buffer0 Register
33 EP4_BUFFER1 0x8c 32 RW EndPoint 4 Buffer1 Register
34 EP5_CSR 0x90 32 RW EndPoint 5 CSR Register
35 EP5_IMS 0x94 32 ROC EndPoint 5 Interrupt Register
36 EP5_BUFFER0 0x98 32 RW EndPoint 5 Buffer0 Register
37 EP5_BUFFER1 0x9c 32 RW EndPoint 5 Buffer1 Register
38 EP6_CSR 0xA0 32 RW EndPoint 6 CSR Register
39 EP6_IMS 0xA4 32 ROC EndPoint 6 Interrupt Register
40 EP6_BUFFER0 0xA8 32 RW EndPoint 6 Buffer0 Register
41 EP6_BUFFER1 0xAc 32 RW EndPoint 6 Buffer1 Register
42 EP7_CSR 0xB0 32 RW EndPoint 7 CSR Register
Table 4-1. Register Description
Sr.
No. Register Offset Width Access Description

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January 2013USB 2.0 (USB20SR) Device IP Core User Guide
43 EP7_IMS 0xB4 32 ROC EndPoint 7 Interrupt Register
44 EP7_BUFFER0 0xB8 32 RW EndPoint 7 Buffer0 Register
45 EP7_BUFFER1 0xBc 32 RW EndPoint 7 Buffer1 Register
46 EP8_CSR 0xC0 32 RW EndPoint 8 CSR Register
47 EP8_IMS 0xC4 32 ROC EndPoint 8 Interrupt Register
48 EP8_BUFFER0 0xC8 32 RW EndPoint 8 Buffer0 Register
49 EP8_BUFFER1 0xCc 32 RW EndPoint 8 Buffer1 Register
50 EP9_CSR 0xD0 32 RW EndPoint 9 CSR Register
51 EP9_IMS 0xD4 32 ROC EndPoint 9 Interrupt Register
52 EP9_BUFFER0 0xD8 32 RW EndPoint 9 Buffer0 Register
53 EP9_BUFFER1 0xDc 32 RW EndPoint 9 Buffer1 Register
54 EP10_CSR 0xE0 32 RW EndPoint 10 CSR Register
55 EP10_IMS 0xE4 32 ROC EndPoint 10 Interrupt Register
56 EP10_BUFFER0 0xE8 32 RW EndPoint 10 Buffer0 Register
57 EP10_BUFFER1 0xEc 32 RW EndPoint 10 Buffer1 Register
58 EP11_CSR 0xF0 32 RW EndPoint 11 CSR Register
59 EP11_IMS 0xF4 32 ROC EndPoint 11 Interrupt Register
60 EP11_BUFFER0 0xF8 32 RW EndPoint 11 Buffer0 Register
61 EP11_BUFFER1 0xFc 32 RW EndPoint 11 Buffer1 Register
62 EP12_CSR 0x100 32 RW EndPoint 12 CSR Register
63 EP12_IMS 0x104 32 ROC EndPoint 12 Interrupt Register
64 EP12_BUFFER0 0x108 32 RW EndPoint 12 Buffer0 Register
65 EP12_BUFFER1 0x10c 32 RW EndPoint 12 Buffer1 Register
66 EP13_CSR 0x110 32 RW EndPoint 13 CSR Register
67 EP13_IMS 0x114 32 ROC EndPoint 13 Interrupt Register
68 EP13_BUFFER0 0x118 32 RW EndPoint 13 Buffer0 Register
69 EP13_BUFFER1 0x11c 32 RW EndPoint 13 Buffer1 Register
Table 4-1. Register Description
Sr.
No. Register Offset Width Access Description