Tektronix 7D01 User manual
Tektronix,
Inc
.
P.O
.
Box
500
Beaverton,
Oregon
97077
070-2206-02
Product
Group 57
IN
COMMITTED
TOEXCELLENCE
CHECK
FOR
CHANGE
INFORMA
F
THIS
MANUAL
.
(Serial
No
.
I°
I
00000
and
up)
N
Serial
Number
ION
MANUAL
.
First
Printing
OCT
1976
Revised
OCT
1982
LIST
OFILLUSTRATIONS
... ................... .
ii
LIST
OF
TABLES
............ ............... .
ii
SAFETY
SUMMARY
SECTION
1
GENERAL
INFORMATION
INTRODUCTION
............. .
.
.........
1-1
GLOSSARY
..................
.
........
1-1
INSTALLATION
.............. ... .......
1-1
PACKAGING
FOR
SHIPMENT
..........
.
.....
1-2
SPECIFICATION
..
.
................
.
......
1-3
S'T'ANDARD
ACCESSORIES
............... ....
1-
9
SECTION
2
OPERATING
INSTRUCTIONS
FRONTPANEL
CONTROLS,
CONNECTORS
AND
INDICATORS
..........
. .
2-1
DETAILED
OPERATING
INFORMATION
..........
2-1
AUXILIARY
FUNCTIONS
...
. .
............
2-1
INTERNAL
STRAP
SELECTIONS
.
....
........
2-4
SIGNAL
CONNECTIONS
........
....
......
2-6
DISPLAYING
DATA
................
.
....
2-7
TRIGGERING
.....
. .
..............
. .
. .
2-7
CLOCK
QUALIFIER
OPERATION
........
.
.
. .
2-8
ASYNCHRONOUS
AND
SYNCHRONOUS
DATA
SAMPLING
.
. . .
.
............
2-9
OPERATIONAL
ANALYSIS
................
2-10
APPLICATIONS
...........
.
..............
2-13
INTRODUCTION
................
, .
.2-13
FAULT'
IDENTIFICATION
......
.
.
.
........
2-13
DELAY
BY
WORDS
............. ........
2-13
DELAY
BY
EVENTS
............... .
.
....
2-14
STATE
TABLE
AND
MAPPING
DISPLAYS
.
.
....
2-14
MICROPROCESSOR
ANALYSIS
.......... ....
2-16
STORAGE
BUFFER
ANALYSIS
............
. .
-2-17
FUNCTIONAL
CHECK
...................
2-17
REV
B,
APR
1979
PAGE
THE
REMAINING
PORTION
OF
THIS
TABLE
OF
CON-
TENTS
LISTS
THE
SERVICINGINSTRUCTIONS
.
THESE
SERVICING
INSTRUCTIONS
ARE
FOR
USE
BY
QUALI-
FIED
PERSONNEL
ONLY
.
T
O
AVOID
ELECTRICAL
SHOCK,
DO
NOT
PERFORM
ANY
SERVICING
OTHER
THAN
THAT
CALLED
OUT
IN
THE
OPERATING
IN-
STRUCTIONS
UNLESS
QUALIFIED
TODO
SO
.
SECTION
3
THEORY
OF
OPERATION
BLOCK
DIAGRAM
DESCRIPTION
...............
3-1
DETAILED
CIRCUIT
DESCRIPTION
.
.............
3-3
FRONT
PANEL
WIRING
....
.
..
. ...........
3-3
WORD
RECOGNIZER
..........
.
. .........
3-3
MEMORY
................
.
. .
. .
.......
3-4
TRIGGER
..................
.
.........
3-7
TIMEBASE
.....................
.
.
. .
. .
3-9
VERTICAL
OUTPUT
.....................
3-9
HORIZONTAL
OUTPUT
..................
3-10
CURSOR
...
.
........................
3-10
POWER
SUPPLIES
.
.....................
3-12
SECTION
4
MAINTENANCE
PREVENTIVE
MAINTENANCE
.................
4-1
CLEANING
.......
.
. . .................
4-1
VISUAL
INSPECTION
... . . . .
.
.
. .
..........
4-1
LUBRICATION
............
.
. .
.
.........
4-1
SEMICONDUCTOR
CHECKS
....... ..........
4-2
TROUBLESHOOTING
...............
.
.......
4-3
TROUBLESHOOTING
EQUIPMENT
.... ...
.
....
4-3
-
TROUBLESHOOTING
TECHNIQUES
.......
. .
. .
4-3
CORRECTIVE
MAINTENANCE
..............
.
. .
4-7
OBTAINING
REPLACEMENT
PARTS
...........
4-7
SOLDERING
TECHNIQUES
.................
4-7
COMPONENT
REMOVAL
AND
REPLACEMENI
......
4-8
ADJUSTMENT
AFTER
REPAIR
..............
4-14
SECTION
5
PERFORMANCE
CHECK
AND
ADJUSTMENT
PRELIMINARY
INFORMATION
. ..............
5-1
TEST
EQUIPMENT
REQUIRED
.
. .
...
.........
5-1
PRELIMINARY
PROCEDURE
. . . . . .
.
.........
5-3
PERFORMANCE
CHECK
AND
ADJUSTMENT
PROCEDURE
................
.
. .....
.
. .
5-4
SECTION
6
REPLACEABLE
ELECTRICAL
PARTS
SECTION
7
INSTRUMENT
OPTIONS
7D01
Instruction
(SN
B020000
&
up)
SECTION
8
DIAGRAMS
AND
CIRCUIT
BOARD
ILLUSTRATIONS
SECTION
9
REPLACEABLE
MECHANICAL
PARTS
CHANGE
INFORMATION
PAGE
71301
Instruction
(SN
B020000
&
up)
FIGURE
NO
.
PAGE
Frontis-
piece
71301
Logic
Analyzer
. .
.............
.
. .
.iv
1-1
71301
Dimensional
Drawing
.....
.....
. .
.1-8
2-1
Front-panel
controls,
connectors,
and
indicators
. .
.... ....
. .
. .
.
.
.2-2
2-2
Internal
Display
Clock Source and
Full
Display/First
Trigger
Selectors
.
. .
....
...
.2-4
2-3
Internal
Signal
Selector
. .
....
. .
.
. .
.....
.2-5
2-4
Pin
assignments
for
Data
Out
connector
J120
. .
. .
.
...
........
.2-6
2-5
Suggested
methods
for
terminating
data
outputs
from Data
Out
connector
J120
.
. .
.
............
.2-7
2-6
Suggested
method
for
assembling
a
remote
Manual
Reset button
.............
.2-7
2-7
Typical
channel
0
to
15
pretrigger
data
display
......
.
.
...........
.2-8
2-8
Equipment
setup
and
displays
for
finding
a
data
fault
and examining
it
on an
analog
display
.
.
..........
.2-14
2-9
Equipment
setup
and
data
display
window
that
has
been
positioned
after
a
preselected
word
has
occurred
25
times
......
2-15
2-10
Equipment
setup
and
display
window
that
has
been
positioned
after
10,500
2-15
2-16
2-17
.3-2
.3-3
.3-5
LIT
I
LLU
,ATI
N
FIGURE
NO
.
PAGE
3-4
Latch
Clock
timing
for
4-channel
operation
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
3-5
3-5
Latch
Clock
timing
for
8-channel
operation
. . . . . . . .
.
. ..............
.3-6
3-6
Memory
Selector
timing
for
4-channel
operation
(display
time
only)
....
........
.3-6
3-7
Memory
Selector
timing
for
8-channel
operation
(display
time
only)
.
. .
.......
.3-6
3-8
Binary
output
of
U628
versus
channel
displayed
.....
...
........
.
.3-9
4-1
Lubrication
procedure
for
a
typical
cam
switch
.
.
..............
.
.
..
.4-2
4-2
Circuit
board
locations
...
.
....
.
. .
.
.4-5
4-3
Power
supply
+5
volt test
point
location
.....
. .
.4-6
4-4
Location
of securing
screws
on
the
Memory
circuit
board
.
.....
.
. .
. .
.
.4-8
4-5
Multi-pin
connector
and P
number
orientation
for
the
Memory
circuit
board
. .
. .
.
.
.4-9
4-6
Location
of securing
screws
on
the
Interface
circuit
board
.....
.
. .
. .
.
...
.
4-10
4-7
Locations
of
securing
screws
on
the
Output
circuit
board
......
. .
. .
.
. .
4-10
4
.8
Locations
of
securing
screws
and
shield
on
the
Power
Supply board
.
.
........
....
4-11
4-9
Locations
of securing
screws
on
the
Cursor
circuit
board
. .
. .
...
. .
.....
4-11
4-10
Locations
of
hex
nuts
and
screws
on
front
sub
panel
which
secure
the
Word
Recog-
nizer
circuit
board
.
..........
4-12
4-11
Exploded
view
of
circuit-board
pin
and
ferrule
....
.....
.
. .
.
.
..........
4-14
The
illustrations
in
Section
8
are
located
near
their associated
Diagrams
on
the
foldout
pages
.
REV
.
A,
MAR
197
7
2-11
clock
pulses
have occurred
.. ...........
Typical
setup
for
troubleshooting
a
microprocessor
system
.. ... .........
2-12
Typical
setup
and
display
for
trouble-
shooting
a
storage
buffer
................
3-1
71301
Block
Diagram
............
3-2
Equivalent
circuit
for
one
channel
of
P6451
Data
Acquisition
Probe
. ........
.
3-3
Truth
Table
for
Store/Display
Clock
Gate
.
........................
.
.
LIST
TABLE
NO
.
1-1
Electrical
Characteristics
.. ....
.
. .
.
......
1-2
Environmental
Characteristics
...... ........
1-3
Physical
Characteristics
..... .. ...........
2-1
Format
Output
Levels
. .
.
.......
2-2
Minimum
Clock
Pulses
Required
to
Display
Data
(After
the
MANUAL
RESET
Button
is
Pressed)
........... .
.
...
.
.........
PAGE
...............
2-10
..............
.
.4-6
...............
.5-1
...............
.7-1
GE
TABLE
NO
.
.1-3
2-3
Operational
Analysis
....
.1-8
4-1
Power
Supply
Tolerances
.
.1-8
5-1
`test
Equipment
......
.2-1
7-1
Option
Information Locat
.2-9
LIST
OFILLUSTRATIONS
...
.
.
. .
.
.
..............
ii
LIST
OFTABLES
........
.
. .
.
. . .
.
.
.
. .
.
.......
ii
SAFETY
SUMMARY
.....
.
...
.
.
. .
., .,
.
.,
....
.iii
SECTION
1
GENERAL
INFORMATION
INTRODUCTION
.............
.
.
.....
....
1-1
GLOSSARY
..................
.
. . .
. .
...
1-1
INSTALLATION
..............
. .
. . . .
.
...
1-1
PACKAGINGFOR
SHIPMENT
..........
.
.
.
...
1-2
SPECIFICATION
.................
. .
.......
1-3
STANDARD
ACCESSORIES
..........
....
. ....
1-9
SECTION
2
OPERATING
INSTRUCTIONS
FRONT
PANEL
CONTROLS,
CONNECTORS
AND
INDICATORS
........
....
2-1
DETAILED
OPERATING
INFORMATION
......
.
.
. .
2-1
AUXILIARYFUNCTIONS
...............
.
.
2-1
INTERNAL
STRAP
SELECTIONS
.............
2-4
SIGNAL
CONNECTIONS
.
. ................
2-6
DISPLAYING
DATA
......... .
.
..........
2-7
TRIGGERING
.................
. .
......
2-7
CLOCK
QUALIFIER
OPERATIO
......
.
.....
2-8
ASYNCHRONOUSAND
SYNCHRONOUS
DATA
SAMPLING
..................
. .
. .
2-9
OPERATIONAL
ANALYSIS
........
.
..
.
....
2-10
APPLICATIONS
.................... .
...
. .
2-13
INTRODUCTION
.................
.
. . ...
2-13
FAULT
IDENTIFICATION
..............
.
.
.
2-13
DELAY
BY
WORDS
...................
. .
2-13
DELAY
BY
EVENTS
.....................
2-14
STATE
TABLE
AND
MAPPING
DISPLAYS
......
2-14
MICROPROCESSOR
ANALYSIS
..............
2-16
STORAGE
BUFFER
ANALYSIS
..............
2-17
FUNCTIONAL
CHECK
...................
2-17
REV
C
JUN
1980
'THE
REMAININGPORTION
OF
THIS
TABLE
OF
CON-
TENTS
LIS'T'S
THE
SERVICINGINSTRUCTIONS
.
THESE
SERVICING
INSTRUCTIONS
ARE
FOR
USE
BY
QUALI-
FIED
PERSONNEL
ONLY
.
T
O
AVOID
ELECTRICAL
SHOCK,
DO
NOT
PERFORM
ANY
SERVICING
OTHER
THAN
THAT
CALLED
OUT
IN
THE
OPERATING
IN-
STRUCTIONS
UNLESS
QUALIFIED
TO
DO
SO
.
PAGE
7D01
Instruction
(SN
B020000
&
up)
SECTION
3
THEORY
OF
OPERATION
BLOCK
DIAGRAM
DESCRIPTION
....
.
.
.........
3-1
DETAILED
CIRCUIT
DESCRIPTION
. .
.
...
........
3-3
FRONT
PANEL
WIRING
.
.
.
.
....
.
.
.........
3-3
WORD
RECOGNIZER
......
.
.
.
.
....
.
.
....
.
3-3
MEMORY
.............
........
......
.
3-4
TRIGGER
.........
...
. .
. .
.
. .
........
.
3-7
TIMEBASE
...........
.
.
. .
.
.
.
...
..
....
3-9
VERTICAL
OUTPUT
.......
.
....
....
.
. .
.
.
3-9
HORIZONTAL
OUTPUT
. .
. .
. .
.
.
...
....
. .
.
3-10
CURSOR
..................
. .
.
.......
3-10
POWER
SUPPLIES
...........
.....
.
.....
3-12
SECTION
4
MAINTENANCE
PREVENTIVE
MAINTENANCE
.....
.
. .
.
.
.......
4-1
CLEANING
...........
4-1
VISUAL
INSPECTION
.................
. .
. .
4-1
LUBRICATION
.................
...
.
...
.
4-1
SEMICONDUCTOR
CHECKS
...........
. .
...
.
4-2
TROUBLESHOOTING
..................
.
....
4-3
TROUBLESHOOTING
EQUIPMENT
........
.
...
4-3
TROUBLESHOOTING
TECHNIQUES
...........
4-3
CORRECTIVE
MAINTENANCE
.................
4-7
OBTAINING
REPLACEMENT
PARTS
...........
4-7
SOLDERING
TECHNIQUES
.................
4-7
COMPONENT
REMOVAL
AND
REPLACEMENT
.....
4-8
ADJUSTMENT
AFTER
REPAIR
..............
4-14
SECTION
5
PERFORMANCE
CHECK
AND
ADJUSTMENT
PRELIMINARY
INFORMATION
..............
5-1
TEST
EQUIPMENT
REQUIRED
...............
5-1
PRELIMINARY
PROCEDURE
....... .
.... .
.5-3
PERFORMANCE
CHECK
AND
ADJUSTMENT
PROCEDURE
......................... .
5-5
SECTION
6
REPLACEABLE
ELECTRICAL
PARTS
SECTION
7
INSTRUMENT
OPTIONS
SECTION
8
DIAGRAMS
AND
CIRCUIT
BOARD
ILLUSTRATIONS
SECTION
9
REPLACEABLE
MECHANICAL
PARTS
CHANGE
INFORMATION
PAGE
7D01
Instruction
(SN
B020000
&
up)
TABLE
NO
.
LIST
.
.
.
...
.iv
....,
.1-8
.
. .
.
.
.2-2
. .
. .
.
.2-4
. .
...
.2-5
.....
.2-6
2-5
Suggested
methods
for
terminating
data
outputs
from
Data
Out
connector
J120
.
...
......
....
..
.2-7
2-6
Suggested
method
for
assembling
a
remoteManual
Reset
button
........
....
.
.2-7
2-7
Typicalchannel
0
to
15
pretrigger
data
display
....
.
.
.......
.
...
.2-8
2-8
Equipment
setup
and
displays for
finding
a
data
fault
and
examining
it
on
an
analog
display
.
..........
.
2-14
2-9
Equipment
setup
and
data
display
window
that
has
been
positioned
after
a
preselected
word
has
occurred
25
times
......
2-15
2-10
Equipment
setup
and
display
window
that
has
been
positioned
after
10,500
clock
pulses
have occurred
. .
...........
2-15
2-11
Typical
setup
for
troubleshooting
a
microprocessor
system
. .
...
.........
2-16
2-12
Typical
setup
and
display for
trouble-
shooting
a
storage buffer
................
2-17
3-1
7D01
Block
Diagram
.
. .
........
.3-2
3-2
Equivalent
circuit
for
one
channel
of
P6451
Data
Acquisition
Probe
.
.........
.3-3
3-3
TruthTable
for
Store/Display
Clock
Gate
. ....
....
.
.
...............
.3-5
LIST
1-1
Electrical
Characteristics
. .
..............
1-2
Environmental
Characteristics
.............
.
1-3
Physical
Characteristics
.......,.....,.,.
.
2-1
FormatOutput
Levels
.
.
......
2-2
Minimum
Clock
Pulses
Required
to
.
Display
Data
(After
the
MANUAL
RESET'
Button
is
Pressed)
...... .. ..................
FIGURE
PAGE
NO
.
P
3-4
Latch
Clock
timing
for
4-channel
operation
. .
. .
....
.,..,.
.
3-5
3-5
LatchClock
timing
for
8-channel
operation
.....
. .
.......
.3-6
3-6
Memory
Selector
timing
for
4-channel
operation
(display
time
only)
.
. .
.......
.3-6
3-7
Memory
Selector
timing
for
8-channel
operation
(display
time
only)
.
. .
,.,....
.3-6
3-8
Binary
output
of
U628
versus
channel
displayed
.....
...
. . .
.
.....
.3-9
4-1
Lubrication
procedure
for a
typical
cam
switch
. .
.............. .
. .
.
.4-2
4-2
Circuit
board
locations
...
.
.
....
.
.
.
.
.4-5
4-3
Power
supply
+5
volt
test
point
location
. .
. .
.
. .
.4-6
4-4
Location
of
securing
screws
on
the
Memory
circuit
board
.
.........
.
.
.4-8
4-5
Multi-pin
connector
and
P
number
orientation for
the
Memory
circuit
board
......
.4-9
4-6
Location
of
securing
screws
on
the
Interface
circuit
board
.....
..........
4-10
4-7
Locations
of securing
screws
on
the
Output
circuit
board
......
.......
4-10
4-8
Locations
of securing
screws
and
shield
on
the
Power
Supply
board
. .
..........
4-11
4-9
Locations
of securing
screws
on
the
Cursor
circuit
board
. .
.....
.......
4-11
4-10
Locations
of
hex
nuts
and
screws
on
front
sub
panel
which
secure
the
Word
Recog-
nizer
circuit
board
.
..........
4-12
4-11
Exploded
view
of
circuit-board
pin
and
ferrule
........................
4-14
The
illustrations
in
Section
8
are
located
near
their
associated
Diagramson
the
foldout
pages
.
PAGE
.
es
.
ca
REV
.
A,
MAR
1977
PAGE
................
2-10
................
.4-6
................
.5-1
or
...............
.7-1
FIGURE
NO
.
Frontis-
piece
7D01
Logic
Analyzer
.. ....
. .
. .
.
.
1-1
7D01
Dimensional
Drawing
.....
.
. .
2-1
Front-panel
controls,
connectors,
and
indicators
. . . . . . . .
. .
2-2
Internal
Display
Clock
Source
and
Full
Display/First
Trigger
Selectors
.....
2-3
Internal
Signal Selector
.. ......
.
.
.
2-4
Pin
assignments
for
Data
Out
connector
J120
.. .. ....
.
GE
TABLE
NO
.
.1-3
2-3
Operational
Analysis
. .
.1-8 4-1
Power
Supply
Toleran
.1-8 5-1 Test
Equipment
....
.2-1
7-1
Option
Information
L
.2-9
Ground
the
Instrument
Do
Not
Operate
in
Explosive
Atmosphere
Avoid
Live Circuits
Do
Not
Service
or
Adjust
Alone
AFETY
WARNING
I
71301
Instruction
(SN
B020000
&
up)
The
following
safety
information
is
provided
to
ensure
safe
operation
of
this
instrument
.
WARNING
information
is
intended
to
protect
the
operator
;
CAUTION
information
is
intended
to
protect
the
instrument
.
The
following
are
general
safety
pre-
cautions that
must
be
observed
during
all
phases
of
operation
and
maintenance
.
To
reduce
electrical-shock
hazard,
the
mainframe
(oscilloscope)
chassis
mustbe
properly
grounded
.
Refer
to
the
mainframe
manual
for
grounding
information
.
Do
not
operate
this
instrument
in
an
area
where
flammable
gases
or
fumes
are
present
.
Such
operation
could
cause
an
explosion
.
Electrical-shock
hazards
are
present
in
this
instrument
.
7
-
he
protective
instrument
covers
must
not
be
removed
by
operating
personnel
.
Component
replacement
and
internal
adjustments
must
be
referred
to
qualified service
personnel
.
Do
not
service
or
make
internal
adjustments
to this
instrument
unless
another
person,
capable
of
giving
first
aid
and
resusci-
tation,
is
present
.
7D01
(SN
B020000
&
up)
7D01
FEATURES
2206-1
The
7D01
Logic
Analyzer
will
store
and
display
up
to
16
channels
of
digital
data
when
installed
in a
7000-series
mainframe
.
The
cursor
function provides
an
intensified
zone
on the
data
display,
and
a
corresponding
numerical
readout
display
shows
the
logic state
(1
or
0)
for
each
displayed
channel
of data
.
The
position of the
cursor,
relative
to the
trigger,
is
also
displayed
on
the
crt
readout
.
Cursor
readout
is
displayed
in
either
3-bit
or
4-bit
bytes
.
Digital
data
can
be
stored
in
3
formats
:
4
channels
at
1016
bits/channel,
8
channels
at
508
bits/channel,
or
16
channels
at
254
bits/channel
.
The
sample
rate
is
selectable
from
10
nanoseconds
to 5
milliseconds/sample
(in
a
5-2-1
sequence)
when
using the
internal
time
base,
or can be
used
with
an
external
clock
signal
(up to
50
megahertz)
.
The7D01
can
be
triggered
from
4 sources
:
channel
0
data,
an
external
signal,
a
built-in
16-channel
word
recognizer,
or
man-
ually
.
The
triggered
data
can
be
produced
following
the
trigger
(POST
TRIG),
centered
around
the
trigger
(CENTER),
or
pre-
ceeding
the
trigger
(PRETRIG)
.
The
input
threshold
can
be
varied
from
minus
12
volts
to
plus
12
volts,
or
set
to plus
1
.4
volts
for
TTL
logic
levels
.
The
Word
Recognizer
produces
an output
when
the
logic
states
of the 16
input
data
channels
match
the
states
of the
corres-
ponding
Word
Recognizer
switches
.
Two
qualifier
inputs are
also
provided
to
enable
the
Word
Recognizer
output
.
The
Word
Recognizer
operates
in
either
the
synchronous
or
asynchronous
mode
.
A
variable
filter
(to
at
least
300
nanoseconds)
allows
rejection
of
brief
false-trigger
signals
.
The
7D01
Logic
Analyzer
will
store
and
display
up
to 16
channels
of
digital
data
when
installed
in
a
7000-series
mainframe
.
The
cursor
function provides
an
intensified
zone on
the
data
display,
and
a
corresponding
numerical
readout
display
shows
the
logic state
(1
or 0)
for
each
displayed
channel
of data
.
The
position
of
the
cursor,
relative
to
the
trigger,
is
also
displayed
on
the
crt
readout
.
Cursor readout
is
displayed
in
either
3-bit
or
4-bit
bytes
.
Digital
data
can
be stored
in
3
formats
:
4
channels
at
1016
bits/channel,
8
channels
at
508
bits/channel,
or
16
channels
at
254
bits/channel
.
The
sample
rate
is
selectable
from
10
nanoseconds
to
5
milliseconds/sample
(in
a
5-2-1
sequence)
when
using
the
internal
time
base,
or
can
be
used with
an
external
clock
signal
(up
to
50
megahertz)
.
The
7D01
can be
triggered
from
4
sources
:
channel
0
data,
an
external
signal,
a
built-in
16-channel
word
recognizer,
or
man-
ually
.
The
triggered
data
can be
produced
following the
trigger
(POST
TRIG),
centered
around
the
trigger
(CENTER),
or pre-
ceeding
the
trigger
(PRE
TRIG)
.
The
input
threshold can
be
varied
from
minus
12
volts
to
plus
12
volts,
or
set
to plus
1
.4
volts
for
TTL
logic
levels
.
The
Word
Recognizer
produces
an
output
when
the
logic
states
of
the
16
input
data
channels
match
the
states
of
the
corres-
ponding
Word
Recognizer
switches
.
Two
qualifier
inputs
are
also
provided
to
enable the
Word
Recognizer
output
.
The
Word
Recognizer
operates
in
either
the
synchronous
or
asynchronous
mode
.
A
variable
filter
(to
at
least
300
nanoseconds)
allows
rejection
of
brief
false-trigger
signals
.
iv
7D01
(SN
B020000
&
up)
7D01
FEATURES
REV
B,
JAN
1979
The
7D01
is
calibrated
and
ready
to
use
when
received
.
It is
designed
to
occupy
a
vertical
and
horizontal
plug-in
compartment
in
all
7000-series
mainframes
with
readout
except
the
7104, which
may
suffer
crt
damage
that
will
not
be
covered
by
the
instrumentwarranty,
and
the
Digital
Processing
Oscilloscope
(DPO),
which
will
not
digitize
the
7D01
outputs
.
There
are
some
.
.
.
.
azMwarIturOEXCEUFNce
Date
:
___
Product
:
__
7D01__
Q
.
C
ANAL
Y
I
R
4-22-81
IN
ION
Change
Reference
:
Manual
Part
No
. : , .
.--------
Q7_Q72Z0fa-02
. .
.__
71301
Operator's
Manual
The
Operator's
manual
contains
the
information
necessary
to
operate
the
7001
Logic
Analyzer
.
The
manual
is
divided
into
three
sections,
each
covering
a
specific
topic of the
instrument
.
Section
1
provides
a
basic
description of
the
7001,
a
glossary
of
logic
terms,
installation
instructions,
and
specifications
.
Section
2
contains
operating
information
for the
instrument
.
Information
concerning
available
op-
tions
for
the
7001
is
on
a
tabbed
page
in
Section
3
.
7001
Instruction
Manual
The
Instruction
manual
provides
operating
and
servicing
information
for
the
7001
Logic
Analyzer
.
The
manual
is
divided
into
ten
sections
.
Operating
information
is
covered
in
the
first
two
sections
;
servicing
information
is
contained
in
the
remaining
eight
sections
of
the
manual
.
Schematics
are
located
at
the
rear
of the
manual
and
can
be
unfolded
and
used
for
reference
while reading
other
parts
of the
manual
.
The
reference designators
and
symbols
used
on
the
schematics
are
defined
on
the
first
page
of the
Diagrams
section
.
Abbreviations
used
in
the
manuals,
except
in
the
parts
list
and
schematics,
comply
with
the
American
National
Standards
Institute
Y1
.1-1972
publication
.
The
parts
lists
are
computer
printouts
and
use
computer-
supplied
abbreviations
.
CPU-Central
Processing
Unit
.
ECL---Emitter-Coupled
Logic
.
REV
OCT
1982
INTRODUCTION
GLOSSARY
The
terms
listed
in
this
glossary
are
used
throughout
this
manual
.
Asynchronous-Multiple
digital
information
transferred
at
non-common
clock
rates
.
Bit---The
smallest
increment
of
digital
information
.
Jitter--A
form
of
distortion
in
asynchronous
systems
that
is
due
to
timing
variations
of the received data
.
Multiplexing--The
combining
of
multiple
inputs into
a
single
output
.
Parallel-to-Serial
Conversion--The
technique
of
storing
a
digital
pattern
from
a
parallel
bus,
then
transferring
that
pattern
out
to a
serial
bus
.
N
~
All
ON
Parity
Bits--Bits
added
to
the data
stream
which
enable the
receiver
to
verify
whether
the data
is
correctly
or
incor-
rectly
received
.
PROM
.
-Programmable
ReadOnly
Memory
.
RAM-Random
Access
Memory
.
Serial
Data-Data
transferred
on
a
single
line
.
Serial
data
logic
is
derived
in a
sequential
mode
.
Store
Clock---The clock
used
to
store
information
into
the
7001
memory
.
Synchronous--Digital
information
transferred
with
the
same
clock
reference
.
Threshold Voltage--The
comparator
input
voltage
on
the
inverting
input,
which
is
used
as
a
reference
.
Thus,
if
the
signal
on
the
non-inverting
input
is
above
the
threshold
voltage,
the
output
is
H
I ;
if
the
signal
is
below
the
threshold
voltage,
the
output
is
LO
.
TTL-Transistor-Transistor
Logic
.
Section
1--7001
(SN
B020000
&
up)
"Wired-OR"-ECL
gate
outputs
that
are
connected
together
to
yield
the
equivalent
output
of an
OR
gate
.
INSTALLATION
The7001
is
calibrated
and
ready
to
use
when
received
.
It
is
designed
to
occupy
a
vertical
and
horizontal
plug-in
com-
partment
in
all
7000-series
mainframes
with
readout
except
the
7104,
which
may
suffer
crt
damage
that
will
not
be
cov-
ered
by
the
instrument
warranty,
and
the
Digital
Processing
Oscilloscope
(DPO),
which
will
not
digitize
the
7001
out-
puts
.
There
are
some
operating
modes,
however,
that
will
not
provide
proper
operation
.
These
modes
are discussed
under
Displaying
Data
in
Section
2
.
Install
the
7001
in
the
two
compartments
on
the
right
side
of a
three-compartment
mainframe,
or
in
the
right
vertical
andA
horizontal
compart-
iments
in
the
center
of
a
four-compartment
mainframe
.
NOTE
Some
rackmounted
mainframes
have
vertically
mounted
rods
in
front
of
the
plug-in
compart-
ments
that
interfere
with
the
installation
of
the
7001
.
Detach
these
rods
by
removing
the
mount-
ing
screws
at
each
end
before
installing
the
7001
.
General
Information--7DO1
(SN
B020000
&
up)
To
install
the
7DO1
in
the
mainframe,
align
the
7DO1
tracks
with
the
rails
of a
vertical
and
horizontal
plug-in
compart-
ment
.
Gently
slide
the
7DO1
into the
mainframeand
push
firmly to lock
the
7DO1
front
panel
flush
with the
mainframe
.
To
remove
the
7DO1,
grasp the
release
latch
in
the
lower
left
cornerand
pull
the
7DO1
out
of
the
mainframe
.
PACKAGING
FOR
SHIPMENT
If
this
instrument
is
to be
shipped
for
long distances
by
commercial
transportation,
it is
recommended
that
the
instrument
be
packaged
in
the
original
manner
for
maxi-
mum
protection
.
The
carton
and
packing
material
in
which
your
instrument
was
shipped
should
be saved
and
used
for
this
purpose
.
If
the
original
packaging
is
unfit
for
use or
not
available,
package
the
instrument
as
follows
:
1
.
Obtain
a
carton
of
corrugated
cardboard
with
at
least
a
200
pound
test
strength
and
inside
dimensions
of
no
less
than
six
inches
more
than
the
instrument
dimensions
;
this
will
allow
for
cushioning
.
2
.
Surround
the
instrument
with polyethylene
sheeting
to
protect the
finish
of the
instrument
.
3
.
Cushion
the
instrument
on
all
sides
by
tightly
packing
dunnage
or
urethane
foam
between
the
carton
and
the
instrument,
allowing
three inches
on
all
sides
.
4
.
Seal
the
carton
with
shipping
tape
or an
industrial
stapler
.
Also,
if
this
instrument
is
to be
shipped
to a
Tektronix
Service
Center
for
service
or
repair,
attach
a
tag
to
the
instrument
showing
the
following
:
Owner
of
the
instru-
ment
(with
address),
the
name
of
an
individual
at
your
firm
that
can
be
contacted,
complete
instrument
type
and
serial
number,
and
a
description of the
service
required
.
Mark
the
address
of
the
Tektronix
Service Center,
and
your
return
address,
on
the
carton
in
one
or
more
prominent
locations
.
REV
.
A,
MAR
1977
The
electrical
specifications
listed
in
Table
1-1
apply
when
the
following
conditions
are
met
:
(1)
The
instrument
must
have
been
adjusted
at
an
ambient
temperature
between
+20°
and
+30
0
C
(+68°
and
+86
°
F), (2)
the
instrument
must
be
operating
in
an
ambient
temperature
between
0
0
and
+40
0
C
(+32°
and
+104
°
F),
and
(3)
the
instrument
must
have been
operating
for
at
least
20
minutes
.
Characteristic
__-
SPECIFICATIO
TABLE
1-1
Electrical
Characteristics
CLOCK
AND
DATA
INPUTS
Probe
Inputs
(Clock,
Qualifier,
and
Data)
Input R
and
C
'Threshold
Voltage
VAR
(at
Monitor
Jack)
TT
L
Minimum
Logic
Swing
Maximum
Logic
Swing
~~
Maximum
Non-Destructive
Input
Voltage
External
Clock
Minimum
Clock
Period
CH
0-3
CH
0-7
CH
0-15
Minimum
Clock
Pulse
Width
_
CH
0-3
CH
0-7
N
CH
0-15
Minimum
Data
Setup
Time
CH
0-3
CH
0-7
Minimum
Data Hold
Time
Clock
Qualifier
input connector)
REV
OCT
1982
P6451
AProbe~
._
._
.___
.
External
Input
(measured
at
external
20
ns or
less
.
20
ns
or
less
.
--
40
nns
or
less
.
General
Information--7D01
(SN
B020000
&
up)
HI Level
10
ns or
less
10
ns or
less
20
ns or
less
20
ns or
less
.
~~20
ns
or
less
.
23
ns or
less
.
~0
ns or
less
.
__
1
M2within
5%,
paralleled
by approx
.
5
pF
.
--12
V
or
less,
to
at
least
+12
V
.
+1
.4
V
within 0
.2
V
.
-
500
mV
plus
2%
of
threshold
voltage
p-p or
less,
centered
on
threshold
voltage
.
A
-60
^
V
or
less,
to at
least
threshold
voltage
plus
10
V
.
--60
V
or
less,
to at
least
+60
V
.
Setup
Time
LO
Level
10
ns or
less
10
A
ns
V
or
less
^^
_
_
Per
form
ance
Requirement
20
ns or
less
General
Information-71301
(SN
B020000
&
up)
Minimum
Data
Pulse
Width
(to
Ensure
Recording)
Crystal
Oscillator
Frequency
Sample
Intervals
TABLE
1-1
(CONT
.)
Electrical
Characteristics
Characteristic
CLOCK
AND
DATA
INPUTS
(CONT
.)
TRIGGER
INTERNAL
CLOCK
100
MHz
within
0 .005
MHz
.
10
ns to
5
ms/sample
in
1-2-5
sequence
.
1-4
REV
OCT
1982
External
Trig/Qualifier
Input
Threshold
/
+1
.4
V
within
0
.2
V
(TTL
Level)
.
Minimum
Pulse
Width
I
15
ns or
less
.
Max
Safe
Input
Voltage
1
-5
V
or
less,
to at
least
+10
V
.
Word
Recognizer
1
16
Data
inputs,
Probe
Qualifier,
and
External
Qualifier
.
Output
is
true
when
input
conditions
match
switch
settings
(H
I,
X,
LO)
.
Minimum
Input
Pulse
Width(Asynchronous
Mode)
Any
Single
Channel
I
10
ns or
less
.
Channels
0-3
I
15
ns or
less
.
Any
Other
Combination
1
20
ns or
less
.
Filter
.
.-
_
.
-
.
.__
._-
.
.-
._
Synchronous
Mode
Continuously
variable
to
at
least
300
ns
.
__
. . .
.__~L___i
.___
.
.____
.
I
Coincidence
of
matching
combination
and
an external clock
edge
must
occur
for
recognition
.
Minimum
Setup
Time
1
12
.5
ns or
less
.
Minimum
Hold
Time
I
8
.5
ns
or
less
.
TABLE
1-1
(CONT
.)
Electrical
Characteristics
TRIGGER
(CONT
.)
General
Information-71301
(SN
B020000
&
up)
Output
Impedance
(Rising
Edge)
Full
Display/First
Trigger
Mode
Selection
Full
Display
Mode
Position
Display
Length
in
X1
Mag
(With
Full
Data)
Raster
Shift
With
Format
Change
Display
Time
Range
Blanking
Time
Ch
0-3
Ch
0-7
Ch
0-15
REV
.
A,
MAR
197'7
DISPLAY
At
least
+1
.9
V
(0
.95
V
into
50-52
load)
.
+0
.1
V
or
less
(50
mV
into
50-52
load)
.
Selectable
by
internal
jumper,
P617
.
Produces
a
full
horizontal
display
.
Accepts
the
first
trigger
after
reset
.
Positions
magnified
display
within
graticule
area
.
Positions
magnified
display
within
graticule
area
.
Approximately
1
sec
to 10
sec,
followed
by
reset
;
or
infinite
hold
.
Resets
to
store
mode
when
button
is
pushed
.
1
group
of
4
traces
.
2
groups
of
4
traces
each
.
General
Information
,
-7D01
(SN
B020000
&
up)
Position
(Relative
to
Displayed
Trigger
Event)
10
ns/Sample
Serial
Data
Out
Channel
Sequence
:
C
H
0-3
CH
0-7
CH
0-15
Ch
a
racteristic
*All
logic
levels
are
ECL
levels
unless
otherwise
specified
.
TABLE
1-1
(CONT
.)
Electrical
Characteristics
Performance
Requirement
DISPLAY
(CONT
.)
Positions
intensified
zone
to
any
displayed
bit,
in incre-
ments
of
1
bit
or
16
bits
.
Top
right-hand
readout
shows
cursor
position
(in
sample
intervals)
relative
to
trigger
(e .g
.,
TRIG
±
xxx)
.
Bottom
readout
shows
the
logic state
of
each
displayed
channel
at
the cursor
(Hi
=
1
;
Lo
=
0)
.
Breaks
data
readout
into
3-bit
or
4-bit
bytes
.
In
16
channels
and
3-bit bytes,
the
left
hand
group
remains
4
bits
.
Intensifies
trigger
point
selected
by
data
position switch
.
5
Pin
4--Serial
data
from
memory,
non-inverted
.
2-3-4-5-6-7-0-1-2,
etc
.
2-3-12-13-14-15-8-9-10-11-4-5-6-7-0-1-2,
etc
.
REV
C,
JAN
1979
Data
Out
Connector
J120
*
(Cont
.)
External
Display
Clock
Input
Frequency
Range
I
Less than
1
Hz
to
at
least
2
MHz
.
C
h
_0_-3
Ch
^
0-7
._
Display/Store
Output
Store
Display
Trigger
Intensify
Output
Internal
Power
Supplies
-4
.8
Volt
Accuracy
(-I-20
,
to -+-30°
C)
measured
at
TP
112on
memory
board
.
---2
.0
Volt
Characteristic
*All
logic
levels
are
ECL
levels
unless
otherwise
specified
.
REV
OCT
1982
DATA
OUT
(CONT
.)
POWER
SUPPLY
General
Information--7D01
(SN
B020000
&
up)
TABLE
1-1
(CONT
.)
Electrical
Characteristics
Performance
Requirement
Pin
16--Falling
edge
indicates
end
of
Ch
2
;
rising
edge
indicates
end
of
Ch
3
.
Frame
occurs every 16th
sweep
Pin-14
Falling
edge
indicates
end
of
channel
;
rising
edge
indicates
beginning
of
channel
.
Pin
15
Hi
input
forces
reset
.
Hi
output
occurs
when
MANUAL
RESE
-
fis
pressed
.
Pin
3,
terminated
with
100
E2
to
--2
V
.
Pins
1,
2,
and
5 of
J120
are
connected
to pins
7, 8,
and
6,
respectively
of the
Signal Select
Jumper
.
There
are
5
signals
available
to
the
Signal Select
Jumper
.
Format
Output
I
Pins
1
and
2 of
Signal Select
Jumper
:
Pin 3 of the
Signal Select
Jumper
:
Pin
4
of
Signal Select
Jumper,
LO
=
intensified
trigger
point
on
display
.
Master
Reset
Output
I
Pin 5
of
Signal Select
Jumper,
HI
during
reset
.
Within
4.80
V
to -4
.975
V
.
Refer
to 7000-series
oscilloscope
performance
requirements
.
General
Information-71301
(SN
B020000
&
up)
Temperature
Operating
Storage
Altitude
Operating
Storage
Transportation
Characteristic
Characteristic
Weight
(Without
Accessories)
NOTE
DIMENSIONS
ARE
GIVEN
WITH
TOP
FIGURE
IN
INCHES
ANDBOTTOM
FIGURE
IN
CENTIMETERS
.
TABLE
1-2
Environmental
Characteristics
0
°
to
+40
°
C
.
-55
0
to
+75
0
C
.
To
15,000
feet
.
To
50,000
feet
.
TABLE
1-3
Physical Characteristics
Figure
1-1
.
71301
Dimensional
Drawing
.
Performance
Requirement
Qualified
under
National
Safe
Transit
Committee
Test
Procedure
1A,
Category
11
.
Description
Approximately
4
.4
Ibs
(2 .0
kg)
.
REV
.
A,
MAR
197'7
STANDARD
ACCESSORIES
For
more
information,
refer
to the
tabbed
Accessories
page
in
the
back
of
this
manual
.
General
Information-7D01
(SN
B020000
&
up)
1
ea
.
...................
.
. . .
Instruction
Manual
1
ea
.................
...
.
.
. .
Operator's
Manual
2 ea
....................
. .
P6451
ProbePackage
REV
.
A,
MAR
1977
INSTRUCTION
This
section
includes
a
description
of
the
71301
front-panel
controls,
connectors,
and
indicators
.
Also
included
is
detailed
operating information,
some
basic
application
procedures
and
a
functional
check
procedure
.
Refer
to
Section
1,
General
Information, for
a
glossary
of
terms
and
installation
instructions
.
FRONT-PANEL
CONTROLS,
CONNECTORS,
AND
INDICATORS
Refer
to Detailed
Operating
Information
for
a
discussion
of
the
auxiliary
functions
available
with
the
internal selectors,
The
location
and
function
of
the
front-panel
controls,
and
the
input
and
output
signals
available
through the Data
connectors,
and
indicators are
illustrated
in
Figure
2-1
.
Out
connector
.
AUXILIARYFUNCTIONS
Several
auxiliary
functions
can
be
selected
by
connectors
and
jumpers
located
inside
the
71301
.
A
25-pin
Data
Out
connector
is
also
located
inside
the
71301
to
provide
various
input
and
output
signals
for use
with
external
equipment
.
The
following information
describes
the
auxiliary
functions
with
procedures
for
making
the
appropriate
internal
connections
.
Display
Clock
Source
Selector
(P835)
Two-pin
jumper
which
determines
whether
the
71301
is
to
be
used
for
display only,
or
for
display
and
data
output
(serial
and
parallel
data
at
the
Data
Out
connector)
.
When
the
71301
is
used
for
data
displays,
P835
must
be
set
to
Internal
Display
Clock
(see
Fig
.
2-2)
.
When
the
71301
is
to be
used
for
display
and
data
output
(serial
and
parallel),
P835
must
be
set
to
External
Display
Clock
(see
Fig
.
2-2)
and
an
external
display
clock
signal
must
be
applied
to
pin
3
of
Data
Out
connector
J120
to
synchronize
the
data
out-
put
.
The
rate
per
bit
of
the
serial
and
parallel
output
data
is
determined by
the
rate
of
the
external
display
clock
signal
applied
to
pin
3
of
Data
Out
connector
J120
.
If
a
display
is
desired,
as
well
as
serial
and
parallel
data,
the
external
dis-
play
clock
signal
repetition
rate
must
be
approximately
2
microseconds
.
The
internal
display
clock
signal
is
not
available
as
an
output
.
Full
Display/First
Trigger
Selector
(P617)
DETAILED
OPERATING
INFOR
Two-pin jumper
which
determines
whether
data
is
displayed
at
the
first
acceptable
trigger
after
the
memory
has
addres-
sed
one
full
block
of
data,
or
whether
data
is
displayed
after
the
first
acceptable
trigger
.
TION
When
P617
is
set
to
Full
Display
(see
Fig
.
2-2),
the
memory
stores
one
complete
block
of
data
and
then
accepts
the
next
trigger
.
The
Full
Display
position
is
recommended
for
most
repetitive
signal
applications
.
If
a
trigger
is
expected
soon
after
a
reset
pulse,
or
if
the
wait
between
displays
at
slow sample
rates
is
objectionable,
P617
can
be
set
to
the
First
Trigger
position
(see
Fig
.
2-2)
.
Refer
to
Synchronous
and Asynchronous
Data
Sampling
for
more
information
.
Signal
Selector
(P300)
Internal
multi-pin
connector
P300
provides
5
signals
for
connection
to
3
outputs
on
Data
Out
connector
J120
.
Any
3
of
the
5
signals
can
be
used
for
external
use
.
Figure
2-3
shows
the
location
of
P300,
and
identifies
the
pin
assign-
ments
as
they
are
connected
when
shipped
from
the
factory
.
To
change
signal
outputs
at
J120,
move
the
jumper
connec-
tions
at
P300
(refer
to
Fig's
.
2-3
and
2-4)
.
FORMAT
OUTPUT
.
Two
outputs (P300
pins
1
and
2)
provide
ECL-level
outputs
which
indicate
the
channel
selected
by
the
front-panel
DATACHANNELS
switch
.
Table
2-1
shows
the
ECL
levels at
pins
1
and
2
of
P300
for
each
position
of
the
DATA
CHANNELS
switch
.
Section
2---7001
(SN
B020000
&
up)
TABLE
2-1
Operating
Instructions--70,
0
1
(SN
B020000
&
up)
2-2
EXT
CLOCK
POLARITY
Switch-Selects
the
active
edge of
the
external
clock
signal
applied
to
the
C
(clock)
input
of
the
Channel
0-7
Data
Input
connector
.
0
SAMPLE
INTERVAL
Switch-Selects
the
data
input
sample
rate
.
Sample
rates
from
5
milliseconds to
10 nanoseconds
are
provided
in
a
5-2-1
sequence
.
A
lamp behind
the
knob
skirt
blinks
when
the
sample
rate
is
too
fast
for
8-channel operation (10
nanosecond)
or
16-channel
(10
or
20
nanosecond)
sample
intervals
.
When
set
to
the
EXT
position,
the
C
(clock)
input
is
selected
.
The
SAMPLE
INTERVAL
lamp does not
blink
when
operating
in
the
EXT
position
.
Figure
2-1
.
Front
panel
controls,
connectors,
and
indicators
.
2206-3A
REV
B,
JAN
1979
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