Teledyne Lecroy PCI Express 5.0 M.2 M-Key Interposer User manual

Introduction
The Teledyne LeCroy PCI Express 5.0 M.2 M-Key Interposer CrossSync PHY Capable, which is used with Summit T5
Protocol Analyzers, enables PCIe bus traffic between a system board or tablet and a M.2 connector on a PCIe M.2 device
to be monitored, captured, and recorded for protocol analysis. The Gen5 M.2 Interposer (CrossSync PHY capable) will
support analysis for PCIe host interfaces such as SATA Express (AHCI/PCIe) and NVM Express (NVMe) at data rates from
2.5 GT/s up to 32.0 GT/s and link widths of up to x2 or up to x4.
The interposer supports side band signals such as PERST#, WAKE#, CLKREQ#, SMBus (SMBCLK, SMBDAT) and analog
probing for PCIe high speed serial signals as well as probing/monitoring for power rails and reference clock. The M.2
technology specification includes two connector definitions: Socket 2 and Socket 3. Socket 2 keyed as “B” allows for PCIe
x2 interface for SSDs, WWAN or other non-storage devices. Socket 3 keyed as “M” is strictly for high-performance storage,
offering x4 lanes of bandwidth in this form factor. In some cases a “B/M” keyed SSD will also be available and it is both a
Socket 2 and 3 type. A, “M” or a “B/M” keyed memory SSD can then be connected to a host based M connector which is
capable of supporting any of the devices mentioned above.
Teledyne LeCroy provides an interposer to use with M and B-M type memory modules. The interposer supports the 30mm,
42mm, 60mm, 80mm, and 110mm SSD lengths as well as 22mm and 30mm widths. The interposer can be used with
Summit T4 Analyzers using a conversion cable.
PCI Express Gen5 M.2 M-Key Interposer
PCI Express®5.0 M.2 M-Key Interposer
CrossSync PHY Capable 
User Manual and Quick Start Guide
Before Starting
Use this document for quick installation and setup. If you experience problems or
need more information, see the product manuals available at the Teledyne LeCroy
web site or in the Documents folder in the PCIe Protocol Suite installation.
1

• PCI Express 5.0 M.2 M-Key Interposer CrossSync
PHY Capable Carrier board
• Connector cable assembly 18 inches for
connection to host slot
• DC Power Adapter (+12V @ 3 Amps)
• Depending on configuration: SMA to BNC 3ft
Cable
• Extension bracket kit (metal brackets with clip)
supporting M.2 devices of 60, 80 and 110mm
devices (depending on purchased configuration
two more bracket sizes 30 and 42mm included)
• Thumbscrew and standoff
• User Manual and Quick Start Guide (this
document)
2
Interposer Cable Assembly Installation
If required, install a different extension bracket to the small PCB at the end of the 18" interposer cable. The extension
brackets are provided to allow the user to attach and secure the Teledyne LeCroy M.2 interposer cable on the host system
which usually supports different M.2 card form factors. Follow below instructions to install the extension brackets that will fit
your application.
Cable Assembly for Screw Attachment with 42mm PCB Configuration
The cable comes already with the Type 2260 bracket extension installed. To install a different bracket follow below
procedure. The Teledyne LeCroy M.2 Interposer Extension Bracket Kit contains the items listed below. The items are
shown in the figure below.
•Type 22110 Extension bracket
•Type 2280 Extension bracket
•Type 2260 Extension bracket.
•Screws to attach the Extension bracket to the interposer Cable Assembly
M2 Interposer Extension Bracket Kit
3
Components
The Teledyne LeCroy 5.0 M.2 M-Key Interposer CrossSync PHY Capable kit has the following components:

For this cable configuration screws are used to hold the bracket to the PC Board. The assembly process for swapping the
default Type 2260 bracket with the Type 2280 is described below (follow the same steps for the Type 22110 bracket).
1. First remove the two Phillips head screws, then remove the Type 2260 Extension bracket.
2. Place the Type 2280 Extension bracket aligned with the counter sink screw holes.
3. Make sure the text “Type 2280" on the bracket is facing the top of the PCB where the cables are attached.
4. Insert the screws and tighten them using a 1.4mm Phillips or flat blade screw driver.
5. The view from the top side of the PCB is shown below. The text “Type 2280" is clearly visible.
Attaching the Cables to the Interposer
1. Once the cable assembly has been completed (Method One or Method Two) the next step is to attach the cables to the
Interposer as shown below.
2. Connect the cable ends to the interposer pod. There is a power cable, a sideband signals cable and a high speed sig-
nals cable. These three cables have different connectors and are keyed. Be careful to install the connectors in the right
orientation (following labels) and do not force them. See diagram below.
Phillips head
screws
Warning! Attempting to use the board without the extension bracket and properly secured to the host will cause
damage to the plug-in card of the interposer cable and warranty will be voided.

Interposer DUT Standoff Installation
A flexible attachment M.2 standoff assembly is provided for the different types of DUTs supported which are 2230, 2242,
3042, 2260, 2280, and 22110. Move the M.2 standoff based on the DUT Type. The standoff will be attached to 2280
location by default. The DUT is secured by a thumbscrew on the top side and a standoff. This is to secure the DUT and not
the DUT bracket. (see drawings below).
Exploded View
Installed
Installed Side Profile
4

Hardware Installation
To use this interposer:
1. Set the SW2 DIP switches to the desired clock selection.
Note: “HOST_CLK” should be the default setting unless you are using an external clock reference source.
2. Move the stand off from the default position to the position required by the DUT.
3. Install the M.2 SSD device under test (DUT) into the connector on the interposer as shown (will fit 30 mm, 42mm,
60mm, 80mm and 110mm).
4. Connect the Summit Analyzer to the interposer using the high speed serial cables (If using Summit T54 use Gen5 Y
cable PE028UCA-X. If using Summit T54 with Gen5 Phy use Gen5 straight cable PE027UCA-X).
5. Connect the analyzer to a host machine using the USB port on the front panel of the Summit analyzer.
6. If not already done, install the PCIe Protocol Analysis on the host machine.
7. Connect 12V DC using the AC adapter supplied with the interposer. (Make sure that the AC adapter is powered on).
8. Power on the Analyzer and wait for it to be recognized by the application. Note: If prompted to update the firmware
please do that before proceeding.
9. Power on the host machine.
10. Launch the Teledyne LeCroy software application to monitor, record and view PCI Express traffic passing through the
M.2 Interposer.
11. Power on the system under test.
Note: Step 8, 9, and 10 are needed in this order for “Power On”traces.
Note: Use the link width control button SW1 to match the minimum physical lane width of the host and device.
PCI Express Gen5 M.2 MKey Interposer CrossSync Phy Interposer Interconnection Overview
Keyed paddle board
inserts in M.2 connector
12 V DC from power supply Upstream connection to oscilloscope
Reference clock probe connections
Summit T54 Gen5 Phy
Power rail probe connections
External clock inputs
Device under test (DUT) Compatible with
30x30, 30x42, 30x60, 30x80, 30x110 and
22x30, 22x42, 22x60, 22x80, 22x110
SSD carrier board
Sideband signal connections
Downstream connection to oscilloscope
PE028UCA-X Y Cable (Use with T54 Expanded Mode or Summit T516)
PE027UCA-X straight cable (Use with Summit T54 or Summit T516 MultiPort Mode)
5

Clock Configuration and Other Switch Settings
SW1: A pushbutton SW1 is used to turn off the terminations and remove all loads on the unused interposer receivers
depending on the maximum number of lanes to be analyzed. Press the pushbutton switch (SW3) to move to the next active
width as indicated by the LEDs (next to the switch on the interposer.
SW2: The source for the reference clock used by the analyzer to record PCI Express traffic is configurable according to
below table for SW2. Make sure clock source in Recording Options in the PCIe Protocol Analysis application is set to
External.
Note: Factory default is host clock: SW2.1 = OFF, SW2.2 = OFF, SW2.3 = OFF, SW2.4 = ON
Note: Other switch configurations (other than those shown in the table above) are invalid.
Note: External input clocks can be HCSL, LVPECL, LVDS or any single ended standard input voltage amplitude not to
exceed 800mV.
SW3: This switch connects the DUT power indication LEDs to the bus power. In some systems with Hot-Plug management
the Power Indication LEDs on the interposer may prevent the host system from turning ON bus power to the device, if this
happens disconnect the LEDs using SW3 to allow proper bus power operation.
DUT Power LED Status on Interposer
SW2: Clock Source Control
SW2.1 SW2.2 SW2.3 SW2.4
Reference Clock Source
for Downstream Analysis
Reference Clock Source
for Upstream Analysis
OFF OFF OFF ON Host System PCIe Slot Host System PCIe Slot
OFF ON OFF OFF US_CLK from MMCX connector Host System PCIe Slot
OFF OFF ON OFF Host System PCIe Slot DS_CLK from MMCX connector
ON OFF OFF OFF US_CLK from MMCX connector DS_CLK from MMCX connector
SW3: DUT Power Status LED
ON LED Connected (Default)
OFF LED Disconnected
6
SW3 DUT Power LED
SW1 Active Link Width Select

Recording Traffic
We are continuously improving and releasing new products. For new interposers to operate optimally always check
Teledyne LeCroy website for the latest version of the PCIe Protocol Analysis Software.
After you have set up the hardware and software, you can record traffic.
For instructions on setting up and implementing a recording, please refer to the PCI Express Protocol Analysis Summit T5
Gen5 Analyzer User Manual.
Side Band Test Point Header J6207
Connector Pin Number Signal Name Connector Pin Number Signal Name
1 Ground 17 VIO_CFG_HDR
2 No Connection 18 No Connection
3 CLK_32KHZ_SUSCLK_HDR 19 PERST#IN_HDR
4 No Connection 20 No Connection
5 GPIO_9_DAS_DSS_N_LED1_N_HDR 21 SMCLK_HDR
6 No Connection 22 No Connection
7 ALERT#IN_HDR 23 DEVSLP_DGND_HDR
8 No Connection 24 No Connection
9 PEDET_HDR 25 WAKE#_HTR
10 No Connection 26 No Connection
11 PWRDIS_HDR 27 CLKREQ#IN_HDR
12 No Connection 28 No Connection
13 PLN#_HDR 29 SMDAT_HDR
14 No Connection 30 No Connection
15 PLA_S3#_HDR 31 Ground
16 No Connection
7

CrossSync PHY
The Teledyne LeCroy PCI Express 5.0 M.2 M-Key Interposer CrossSync PHY Capable includes CrossSync PHY capability,
enabling:
•Easy signal access to sideband signals, power rail and refclk probing points
•Preinstalled connections on data lanes for Teledyne LeCroy DH Series high-bandwidth differential oscilloscope
probes (optional)
•Time-synchronization and integrated cross-analysis between PETracer protocol analysis software and MAUI
oscilloscope software (optional)
Signal Name PE222UIA-X PE222UIA-X-1PHY PE222UIA-X-2PHY PE222UIA-X-4PHY
Pin Headers
CLK_32KHZ SUSCLK X X X X
DAS/DSS LED_1# X X X X
ALERT#IN X X X X
PEDET X X X X
PWRDIS X X X X
PLN# X X X X
PLA_S3# X X X X
VIO_CFG X X X X
PERST#IN X X X X
SMB_CLK X X X X
DEVSLP X X X X
WAKE# X X X X
CLKREQ#IN X X X X
SMB_DATA X X X X
UMC Connectors
Refclk X X X X
3.3V rail voltage X X X X
3.3V rail current X X X X
DH Series Differential Oscilloscope Probe Connections (Optional)
L0 Upstream X X X
L0 Downstream X X X
L1 Upstream XX
L1 Downstream XX
L2 Upstream X
L2 Downstream X
L3 Upstream X
L3 Downstream X
8

Recommended Oscilloscope Probes
Sideband signals may be probed with a standard passive or active high-impedance oscilloscope probe.
Rail voltage and current points are best probed with an RP4030 voltage rail probe, but connection directly to a coaxial
oscilloscope input is possible.
Reference clock probing points can be connected directly to a 50? oscilloscope input.
High-speed signal probing points are designed exclusively for Teledyne LeCroy DH series high-bandwidth differential
probes.
Oscilloscope Software Options
The Oscilloscope Software options allow you to enable CrossSync PHY functionality on installed CrossSync software.
Recommended Oscilloscopes
CrossSync PHY is compatible with all LabMaster 10 Zi and WaveMaster 8 Zi series oscilloscopes. Below are some
recommendations for example test configurations.
PCI Express 3.0 - CrossSync PHY and Compliance Test Capable
PCI Express 4.0 - CrossSync PHY and Compliance Test Capable
Product Description Product Code
High-speed Data Signals
8 GHz differential probe with ProLink interface DH08-PL
13 GHz differential probe with ProLink interface DH13-PL
16 GHz differential probe with ProLink interface DH16-PL
20 GHz differential probe with ProLink interface DH20-PL
25 GHz differential probe with 2.92 mm interface DH25-2.92MM
30 GHz differential probe with 2.92 mm interface DH30-2.92MM
Rail Voltage/current Points
Voltage Rail Probe 4 GHz bandwidth, 1.2x attenuation, ±30V offset, ±800mV RP4030
Product Description Product Code
CrossSync PHY option for LabMaster 10 Zi - sync oscilloscope with PCIe Protocol Analyzer hardware LM10Zi-CrossSyncPHY
CrossSync PHY option for WaveMaster 8 Zi - sync oscilloscope with PCIe Protocol Analyzer hardware WM8Zi-CrossSyncPHY
Product Description Product Code
13 GHz (or higher), 40 GS/s, 4ch, 64 Mpts/Ch Serial Data Analyzer
with 6.5 Gb/s Serial Trigger, 8b/10b and 64b/66b decode. SDA 813Zi-B
Product Description Product Code
25 GHz (or higher), 80 GS/s, 4 Ch, 32 Mpts/Ch LabMaster 10 Zi Acquisition Module LabMaster 10-25Zi-A
LabMaster Master Control Module LabMaster MCM-Zi-A

Enabling CrossSync PHY Capability
Use the following procedure to enable CrossSync PHY for your the interposer:
1. Locate any miscellaneous signals to be probed.
Top View
2. Locate the PCIe Express pairs probe points, as located on the left and right sides of the interposer.
Left Side View
Right Side View
Buffered Refclk
Copy (UMC)
Pin Header for
Sideband Signals
1.8V Rail Voltage
(UMC)
1.8V Rail Current
shunt (1V=1A)
(UMC)
Passive Probe
Grounds
3.3V Rail Voltage
(UMC)
3.3V Rail Current
shunt (1V=1A)
(UMC)
Upstream Signal Probe Points (Optional)
Downstream Signal Probe Points (Optional)