Terasic Agilex 7 FPGA Starter Kit User manual

Agilex 7 FPGA
Starter Kit
User Manual
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1.1. Vu0Q

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Starter Kit
User Manual
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Contents
Chapter 1 Overview..................................................................................4
1.1 General Description ..............................................................................4
1.2 Key Features.........................................................................................5
1.3. Block Diagram.......................................................................................6
1.4. Board Power On....................................................................................6
1.5. Install Drivers for USB port....................................................................9
2.1. Board Protection .................................................................................10
2.2. Mechanical Specifications...................................................................11
Chapter 2 Board Component ................................................................12
2.1 Board Overview...................................................................................12
2.2 Configuration.......................................................................................13
2.3 Status and Setup Components ...........................................................17
2.4 Reset Devices.....................................................................................24
2.5 General User Input/Output..................................................................25
2.6 Clock Circuit........................................................................................28
2.7 DDR4 SO-DIMM .................................................................................31

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2.8 QSFP28 Port.......................................................................................43
2.9 PCI Express........................................................................................46
2.10 FMC+ Connector.................................................................................49
2.11 USB to UART......................................................................................62
2.12 Micro SD Card Socket.........................................................................64
2.13 Gigabit Ethernet..................................................................................65
2.14 System Status Interface......................................................................67
Chapter 3 Dashboard GUI......................................................................69
3.1 Driver Installed on Host.......................................................................69
3.2 Run Dashboard GUI............................................................................72
Chapter 4 Additional Information .........................................................84
4.1 Getting Help........................................................................................84

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Chapter 1
Overview
his chapter provides an overview of the Terasic Agilex 7 FPGA Starter Kit
(A7SK) and installation guide.
1.1 General Description
The Terasic Agilex 7 FPGA Starter Kit takes advantage of the latest Intel Agilex™ 7
FPGA F-Series devices with 2x F-Tile and from 600K to 2.7M logic elements options,
offering 50% higher fabric performance and 40% lower power consumption than
equivalent Stratix® 10 devices. (Note: Standard kits are built with 2.7M LEs version.
Other device options are available for customized requests.)
Combining PCI Express 4.0 x8, one 100G QSFP-28 connector, and offering up to
16GB of DDR4, the Terasic Agilex 7 FPGA Starter Kit provides optimal acceleration
and throughput for communications, high-performance computing, data center, and
other compute-intensive applications. In addition, the on-board FMC+ connector
makes the board extensible and can work with various daughter cards, such as
Terasic’s HDMI-FMC, XTS-FMC, and HDMI 2.1 FMC daughter card.
The Agilex 7 FPGAStarter Kit also supports the Intel® oneAPI and Intel® Open FPGA
Stack (OFS). Developers can customize their own unique acceleration workloads
effortlessly by leveraging the Intel Agilex™ FPGA on the Terasic Agilex 7 FPGA
Starter Kit.
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1.2 Key Features
The following hardware is implemented on the Agilex 7 FPGAStarter Kit board:
Intel® Agilex™ F-Series
AGFB027R24C2E2VR2
2.7M logic elements (LEs)
287 Mb On-chip RAM (M20K and MLAB)
17,056 18-bit x 19-bit multipliers
4,510 Variable-precision DSP blocks
FPGA Configuration
On-Board USB Blaster II (UB2) for FPGA programming and Debug
AS x4 (QSPI Flash 2048 or 1024 Gbit)
FPGA Fabric
PCIe Gen4 x8
HDMI 2.1 Output Port
DDR4-A: DDR4 SO-DIMM Socket shared with HPS,shipping with 8GB
ECC SO-DIMM
DDR4-B: On-board components 8GB DDR4 with x72 data bus, suppor
t ECC (Note )
One FMC+ connectors with 16 transceivers, supporting VADJ 1.2V
One QSFP28 Port for 100/40/25/10 GbE network interface
2x5 Timing Expansion Header
User LED x2, Button x2, DIP Switch x2
HPS(Hard Processor System) Fabric
Quad-core 64 bit ARM Cortex-A53 MPCore* processor
MicroSD Socket
DDR4-A: DDR4 SO-DIMM Socket shared with FPGA
Gigabit Ethernet PHY + RJ45

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UART to USB Port
LED x1, Button x1, Cold Reset Button
Board Management System
Power Monitor
Temperature Monitor
Auto fan Control
1.3. Block Diagram
Figure 1-1 shows the block diagram of the Agilex 7 FPGA Starter Kit board. To
provide maximum flexibility for the users, all key components are connected to the
Agilex™ FPGA device. Thus, users can configure the FPGA to implement any system
design.
Figure 1-1 Block diagram of the Agilex 7 FPGA Starter Kit board
1.4. Board Power On
The Agilex 7 FPGA Starter Kit board can be used in stand-alone or be installed to the

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Host through PCIe slot. This section will introduce how to power on the board and the
information that user should notice in these two modes.
Stand-alone Mode
When the Agilex 7 FPGAStarter Kit board is used in stand-alone mode, users can use
the 12V ATX power provided in the kit to connect to the 8-pin 12V ATX power
connector (See Figure 1-2) of the Agilex 7 FPGA Starter Kit board. To power up the
board, user need to turn the power switch SW2 to “ON”position.
Figure 1-2 Board Power Control Switch
Install to Host
When the Agilex 7 FPGAStarter Kit is installed on the Host via PCIe slot. Although the
Host can provide power to Agilex 7 FPGA Starter Kit board via PCIe slot, but Terasic
strongly recommends that users connect an external power (through the 2x4 ATX

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power connector) to the board. This can prevent the power provided from Host unable
to meet the power requirement of Agilex 7 FPGAStarter Kit. If the power supply to the
board is insufficient, it may cause some components to be abnormal.
In order to avoid insufficient power supply to the board, there is a force external power
switch (SW1) on the board (See Figure 1-4). The SW1 is default set as ON. When
install the board on the PCIe slot in the PC, users must connect the 2x4 pin 12V DC
external power connector to the board, otherwise the board will not be power on. This
restriction is designed to avoid FPGA damage due to insufficient power. Users can set
it as OFF if the FPGA utilization rate is low and PCIe edge power source is sufficient.
Figure 1-3 Plug external power on the board

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Figure 1-4 Force external power switch
1.5. Install Drivers for USB port
The Micro USB connector on the board provides 3 functions:
USB blaster II circuit
HPS USB to UART
MAX10 USB to UART
The first one is USB blaster II circult, which provides the JTAG interface between
host and FPGA board.The second function is the serial communication function of
HPS Fabric, which allows Host to communicate or debug with HPS Fabric. The last
one is the UART function for board system monitoring. It allows user to monitor the
staus on the board such as temperature and fan speed in real time.These three
functions are all connected to the Micro USB connector through the USB hub. The
user only needs to connect the host with a USB cable to the board to realize these

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three functions.
At the same time, some drivers need to be installed on the host to use these functions.
Users can refer to the following steps.
1. Please refer to this link to install USB Blaster II driver : Terasic Wiki
2. For the UART driver of HPS and system monitoring, please refer to section 3.1.
Figure 1-5 The Micro USB port
2.1. Board Protection
The temperature of Agilex 7 FPGA Starter Kit board will have a lot to do with the
user's design code, chassis, and ambient temperature. When using Agilex 7 FPGA
Starter Kit board in the server. Customers should pay attention to whether the
temperature of Agilex 7 FPGA Starter Kit board is too high to avoid abnormal work for
user’s design or even damage to the board.
The Dashbaord_gui software (see chapter 4 of this user manual) is provided in the
system CD to allow users to monitor the temperature status of the board. A
temperature monitor IP (see section 5.4 in the user manual) is also provided so that
the user can directly monitor the temperature status in the Agilex FPGA.

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If the board temperature is too high, it is recommended that customers can switch the
PCIe slot position in the server chassis or increasing the fan strength in the chassis,
or replace the chassis to a big space, or reduce the ambient temperature to improve
cooling system.
In addition, the efficiency of the Agilex 7 FPGA Starter Kit cooling system will
decrease with the aging of dust and fans, so customers should re-evaluate the cooling
efficiency regularly.
2.2. Mechanical Specifications
Figure 1-6 shows the Mechanical Layout of Agilex 7 FPGA Starter Kit. The unit of the
Mechanical Layout is millimeter (mm).
Figure 1-6 Mechanical layout

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Chapter 2
Board Component
his chapter introduces all the important components on the Agilex 7 FPGA
Starter Kit.
2.1 Board Overview
Figure 2-1 and Figure 2-2 is the top and bottom view of the Agilex 7 FPGA Starter Kit
development board. It depicts the layout of the board and indicates the location of the
connectors and key components. Users can refer to this figure for relative location of
the connectors and key components.
Figure 2-1 FPGA Board (Top)
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Figure 2-2 FPGA Board (Bottom)
2.2 Configuration
This section describes the configuration mode for Agilex SoC FPGA available on the
ApolloAgilex. The peripheral circuits and usage scenarios for each mode will be listed.
As shown in Figure 2-3, the mode select pin of the FPGA on theAgilex 7 FPGA Starter
Kit has been set to Active Serial (AS) Fast mode using resistors. Thus, the Agilex 7
FPGA Starter Kit supports the following configuration modes:
JTAG Mode (Configure the FPGA using the on-board USB Blaster II,
MSEL[2:0] = 3’b111).
Active Serial Fast mode (MSEL[2:0] = 3’b001)
Users can use these modes to configure the FPGAor HPS (Hardware Process System)
fabric in the Agilex SoC FPGA and make the FPGA to run the user's logic or boot the
HPS to run the OS.
Below we will introduce more detailed information of AS mode, as well as other
configuration information.

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Figure 2-3 The MSEL pin setting
Active Serial (Fast) mode
In AS mode, the FPGA's configuration file is stored in the QSPI flash. The Secure
Device Manager (SDM) in Agilex SoC FPGA is responsible for the entire AS mode
process and interface. The SDM will load the initial configuration firmware from the
QSPI flash to configure the FPGA including FPGA I / O and core configuration. HPS
part of the boot can also be completed in this mode. Figure 2-4 shows the architecture
of the AS mode of theAgilex 7 FPGA Starter Kit.

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Figure 2-4 AS mode for the Agilex 7 FPGA Starter Kit
For more information on the configuration of Agilex SoC FPGAs, please refer to the file:
Intel Agilex Configuration User Guide
SoC FPGA boot
The boot process for Agilex SoC FPGA can be divided into two different methods:
FPGA Configuration First Mode
HPS Boot First Mode
The difference between the two methods is the initial difference between HPS and
FPGA fabric after powering on. More details can be found in the user documentation:
Intel® Agilex™ SoC FPGA Boot User Guide.
The factory setting of the SoC boot of the Agilex 7 FPGA Starter Kit is the FPGA
Configuration First Mode. The architecture is shown in the Figure 2-5. Two storage
mediums are used. The system needs QSPI flash on Apollo Agilex as SDM flash for
booting.

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Figure 2-5 FPGA Configuration First Dual SDM and HPS Flash
The QSPI flash memory has the following boot data for the first part of the SoC FPGA
configuration:
Configuration firmware for the SDM
FPGA I/O and HPS external memory interface (EMIF) I/O configuration data
FPGA core configuration data
HPS First-Stage Boot Loader(FSBL) code and FSBL hardware handoff binary
data
Meanwhile, Terasic provides the micro SD card with built-in image data as HPS flash,
which is used for HPS boot in the later part. The micro SD card stores the following
data:
Second-Stage Boot Loader(SSBL)
Kernel Image and Device Tree Blob(DTB)
Operating System
The factory SoC boot process ofApollo Agilex is summarized as follows:
When the Agilex 7 FPGA Starter Kit is powered on, the SDM will read the configuration
firmware and complete SDM initial form the QSPI flash according to the MSEL pin
setting. Then, the SDM will configure the FPGA I/O and core (full configuration).

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After the FPGA is first configured, SDM continues to load the FSBL(First-Stage Boot
Loader) from the QSPI flash and transfer it to the HPS on-chip RAM, and releases the
HPS reset to let the HPS start using the FSBL hardware handoff file to setup the clocks,
HPS dedicated I/Os, and peripherals.
The FSBL then loads the SSBL(Second-Stage Boot Loader) from the Micro SD Card
into HPS SDRAM and passes the control to the SSBL. The SSBL enables more
advanced peripherals and loads OS into SDRAM.
Finally, the OS boots and applications are scheduled for runtime launch.
JTAG Programming
The JTAG interface of the Apollo Agilex is mainly implemented by the USB Blaster II
circuit on the board. For programming by on-board USB Blaster II, the following
procedures show how to download a configuration bit stream into the Agilex SoC
FPGA:
Make sure that power is provided to the FPGA board
Connect your PC to the FPGA board using a micro-USB cable and make
sure the USB Blaster II driver is installed on the PC.
Launch Quartus Prime programmer and make sure the USB Blaster II is
detected.
In Quartus Prime Programmer, add the configuration bit stream file (.sof),
check the associated “Program/Configure” item, and click “Start” to start
FPGA programming.
2.3 Status and Setup Components
Status LED
The FPGA Board development board includes board-specific status LEDs to indicate
board status. Please refer to Figure 2-6 and Table 2-1 for the description of the LED
indicator.

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Figure 2-6 Position of the status LED
Table 2-1 Status LED
Board
Reference
LED Name
Description
D8
12-V Power
Illuminates when 12-V power is active.
D7
3.3-V Power
Illuminates when 3.3-V power is active.
D1
FAN_ALERT_n
Illuminates when the fan is abnormal, such
as when the fan speed is different from
expected
D6
POWER_LEDG
Illuminates when the 3.3V power good and
power sequence process finished. (*1)
D5
POWER_LEDR
Illuminates when the 3.3V power abnormal
or power sequence process failed. (*1)
D2
JTAG_RX
Illuminates when the USB Blaster II circuit is
transmitting data

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D4
JTAG_TX
Illuminates when the USB Blaster II circuit is
receiving data
Setup PCI Express Control DIP switch
The PCI Express Control DIP switch (SW8) is provided to enable or disable different
configurations of the PCIe Connector (See Figure 2-7). Table 2-2 lists the switch
controls and description.
Figure 2-7 Position of the PCIe mode switch
Table 2-2 SW8 PCIe Control DIP Switch
Board
Reference
Signal Name
Description
Default
SW4.1
PCIE_PRSNT2n_x1
On : Enable x1 presence detect
Off: Disable x1 presence detect
Off
SW4.2
PCIE_PRSNT2n_x4
On : Enable x4 presence detect
Off: Disable x4 presence detect
Off

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SW4.3
PCIE_PRSNT2n_x8
On : Enable x8 presence detect
Off: Disable x8 presence detect
Off
SW4.4
N.C
--
--
Setup Configure Mode
The SW7and SW6slide switches (see Figure 2-8) are used to specify the
configuration mode of the FPGA. As currently only AS Fast and JTAG mode are
supported.
Figure 2-8 Position of slide switches SW6 and SW7 for Configuration Mode
Table 2-3 MSEL Settings for supported configuration Scheme of the board
FPGA Configuration
Mode
MSEL2
MSEL1
MSEL0
AS Fast (Default)
0
0
1