Texas Instruments TLC5916 User manual

. . .
VLED
GND
SDO
R-EXT
VDD
LE
CLK
SDI
LE
CLK
OE OE
SDI
Controller
OUT0
. . .
3.0V to 5.5V
OUT1
OUT6
OUT7
TLC5917
To Controller if Error
Detection Used
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TLC5916 , TLC5917
SLVS695D –JUNE 2007–REVISED JANUARY 2015
TLC591x 8-Channel Constant-Current LED Sink Drivers
1 Features 3 Description
The TLC591x Constant-Current LED Sink Drivers are
1• Eight Constant-Current Output Channels designed to work alone or cascaded. Since each
• Output Current Adjusted Through Single External output is independently controlled, they can be
Resistor programmed to be on or off by the user. The high
• Constant Output Current Range: 3-mA to 120-mA LED voltage (VLED) allows for the use of a single
LED per output or multiple LEDs on a single string.
per Channel With independently controlled outputs supplied with
• Constant Output Current Invariant to Load Voltage constant current, the LEDs can be combined in
Change parallel to create higher currents on a single string.
• Open Load, Short Load and Overtemperature The constant sink current for all channels is set
Detection through a single external resistor. This allows
different LED drivers in the same application to sink
• 256-Step Programmable Global Current Gain various currents which provides optional
• Excellent Output Current Accuracy: implementation of multi-color LEDs. An additional
– Between Channels: < ±3% (Maximum) advantage of the independent outputs is the ability to
– Between ICs: < ±6% (Maximum) leave unused channels floating. The flexibility of the
TLC591x LED drivers is ideal for applications such as
• Fast Response of Output Current (but not limited to): 7-segment displays, scrolling
• 30-MHz Clock Frequency single color displays, gaming machines, white goods,
• Schmitt-Trigger Input video billboards and video panels.
• 3.3-V or 5-V Supply Voltage Device Information(1)
• Maximum LED Voltage 20-V PART NUMBER PACKAGE BODY SIZE (NOM)
• Thermal Shutdown for Overtemperature SOIC (16) 9.90 mm × 3.91 mm
Protection TLC5916 PDIP (16) 19.30 mm × 6.35 mm
TSSOP (16) 5.00 mm × 4.40 mm
2 Applications SOIC (16) 9.90 mm × 3.91 mm
• General LED Lighting Applications TLC5917 PDIP (16) 19.30 mm × 6.35 mm
• LED Display Systems TSSOP (16) 5.00 mm × 4.40 mm
• LED Signage (1) For all available packages, see the orderable addendum at
• Automotive LED Lighting the end of the datasheet.
• White Goods
• Gaming Machines/Entertainment
Single Implementation of TLC5916 / TLC5917 Device
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC5916 , TLC5917
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Table of Contents
1 Features.................................................................. 19 Detailed Description............................................ 13
9.1 Overview................................................................. 13
2 Applications ........................................................... 19.2 Functional Block Diagram....................................... 14
3 Description............................................................. 19.3 Feature Description................................................. 14
4 Revision History..................................................... 29.4 Device Functional Modes........................................ 16
5 Device Comparison Table..................................... 310 Application and Implementation........................ 21
6 Pin Configuration and Functions......................... 310.1 Application Information.......................................... 21
7 Specifications......................................................... 410.2 Typical Application................................................ 24
7.1 Absolute Maximum Ratings ...................................... 411 Power Supply Recommendations ..................... 27
7.2 ESD Ratings.............................................................. 412 Layout................................................................... 27
7.3 Recommended Operating Conditions....................... 412.1 Layout Guidelines ................................................. 27
7.4 Thermal Information.................................................. 412.2 Layout Example .................................................... 27
7.5 Electrical Characteristics: VDD = 3 V......................... 513 Device and Documentation Support ................. 29
7.6 Electrical Characteristics: VDD = 5.5 V...................... 613.1 Related Links ........................................................ 29
7.7 Switching Characteristics: VDD = 3 V........................ 713.2 Trademarks........................................................... 29
7.8 Switching Characteristics: VDD = 5.5 V..................... 813.3 Electrostatic Discharge Caution............................ 29
7.9 Timing Requirements................................................ 913.4 Glossary................................................................ 29
7.10 Typical Characteristics............................................ 914 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 10 Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2011) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (February 2011) to Revision C Page
• Replaced the Power Dissipation and Thermal Impedance table with the Thermal Information tables.................................. 4
Changes from Revision A (November 2010) to Revision B Page
• Added Maximum LED Voltage 20-V to Features. .................................................................................................................. 1
• Added Abstract section........................................................................................................................................................... 1
• Changed resistor value in Single Implementation diagram from 840Ωto 720Ω.................................................................. 13
• Changed Default Relationship Curve to reflect correct data. .............................................................................................. 21
• Changed resistor value in Cascading Implementation diagram from 840Ωto 720Ω........................................................... 22
• Changed resistor value in Single Implementation diagram from 840Ωto 720Ω.................................................................. 24
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SDI
CLK
LE(ED1)
OUT0
OUT1
OUT2
OUT3
VDD
R-EXT
SDO
OE(ED2)
OUT7
OUT6
OUT5
OUT4
D, N, OR PW PACKAGE
(TOP VIEW)
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5 Device Comparison Table
OVERTEMPERATURE OPEN-LOAD SHORT TO GND SHORT TO VLED
DEVICE(1) DETECTION DETECTION DETECTION DETECTION
TLC5916 X X X —
TLC5917 X X X X
(1) The device has one single error register for all these conditions (one error bit per channel).
6 Pin Configuration and Functions
16-PIN
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CLK 3 I Clock input for data shift on rising edge
GND 1 – Ground for control logic and current sink
Data strobe input
Serial data is transferred to the respective latch when LE(ED1) is high. The data is latched
LE(ED1) 4 I when LE(ED1) goes low. Also, a control signal input for an Error Detection Mode and Current
Adjust Mode (see Timing Diagram). LE(ED1) has an internal pulldown.
Output enable. When OE(ED2) is active (low), the output drivers are enabled; when
OE(ED2) is high, all output drivers are turned OFF (blanked). Also, a control signal input for
OE(ED2) 13 I an Error Detection Mode and Current Adjust Mode (see Figure 11). OE(ED2) has an internal
pullup.
OUT0 to OUT7 5 to 12 O Constant-current outputs
R-EXT 15 I External Resistor - Connect an external resistor to ground to set the current for all outputs
SDI 2 I Serial-data input to the Shift register
SDO 14 O Serial-data output to the following SDI of next driver IC or to the microcontroller
VDD 16 I Supply voltage
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage 0 7 V
VIInput voltage –0.4 VDD + 0.4 V
VOOutput voltage –0.5 20 V
fclk Clock frequency 25 MHz
IOUT Output current 120 mA
IGND GND terminal current 960 mA
TAOperating free-air temperature –40 125 °C
TJOperating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN MAX UNIT
VDD Supply voltage 3 5.5 V
VOSupply voltage to output pins OUT0–OUT7 20 V
VO≥0.6 V 3
IOOutput current DC test circuit mA
VO≥1 V 120
IOH High-level output current source SDO shorted to GND –1 mA
IOL Low-level output current sink SDO shorted to VCC 1 mA
VIH High-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0.7 × VDD VDD V
VIL Low-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0 0.3 × VDD V
7.4 Thermal Information TLC5916 TLC5917
THERMAL METRIC(1) 16 PINS 16 PINS UNIT
D N PW D N PW
RθJA Junction-to-ambient thermal resistance 87.4 51.8 113.9 87.4 51.8 114.8
RθJC(top) Junction-to-case (top) thermal resistance 48.1 39.1 35.2 48.1 39.1 35.9
RθJB Junction-to-board thermal resistance 44.4 31.8 59.2 44.4 31.8 59.8 °C/W
ψJT Junction-to-top characterization parameter 12.5 23.9 1.3 12.5 23.9 1.3
ψJB Junction-to-board characterization parameter 44.2 31.7 58.5 44.2 31.7 59.2
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — — —
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics: VDD = 3 V
VDD = 3 V, TJ= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VDD Input voltage 3 5.5 V
VOSupply voltage to the output pins 20 V
VO≥0.6 V 3
IOOutput current mA
VO≥1 V 120
IOH High-level output current, source –1 mA
IOL Low-level output current, sink 1 mA
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD V
TJ= 25°C 0.5
Ileak Output leakage current VOH = 17 V μA
TJ= 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
VOUT = 0.6 V, Rext = 720 Ω,
Output current 1 26 mA
CG = 0.992
IOL = 26 mA, VO= 0.6 V, Rext = 720 Ω,
IO(1) Output current error, die-die ±3% ±6%
TJ= 25°C
Output current skew, channel-to- IOL = 26 mA, VO= 0.6 V, Rext = 720 Ω,±1.5% ±3%
channel TJ= 25°C
Output current 2 VO= 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
IOL = 52 mA, VO= 0.8 V, Rext = 360 Ω,
Output current error, die-die ±2% ±6%
IO(2) TJ= 25°C
Output current skew, channel-to- IOL = 52 mA, VO= 0.8 V, Rext = 360 Ω,±1.5% ±3%
channel TJ= 25°C
VO= 1 V to 3 V, IO= 26 mA ±0.1
IOUT vs Output current vs %/V
VDD = 3.0 V to 5.5 V,
VOUT output voltage regulation ±1
IO= 26 mA/120 mA
Pullup resistance OE(ED2) 500 kΩ
Pulldown resistance LE(ED1) 500 kΩ
Tsd Overtemperature shutdown(2) 150 175 200 °C
Thys Restart temperature hysteresis(2) 15 °C
Threshold current for open error 0.5 ×
IOUT,Th IOUT,target = 3 mA to 120 mA
detection Itarget %
Trigger threshold voltage for
VOUT,TTh short-error detection IOUT,target = 3 mA to 120 mA 2.5 2.7 3.1 V
(TLC5917 only)
Return threshold voltage for
VOUT, RTh short-error detection IOUT,target = 3 mA to 120 mA 2.2 V
(TLC5917 only) Rext = Open 5 10
Rext = 720 Ω8 14
IDD Supply current mA
Rext = 360 Ω11 18
Rext = 180 Ω16 22
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) Specified by design.
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7.6 Electrical Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VDD Input voltage 3 5.5 V
VOSupply voltage to the output pins 20 V
VO≥0.6 V 3
IOOutput current mA
VO≥1 V 120
IOH High-level output current, source –1 mA
IOL Low-level output current, sink 1 mA
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD V
TJ= 25°C 0.5
Ileak Output leakage current VOH = 17 V μA
TJ= 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
VOUT = 0.6 V, Rext = 720 Ω,
Output current 1 26 mA
CG = 0.992
IOL = 26 mA, VO= 0.6 V, Rext = 720 Ω,
IO(1) Output current error, die-die ±3% ±6%
TJ= 25°C
Output current skew, channel-to- IOL = 26 mA, VO= 0.6 V, Rext = 720 Ω,±1.5% ±3%
channel TJ= 25°C
Output current 2 VO= 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
IOL = 52 mA, VO= 0.8 V, Rext = 360 Ω,
Output current error, die-die ±2% ±6%
IO(2) TJ= 25°C
Output current skew, channel-to- IOL = 52 mA, VO= 0.8 V, Rext = 360 Ω,±1.5% ±3%
channel TJ= 25°C
VO= 1 V to 3 V , IO= 26 mA ±0.1
IOUT vs Output current vs %/V
VDD = 3.0 V to 5.5 V,
VOUT output voltage regulation ±1
IO= 26 mA/120 mA
Pullup resistance OE(ED2), 500 kΩ
Pulldown resistance LE(ED1), 500 kΩ
Tsd Overtemperature shutdown(2) 150 175 200 °C
Thys Restart temperature hysteresis(2) 15 °C
Threshold current for open error 0.5 ×
IOUT,Th IOUT,target = 3 mA to 120 mA
detection Itarget%
Trigger threshold voltage for
VOUT,TTh short-error detection IOUT,target = 3 mA to 120 mA 2.5 2.7 3.1 V
(TLC5917 only)
Return threshold voltage for
VOUT, RTh short-error detection IOUT,target = 3 mA to 120 mA 2.2 V
(TLC5917 only) Rext = Open 6 10
Rext = 720 Ω11 14
IDD Supply current mA
Rext = 360 Ω13 18
Rext = 180 Ω19 24
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) Specified by design.
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7.7 Switching Characteristics: VDD = 3 V
VDD = 3 V, TJ= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn 40 65 95 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 40 65 95 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 40 65 95 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 12 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 300 365 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 300 365 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 300 365 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 12 20 30 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration, LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 500 ns
VIH = VDD, VIL = GND,
tw(ED2) Pulse duration, OE(ED2) in Error Detection Mode 2 μs
Rext = 360 Ω, VL= 4 V,
RL= 44 Ω, CL= 10 pF,
th(ED1,ED2) Hold time, LE(ED1) and OE(ED2) 10 ns
CG = 0.992
th(D) Hold time, SDI 2 ns
tsu(D,ED1) Setup time, SDI, LE(ED1) 3 ns
tsu(ED2) Setup time, OE(ED2) 8.5 ns
th(L) Hold time, LE(ED1), Normal Mode 15 ns
tsu(L) Setup time, LE(ED1), Normal Mode 15 ns
trRise time, CLK(2) 500 ns
tfFall time, CLK(2) 500 ns
tor Rise time, outputs (off) 40 85 105 ns
tor Rise time, outputs (off), TJ= 25°C 83 100 ns
tof Rise time, outputs (on) 100 280 370 ns
tof Rise time, outputs (on), TJ= 25°C 170 225 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tror tfis large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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7.8 Switching Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn 40 65 95 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 40 65 95 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 40 65 95 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 8 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 300 365 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 300 365 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 300 365 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 8 20 30 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration, LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 500 ns
VIH = VDD, VIL = GND,
tw(ED2) Pulse duration, OE(ED2) in Error Detection Mode 2 μs
Rext = 360 Ω, VL= 4 V,
RL= 44 Ω, CL= 10 pF,
th(D,ED1,ED2) Hold time, SDI, LE(ED1), and OE(ED2) 10 ns
CG = 0.992
th(D) Hold time, SDI 2 ns
tsu(D,ED1) Setup time, SDI, LE(ED1) 3 ns
tsu(ED2) Setup time, OE(ED2) 8.5 ns
th(L) Hold time, LE(ED1), Normal Mode 15 ns
tsu(L) Setup time, LE(ED1), Normal Mode 15 ns
trRise time, CLK(2) 500 ns
tfFall time, CLK(2) 500 ns
tor Rise time, outputs (off) 40 85 105 ns
tor Rise time, outputs (off), TJ= 25°C 83 100 ns
tof Rise time, outputs (on) 100 280 370 ns
tof Rise time, outputs (on), TJ= 25°C 170 225 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tror tfis large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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OE
OUT7
Turn on only one channel
Channel 8
0
25
50
75
100
125
150
0 0.5 1 1.5 2 2.5 3
Output Voltage (V)
Output Current (mA)
Temperature = 25°C
IO= 80 mA
IO= 40 mA
IO= 20 mA
IO= 60 mA
IO= 5 mA
IO= 100 mA
IO= 120 mA
OE
OUT1
Turn on only one channel
Channel 1
LE = 5 V (active)
= GND (active)OE
CLK
OUTn
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7.9 Timing Requirements
VDD = 3 V to 5.5 V (unless otherwise noted) MIN MAX UNIT
tw(L) LE(ED1) pulse duration Normal Mode 20 ns
tw(CLK) CLK pulse duration Normal Mode 20 ns
Normal Mode, IOUT < 60 mA 500
tw(OE) OE(ED2) pulse duration ns
Normal Mode, IOUT > 60 mA 700
tsu(D) Setup time for SDI Normal Mode 3 ns
th(D) Hold time for SDI Normal Mode 2 ns
tsu(L) Setup time for LE(ED1) Normal Mode 15 ns
th(L) Hold time for LE(ED1) Normal Mode 15 ns
tw(CLK) CLK pulse duration Error Detection Mode 20 ns
tw(ED2) OE(ED2) pulse duration Error Detection Mode 2000 ns
tsu(ED1) Setup time for LE(ED1) Error Detection Mode 4 ns
th(ED1) Hold time for LE(ED1) Error Detection Mode 10 ns
tsu(ED2) Setup time for OE(ED2) Error Detection Mode 6 ns
th(ED2) Hold time for OE(ED2) Error Detection Mode 10 ns
fCLK Clock frequency Cascade operation 30 MHz
7.10 Typical Characteristics
Figure 1. Response Time, CLK to OUTn Figure 2. Response Time, OE to OUT1
Figure 4. Output Current vs Output Voltage
Figure 3. Response Time, OE to OUT7
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V , V
IH IL
Logic Input
Waveform
V = 5 V
IH
V = 0V
IL
IOUT
RL
CL
Iref
VDD
OE(ED2)
CLK
LE(ED1)
SDI
R-EXT GND SDO
OUT7
OUT0
IDD
Function
Generator
VL
CL
IDD
I , I
IH IL
V ,V
IH IL
Iref
IOUT
VDD
OE(ED2)
CLK
LE(ED1)
SDI
R-EXT GND SDO
OUT7
OUT0
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8 Parameter Measurement Information
Figure 5. Test Circuit for Electrical Characteristics
Figure 6. Test Circuit for Switching Characteristics
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50%
LOW
Out fput of
Outp t onu
t , t
PLH1 PHL1
t , t
LH2 H 2P LP
CLK
SDI
SDO
LE(ED1)
OE(ED2)
OUTn
t , t
PLH4 PHL4
tw(CLK)
50%
50% 50%
50% 50%
50%
50%
50%
tsu(L)
th(L)
tw(L)
tsu(D) th(D)
50%
tw(OE)
tPHL3
tof tor
Output off
tPLH3
50%
20%
80%
OE(ED2)
OUTn 50%
80%
50%
20%
HIGH
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Parameter Measurement Information (continued)
Figure 7. Normal Mode Timing Waveforms
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50%
50%
tw(ED2)
OE(ED2)
CLK
tw(CLK)
tsu(ED2) th(ED2)
OE(ED2)
LE(ED1)
CLK
tsu(ED1) th(ED1)
2 CLK
50%
50%
50%
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Parameter Measurement Information (continued)
Figure 8. Switching to Special Mode Timing Waveforms
Figure 9. Reading Error Status Code Timing Waveforms
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9 Detailed Description
9.1 Overview
The TLC591x is designed for LED displays and LED lighting applications with constant-current control and open-
load, shorted-load, and overtemperature detection. The TLC591x contains an 8-bit shift register and data latches,
which convert serial input data into parallel output format. At the output stage, eight regulated current ports are
designed to provide uniform and constant current for driving LEDs within a wide range of LED Forward Voltage
(VF) variations. Used in system design for LED display applications, for example, LED panels, it provides great
flexibility and device performance. Users can adjust the output current from 3 mA to 120 mA per channel through
an external resistor, Rext, which gives flexibility in controlling the light intensity of LEDs. The devices are designed
for up to 20 V at the output port. The high clock frequency, 30 MHz, also satisfies the system requirements of
high-volume data transmission.
The TLC591x provides two operation modes: Normal Mode and Special Mode. Normal mode is used for shifting
LED data into and out of the driver. Special Mode includes two functions: Error Detection and Current Gain
Control. The two operation modes include three phases: Normal Mode phase, Mode Switching transition phase,
and Special Mode phase. The signal on the multiple function pin OE(ED2) is monitored to determine the mode.
When a one-clock-wide pulse appears on OE(ED2), the device enters the Mode Switching phase. At this time,
the voltage level on LE(ED1) determines which mode the TLC591x switches to.
In the Normal Mode phase, the serial data can be transferred into TLC591x through the pin SDI, shifted in the
shift register, and transferred out via the pin SDO. LE(ED1) can latch the serial data in the shift register to the
output latch. OE(ED2) enables the output drivers to sink current.
In the Special Mode phase, the low-voltage-level signal on OE(ED2) can enable output channels and detect the
status of the output current to determine if the driving current level is sufficient. The detected Error Status is
loaded into the 8-bit shift register and shifted out via the pin SDO, synchronous to the CLK signal. The system
controller can read the error status and determine if the LEDs are properly lit.
In the Special Mode phase, the TLC591x allows users to adjust the output current level by setting a runtime-
programmable Configuration Code. The code is sent into the TLC591x through SDI. The positive pulse of
LE(ED1) latches the code in the shift register into a built-in 8-bit configuration latch, instead of the output latch.
The code affects the voltage at the terminal R-EXT and controls the output-current regulator. The output current
can be finely adjusted by a gain ranging from 1/12 to 127/128 in 256 steps. Therefore, the current skew between
ICs can be compensated within less than 1%. This feature is suitable for white balancing in LED color display
panels.
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Product Folder Links: TLC5916 TLC5917

VDD
8
8
8
8
8
8
I/O Regulator
Control
Logic
OUT0 OUT1 OUT6 OUT7
Output Driver and
Error Detection
8-Bit Output
Latch
SDO
SDI
CLK
LE(ED1)
OE(ED2)
R-EXT
8-Bit Shift
Register
Configuration
Latches
TLC5916 , TLC5917
SLVS695D –JUNE 2007–REVISED JANUARY 2015 www.ti.com
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Open-Circuit Detection Principle
The LED Open-Circuit Detection compares the effective current level Iout with the open load detection threshold
current IOUT,Th. If IOUT is below the IOUT,Th threshold, the TLC591x detects an open-load condition. This error
status can be read as an error status code in the Special Mode. For open-circuit error detection, a channel must
be on.
Table 1. Open-Circuit Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT ERROR STATUS CODE MEANING
CURRENT
Off IOUT = 0 mA 0 Detection not possible
IOUT < IOUT,Th (1) 0 Open circuit
On IOUT ≥IOUT,Th (1) Channel n error status bit 1 Normal
(1) IOUT,Th = 0.5 × IOUT,target (typical)
9.3.2 Short-Circuit Detection Principle (TLC5917 Only)
The LED short-circuit detection compares the effective voltage level (VOUT) with the shorted-load detection
threshold voltages VOUT,TTh and VOUT,RTh. If VOUT is above the VOUT,TTh threshold, the TLC5917 detects an
shorted-load condition. If VOUT is below the VOUT,RTh threshold, no error is detected/error bit is reset. This error
status can be read as an error status code in the Special Mode. For short-circuit error detection, a channel must
be on.
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Product Folder Links: TLC5916 TLC5917

No Fault
Short Fault
Minimum
Return
Threshold
Maximum
Trigger
Threshold
3.1 V
2.5 V
2.2 V VOUT
Minimum
Trigger
Threshold
VOUT,TTh VOUT,RTh
TLC5916 , TLC5917
www.ti.com SLVS695D –JUNE 2007–REVISED JANUARY 2015
Table 2. Shorted-Load Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT ERROR STATUS CODE MEANING
VOLTAGE
Off IOUT = 0 mA 0 Detection not possible
VOUT ≥VOUT,TTh 0 Short circuit
On VOUT < VOUT,RTh 1 Normal
Figure 10. Short-Circuit Detection Principle
9.3.3 Overtemperature Detection and Shutdown
TLC591x is equipped with a global overtemperature sensor and eight individual, channel-specific,
overtemperature sensors.
• When the global sensor reaches the trip temperature, all output channels are shut down, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
after cooling down and can be read out as the error status code in the Special Mode.
• When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in the
Special Mode.
For channel-specific overtemperature error detection, a channel must be on.
The error status code is reset when TLC591x returns to Normal Mode.
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TLC5916 , TLC5917
SLVS695D –JUNE 2007–REVISED JANUARY 2015 www.ti.com
Table 3. Overtemperature Detection(1)
STATE OF OUTPUT PORT CONDITION ERROR STATUS CODE MEANING
Off IOUT = 0 mA 0
On Tj< Tj,trip global 1 Normal
On →all channels Tj> Tj,trip global All error status bits = 0 Global overtemperature
Off Tj< Tj,trip channel n 1 Normal
On
On →Off Tj> Tj,trip channel n Channel n error status bit = 0 Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.
9.4 Device Functional Modes
The TLC591x provides two operation modes: Normal Mode and Special Mode. Normal mode is used for shifting
LED data into and out of the driver. Special Mode includes two functions: Error Detection and Current Gain
Control. The two operation modes include three phases: Normal Mode phase, Mode Switching transition phase,
and Special Mode phase. The signal on the multiple function pin OE(ED2) is monitored to determine the mode.
When a one-clock-wide pulse appears on OE(ED2), the device enters the Mode Switching phase. At this time,
the voltage level on LE(ED1) determines which mode the TLC591x switches to.
In the Normal Mode phase, the serial data can be transferred into TLC591x through the pin SDI, shifted in the
shift register, and transferred out via the pin SDO. LE(ED1) can latch the serial data in the shift register to the
output latch. OE(ED2) enables the output drivers to sink current.
In the Special Mode phase, the low-voltage-level signal on OE(ED2) can enable output channels and detect the
status of the output current to determine if the driving current level is sufficient. The detected Error Status is
loaded into the 8-bit shift register and shifted out via the pin SDO, synchronous to the CLK signal. The system
controller can read the error status and determine if the LEDs are properly lit.
In the Special Mode phase, the TLC591x allows users to adjust the output current level by setting a runtime-
programmable Configuration Code. The code is sent into the TLC591x through SDI. The positive pulse of
LE(ED1) latches the code in the shift register into a built-in 8-bit configuration latch, instead of the output latch.
The code affects the voltage at the terminal R-EXT and controls the output-current regulator. The output current
can be finely adjusted by a gain ranging from 1/12 to 127/128 in 256 steps. Therefore, the current skew between
ICs can be compensated within less than 1%. This feature is suitable for white balancing in LED color display
panels.
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Product Folder Links: TLC5916 TLC5917

1 2 3 4 5
1 0 1 1 1
10 0 0 0
CLK
OE(ED2)
LE(ED1)
1 2 30 4 6 75
0
1
off
on
off
on
off
on
off
on
off
on
Don't care
CLK
OE(ED2)
LE(ED1)
SDI
OUT0
OUT1
OUT2
OUT3
OUT7
SDO
TLC5916 , TLC5917
www.ti.com SLVS695D –JUNE 2007–REVISED JANUARY 2015
Device Functional Modes (continued)
Figure 11. Normal Mode
Table 4. Truth Table in Normal Mode
CLK LE(ED1) OE(ED2) SDI OUT0...OUT7 SDO
↑H L Dn Dn...Dn – 7 Dn – 7
↑L L Dn + 1 No change Dn – 6
↑H L Dn + 2 Dn + 2...Dn – 5 Dn – 5
↓X L Dn + 3 Dn + 2...Dn – 5 Dn – 5
↓X H Dn + 3 Off Dn – 5
The signal sequence shown in Figure 12 makes the TLC591x enter Current Adjust and Error Detection Mode.
Figure 12. Switching to Special Mode
In the Current Adjust Mode, sending the positive pulse of LE(ED1), the content of the shift register (a current
adjust code) is written to the 8-bit configuration latch (see Figure 13).
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1 2 3 4 5
1 0 1 1 1
0 0 0 0
0
CLK
OE(ED2)
LE(ED1)
1 2 3
0
1>2 µs
CLK
OE(ED2)
LE(ED1)
SDO Error Status Code
1 2 30 67
1
0
8-bit Configuration Code
CLK
OE(ED2)
LE(ED1)
SDI
TLC5916 , TLC5917
SLVS695D –JUNE 2007–REVISED JANUARY 2015 www.ti.com
Figure 13. Writing Configuration Code
When the TLC591x is in the Error Detection Mode, the signal sequence shown in Figure 14 enables a system
controller to read error status codes through SDO.
Figure 14. Reading Error Status Code
The signal sequence shown in Figure 15 makes TLC591x resume the Normal Mode. Switching to Normal Mode
resets all internal Error Status registers. OE(ED2) always enables the output port, whether the TLC591x enters
Current Adjust Mode or not.
Figure 15. Switching to Normal Mode
9.4.1 Operation Mode Switching
To switch between its two modes, TLC591x monitors the signal OE(ED2). When an one-clock-wide pulse of
OE(ED2) appears, TLC591x enters the two-clock-period transition phase, the Mode Switching phase. After
power on, the default operation mode is the Normal Mode (see Figure 16).
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1 2 3 4 5
1 0 1 1 1
00 0 0 0
Actual Mode
(Normal or Special) Mode Switching Normal
Mode
CLK
OE(ED2)
LE(ED1)
Phase
1 2 3 4 5
1 0 1 1 1
10 0 0 0
Actual Mode
(Normal or Special) Mode Switching Special
Mode
CLK
OE(ED2)
LE(ED1)
Phase
Switching to Special Mode Switching to Normal Mode
TLC5916 , TLC5917
www.ti.com SLVS695D –JUNE 2007–REVISED JANUARY 2015
Figure 16. Mode Switching
As shown in Figure 16, once a one-clock-wide short pulse (101) of OE(ED2) appears, TLC591x enters the Mode
Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high, TLC591x switches to
Special Mode; otherwise, it switches to Normal Mode. The signal LE(ED1) between the third and the fifth rising
edges of CLK cannot latch any data. Its level is used only to determine into which mode to switch. However, the
short pulse of OE(ED2) can still enable the output ports. During mode switching, the serial data can still be
transferred through SDI and shifted out from SDO.
NOTE
1. The signal sequence for the mode switching may be used frequently to ensure that TLC591x is
in the proper mode.
2. The 1 and 0 on the LE(ED1) signal are sampled at the rising edge of CLK. The X means its
level does not affect the result of mode switching mechanism.
3. After power on, the default operation mode is Normal Mode.
9.4.1.1 Normal Mode Phase
Serial data is transferred into TLC591x through SDI, shifted in the Shift Register, and output via SDO. LE(ED1)
can latch the serial data in the Shift Register to the Output Latch. OE(ED2) enables the output drivers to sink
current. These functions differ only as described in Operation Mode Switching, in which case, a short pulse
triggers TLC591x to switch the operation mode. However, as long as LE(ED1) is high in the Mode Switching
phase, TLC591x remains in the Normal Mode, as if no mode switching occurred.
9.4.1.2 Special Mode Phase
In the Special Mode, as long as OE(ED2) is not low, the serial data is shifted to the Shift Register via SDI and
shifted out via SDO, as in the Normal Mode. However, there are two differences between the Special Mode and
the Normal Mode, as shown in the following sections.
9.4.2 Reading Error Status Code in Special Mode
When OE(ED2) is pulled low while in Special Mode, error detection and load error status codes are loaded into
the Shift Register, in addition to enabling output ports to sink current. Figure 17 shows the timing sequence for
error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must
be sampled at the voltage low signal OE(ED2). Immediately after the second zero is sampled, the data input
source of the Shift Register changes to the 8-bit parallel Error Status Code register, instead of from the serial
data on SDI. Normally, the error status codes are generated at least 2 μs after the falling edge of OE(ED2). The
occurrence of the third or later zero saves the detected error status codes into the Shift Register. Therefore,
when OE(ED2) is low, the serial data cannot be shifted into TLC591x through SDI. When OE(ED2) is pulled high,
the data input source of the Shift Register is changed back to SDI. At the same time, the output ports are
disabled and the error detection is completed. Then, the error status codes saved in the Shift Register can be
shifted out via SDO bit by bit along with CLK, as well as the new serial data can be shifted into TLC591x through
SDI.
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1 2 30 4 56 7
1
0
CLK
OE(ED2)
LE(ED1)
SDI 8-Bit Configuration Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 2 3
1 0 0 0 1
0 0 0 0
0
0 0
0 0 0 0
1 1 1
0
CLK
OE(ED2)
LE(ED1)
SDO
Data source of
shift register Error Detection
SDI SDI
Error Status Code
Bit 7 Bit 6 Bit 5 Bit 4
>2 µs
TLC5916 , TLC5917
SLVS695D –JUNE 2007–REVISED JANUARY 2015 www.ti.com
While in Special Mode, the TLC591x cannot simultaneously transfer serial data and detect LED load error status.
Figure 17. Reading Error Status Code
9.4.3 Writing Configuration Code in Special Mode
When in Special Mode, the active high signal LE(ED1) latches the serial data in the Shift Register to the
Configuration Latch, instead of the Output Latch. The latched serial data is used as the Configuration Code.
The code is stored until power off or the Configuration Latch is rewritten. As shown in Figure 18, the timing for
writing the Configuration Code is the same as the timing in the Normal Mode to latching output channel data.
Both the Configuration Code and Error Status Code are transferred in the common 8-bit Shift Register. Users
must pay attention to the sequence of error detection and current adjustment to avoid the Configuration Code
being overwritten by Error Status Code.
Figure 18. Writing Configuration Code
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