Texas Instruments TPS3703 User manual

VIT+(OV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D004
RESET
VDD
SENSE MR
CT
GND
RESET
VCORE
Processor
OV Threshold
UV Threshold
Optional
TPS3703
1
Monitor Voltage
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3703
SBVS249A –MAY 2020–REVISED JUNE 2020
TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and
Manual Reset
1
1 Features
1• Input voltage range: 1.7 V to 5.5 V
• Undervoltage lockout (UVLO): 1.7 V
• Low quiescent current: 7 µA (Max)
• High threshold accuracy:
– ± 0.25% (typical)
– ± 0.7% (–40°C to +125°C)
• Fixed window threshold levels
– 50-mV steps from 500 mV to 1.3 V
– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V
– Available in UV threshold only
– Window tolerance available from ±3% to ±7%
• User adjustable voltage threshold levels
• Internal glitch immunity and hysteresis
• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10
ms, 20 ms, 100 ms, 200 ms
• Programmable time delay option with a single
external capacitor
• Open-drain active low UV and OV monitor
• RESET voltage latching output mode
2 Applications
•Motor drives
•Factory automation and control
•Home theater and entertainment
•Grid infrastructure
•Data center and enterprise computing
Integrated Overvoltage and Undervoltage
Detection
3 Description
The TPS3703 device is an integrated overvoltage
(OV) and undervoltage (UV) monitor or reset IC in
industry’s smallest 6-pin DSE package. This highly
accurate voltage supervisor is ideal for systems that
operate on low-voltage supply rails and have narrow
margin supply tolerances. Low threshold hysteresis
prevent false reset signals when the monitored
voltage supply is in its normal range of operation.
Internal glitch immunity and noise filters further
eliminate false resets resulting from erroneous
signals.
The TPS3703 does not require any external resistors
for setting overvoltage and undervoltage reset
thresholds, which further optimizes overall accuracy,
cost, solution size, and improves reliability for safety
systems. The Capacitor Time (CT) pin is used to
select between the two available reset time delays
designed into each device and also to adjust the
reset time delay by connecting a capacitor. A
separate SENSE input pin and VDD pin allow for the
redundancy sought by high-reliability systems.
This device has a low typical quiescent current
specification of 4.5 µA (typical). The TPS3703 is
suitable for industrial applications and applications
that require accurate undervoltage and overvoltage
monitoring.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS3703 WSON (6) 1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Overvoltage Accuracy Distribution

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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison ............................................... 3
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 9
8 Detailed Description............................................ 13
8.1 Overview................................................................. 13
8.2 Functional Block Diagram....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 16
9 Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 26
10.1 Power Supply Guidelines...................................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support................. 27
12.1 Device Nomenclature............................................ 27
12.2 Documentation Support ........................................ 29
12.3 Receiving Notification of Documentation Updates 29
12.4 Support Resources ............................................... 29
12.5 Trademarks........................................................... 29
12.6 Electrostatic Discharge Caution............................ 29
12.7 Glossary................................................................ 29
13 Mechanical, Packaging, and Orderable
Information........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2020) to Revision A Page
• APL to RTM release .............................................................................................................................................................. 1

TPS 3703 X X XXX XXX X
Time Delay Option
A: CT (open) 10 ms, CT (VDD) = 200 ms
B: CT (open) 1 ms, CT (VDD) = 20 ms
C: CT (open) 5 ms, CT (VDD) = 100 ms
D: CT (open) 50 µs, CT (VDD) = 50 µs
Y
Nominal Threshold Option
050: 0.50V
...
500: 5.00V
Tolerance Option
3: UV/OV = 3%
4: UV/OV = 4%
5: UV/OV = 5%
6: UV/OV = 6%
7: UV/OV = 7%
Reel
R: Large reel
Package
DSE: WSON (6-pin)
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5 Device Comparison
Figure 1 shows the device nomenclature of the TPS3703. For all possible voltages, window tolerance, time
delays, and UV threshold options, see Table 7. Contact TI sales representatives or on TI's E2E forum for details
and availability of other options; minimum order quantities apply.
Figure 1. TPS3703 Device Nomenclature

SENSE
VDD
CT RESET
MR
GND
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6 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 SENSE I Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if
monitoring VDD supply voltage.
2 VDD I Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.
3 CT I Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.
4 RESET O Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (VIT+) or below the undervoltage threshold (VIT–). See the timing diagram in
Figure 25 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up
voltage.
5 GND — Ground
6 MR I Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.

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(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ= TA.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VDD –0.3 6 V
Voltage VRESET –0.3 6 V
Voltage VCT –0.3 6 V
Voltage VSENSE –0.3 6 V
Voltage VMR –0.3 6 V
Current IRESET ±40 mA
Temperature (2)
Continuous total power dissipation See the Thermal Information
Operating junction temperature, TJ-40 150 °C
Operating free-air temperature, TA-40 150 °C
Storage temperature, Tstg -65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩis recommended.
(2) The maximum rating is VDD or 5.5 V, whichever is smaller.
(3) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
VDD Supply pin voltage 1.7 5.5 V
VSENSE Input pin voltage 0 5.5 V
VCT CT pin voltage (1) (2) VDD V
VRESET Output pin voltage 0 5.5 V
VMR MR pin Voltage (3) 0 5.5 V
IRESET Output pin current 0.3 10 mA
TJJunction temperature (free-air temperature) -40 125 ℃

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1) TPS3703 UNITDSE (WSON)
PINS
RθJA Junction-to-ambient thermal resistance 184.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.6 °C/W
RθJB Junction-to-board thermal resistance 86.4 °C/W
ΨJT Junction-to-top characterization parameter 13.4 °C/W
ΨJB Junction-to-board characterization parameter 86.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) RESET pin is driven low when VDD falls below UVLO.
(2) VPOR is the minimum VDD voltage level for a controlled output state.
(3) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.
7.5 Electrical Characteristics
At 1.7 V ≤VDD ≤5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩto VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage 1.7 5.5 V
UVLO Under Voltage Lockout(1) VDD falling below 1.7 V 1.2 1.7 V
VPOR Power on reset voltage(2) VOL(max) = 0.25 V, IOUT = 15 µA 1 V
VIT+(OV) Positive- going threshold accuracy -0.7 ±0.25 0.7 %
VIT-(UV) Negative-going threshold accuracy -0.7 ±0.25 0.7 %
VHYS Hysteresis Voltage(3) 0.3 0.55 0.8 %
IDD Supply current VDD ≤5.5 V 4.5 7 µA
ISENSE Input current, SENSE pin VSENSE = 5 V 1 1.5 µA
VOL Low level output voltage VDD = 1.7 V, IOUT = 0.4 mA 250 mV VDD = 2 V, IOUT = 3 mA 250 mV
VDD = 5 V, IOUT = 5 mA 250 mV
ILKG Open drain output leakage current VDD = VRESET = 5.5 V 300 nA
VMR_L MR logic low input 0.3 V
VMR_H MR logic high input 1.4 V
VCT_H High level CT pin voltage 1.4 V
RMR Manual reset Internal pullup resistance 100 KΩ
ICT CT pin charge current 337 375 413 nA
VCT CT pin comparator threshold voltage(4) 1.133 1.15 1.167 V
7.6 Timing Requirements
At 1.7 V ≤VDD ≤5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩto VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD = 3.3 V. MIN NOM MAX UNIT
tDReset time delay, TPS3703A, TPS3703E CT = Open 7 10 13 ms
tDReset time delay, TPS3703A, TPS3703E CT = 10 kΩto VDD 140 200 260 ms
tDReset time delay, TPS3703B, TPS3703F CT = Open 0.7 1 1.3 ms
tDReset time delay, TPS3703B, TPS3703F CT = 10 kΩto VDD 14 20 26 ms
tDReset time delay, TPS3703C, TPS3703G CT = Open 3.5 5 6.5 ms

All percentages are calculated with respect to typical VIT
Tolerance[-3% to -7%] Tolerance[+3% to +7%]
[ -1.5% = -0.7%-0.8%) ]
0.5%
[ -1.0% = -0.7%-0.3%) ]
[ -1.25% = -0.7%-0.55%) ]
VIT+(OV)
[0.55%]
[-0.25%]
[0.25%]
[-0.7%] VIT+(OV) - VHYS
[-0.8%]
[-0.3%]
[-0.55%]
Hys band for VIT+(OV)
[0.7%]
[0.55%] [0.55%]
[ -0.1% = 0.7%-0.8%) ]
0.5%
[ 0.4% = 0.7%-0.3%) ]
[ 0.15% = 0.7%-0.55%) ]
Overdrive[2.5%] above VIT+(OV)
[0.25%]
[-0.25%]
[0.55%]
[0.55%]
Hys band for VIT-(UV)
VIT-(UV)
Accuracy at 25ºC
Accuracy across (-40ºC to 125ºC)
[ 0.1% = -0.7%+0.8%) ]
[ -0.4% = -0.7%+0.3% ]
[ -0.15% = -0.7%+0.55%) ]
[0.8%]
[0.3%]
[0.55%]
[ 1.5% = 0.7%+0.8%) ]
[ 1.0% = 0.7%+0.3%) ]
[ 1.25% = 0.7%+0.55%) ]
Overdrive [2.5%] below VIT-(UV)
VIT-(UV) + VHYS
0.5%
0.5%
[0.55%]
[-0.25%]
[0.25%]
[-0.7%]
[0.7%]
Accuracy at 25ºC
Accuracy across (-40ºC to 125ºC)
Nominal monitored voltage
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Timing Requirements (continued)
At 1.7 V ≤VDD ≤5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩto VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD = 3.3 V. MIN NOM MAX UNIT
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT]/VIT; Where VIT stands for VIT-(UV) or VIT+(OV)
(2) tPD measured from threhold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tDbefore the output is in the correct state.
tDReset time delay, TPS3703C, TPS3703G CT = 10 kΩto VDD 70 100 130 ms
tDReset time delay, TPS3703D, TPS3703H CT = 10 kΩto VDD
CT = Open 50 µs
tPD Propagation detect delay(1)(2) 15 30 µs
tROutput rise time(1)(3) 2.2 µs
tFOutput fall time(1)(3) 0.2 µs
tSD Startup delay(4) 300 µs
tGI (VIT-) Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1) 3.5 µs
tGI (VIT+) Glitch Immunity overvoltage VIT+(OV), 5% Overdrive(1) 3.5 µs
tGI (MR) Glitch Immunity MR pin 25 ns
tPD (MR) Propagation delay from MR low to assert RESET 500 ns
tMR_W MR pin pulse width duration to assert RESET 1 µs
tD (MR) MR reset time delay tDms
Figure 2. Voltage Threshold and Hysteresis Accuracy

tD
VIT
Hysteresis
Hysteresis
VDD(MIN)
VPOR
UVLO
RESET tD tPD
Undefined
SENSE
VDD
VIT+(OV)
VIT+(OV) - VHYS
VIT-(UV)
VIT-(UV) + VHYS
tPD
tD
tSD
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(1) VDD = 2 V, RPU = 10 kΩto VDD
(2) Variant D (time delay bypass) has a ~40 µs pulse at RESET pin during power up window, this is present only when
the power cycle off time is longer than 10 seconds, this behavior will not occur if SENSE pin is within window of
operation during VDD power up.
Figure 3. SENSE Timing Diagram

Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
0.5
0.52
0.54
0.56
0.58
0.6
D005
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
0.5
0.52
0.54
0.56
0.58
0.6
D006
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
VIT-(UV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D003
VIT+(OV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D004
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
D001
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
D002
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
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7.7 Typical Characteristics
At TJ= 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
Tested across multiple voltage options
Figure 4. Undervoltage Accuracy vs Temperature
Tested across multiple voltage options
Figure 5. Overvoltage Accuracy vs Temperature
Sample Size of 100 TPS3703A7125 units
Figure 6. Undervoltage Accuracy Distribution
Sample Size of 100 TPS3703A7125 units
Figure 7. Overvoltage Accuracy Distribution
Tested across multiple voltage options
Figure 8. Undervoltage Hysteresis Voltage Accuracy vs
Temperature
Tested across multiple voltage options
Figure 9. Overvoltage Hysteresis Voltage Accuracy vs
Temperature

Overdrive (%)
SENSE Glitch Immunity (Ps)
0 5 10 15 20 25 30 35 40 45 50 55
3
4
5
6
7
8
9
D011
-40qC
25qC
125qC
Overdrive (%)
SENSE Glitch Immunity (Ps)
0 5 10 15 20 25 30 35 40 45 50 55
3
4
5
6
7
8
9
D012
-40qC
25qC
125qC
Overdrive (%)
SENSE Glitch Immunity (Ps)
0 5 10 15 20 25 30 35 40 45 50 55
9
10
11
12
13
14
15
16
D009
-40qC
25qC
125qC
Overdrive (%)
SENSE Glitch Immunity (Ps)
0 5 10 15 20 25 30 35 40 45 50 55
9
10
11
12
13
14
15
16
D010
-40qC
25qC
125qC
Temperature (qC)
Supply Current (PA)
-50 -25 0 25 50 75 100 125
2
3
4
5
6
7
D007
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
Temperature (qC)
Supply Current (PA)
-50 -25 0 25 50 75 100 125
2
3
4
5
6
D008
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
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Typical Characteristics (continued)
At TJ= 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
Output (RESET Pin) = High
Figure 10. Supply Current vs Temperature
Output (RESET Pin) = Low
Figure 11. Supply Current vs Temperature
VDD = 1.7 V
Figure 12. SENSE Glitch Immunity (VIT-) vs Overdrive
VDD = 1.7 V
Figure 13. SENSE Glitch Immunity (VIT+) vs Overdrive
VDD = 5.5 V
Figure 14. SENSE Glitch Immunity (VIT-) vs Overdrive
VDD = 5.5 V
Figure 15. SENSE Glitch Immunity (VIT+) vs Overdrive

Temperature (qC)
ICT (nA)
-50 -25 0 25 50 75 100 125
365
370
375
380
385
390
D017
1.7 V
5.5 V
Capacitor Value (nF)
tD with Capacitor (s)
0.1 0.2 0.5 1 2 3 45 7 10 2030 50 100 200 5001000
0
0.5
1
1.5
2
2.5
3
3.5
tD_r
25°C
-40°C
125°C
Temperature (qC)
MR Threshold (V)
-50 -25 0 25 50 75 100 125
0.3
0.4
0.5
0.6
D015
VMR_H
VMR_L
Temperature (qC)
MR Threshold (V)
-50 -25 0 25 50 75 100 125
1.04
1.06
1.08
1.1
1.12
1.14
1.16
D016
VMR_H
VMR_L
IRESET (mA)
VOL (V)
0 1 2 3 4 5
0
0.05
0.1
0.15
0.2
0.25
0.3
D013
-40qC
25qC
125qC
IRESET (mA)
VOL (V)
0 1 2 3 4 5
0
0.05
0.1
0.15
0.2
0.25
D014
-40qC
25qC
125qC
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Typical Characteristics (continued)
At TJ= 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
VDD = 1.7 V
Figure 16. Low-Level Output Voltage vs RESET Current
VDD = 5.5 V
Figure 17. Low-Level Output Voltage vs RESET Current
VDD = 1.7 V
Figure 18. SET Threshold vs Temperature
VDD = 5.5 V
Figure 19. SET Threshold vs Temperature
Figure 20. CT Current vs CT Value Figure 21. RESET Timeout vs CT Capacitor

Temperature (qC)
tPD(SENSE) (Ps)
-50 -25 0 25 50 75 100 125
0
2
4
6
8
10
12
D020
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
Capacitor Value (nF)
tD with Capacitor (ms)
0.1 0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10
0
5
10
15
20
25
30
35
tD_r
25°C
-40°C
125°C
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Typical Characteristics (continued)
At TJ= 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
Figure 22. Timeout vs CT Capacitor (0.1 to 10 nF) Figure 23. Detect Propagation Delay vs Temperature

GND
SENSE
RESET
MR
Time Delay
Logic
VDD
RMR
Vref
VDD CT
ICT
Cap
Control
VCT 50mV
UV Comparator
GND
RESET
MR
Time Delay
Logic
VDD
RMR
VDD CT
ICT
Cap
Control
VCT 50mV
SENSE
Vref
Vref_OV
Vref_UV
UV Comparator
OV Comparator
Undervoltage Only Version Window Version
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8 Detailed Description
8.1 Overview
The TPS3703 family of devices combines two voltage comparators and a precision voltage reference for
overvoltage and undervoltage detection. The TPS3703 features a highly accurate window threshold voltages
(±0.7% over temperature) and a variety voltage threshold variants.
The TPS3703 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the
device. These internal resistors allow for lower component counts and greatly simplifies the design because no
additional margins are needed to account for the accuracy of external resistors.
TPS3703 version A, B and C has three time delay settings, two fixed by connecting CT pin to VDD through a
resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor
connected from CT pin to ground.
Manual Reset (MR) allows for sequencing or hard reset by driving the MR pin below VMR_L.
The TPS3703 is designed to assert active low output signals when the monitored voltage is outside the safe
window. The relationship between the monitored voltage and the states of the outputs is shown in Table 1.
8.2 Functional Block Diagram
*For all possible voltages, window tolerance, time delays, and UV threshold options, see Table 7.
8.3 Feature Description
8.3.1 VDD
The TPS3703 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input supply
capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 1-
µF capacitor between the VDD pin and the GND pin.
VDD needs to be at or above VDD(MIN) for at least the start-up delay (tSD+ tD) for the device to be fully functional.
8.3.2 SENSE
The TPS3703 combines two comparators with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. Both comparators also include built-in hysteresis that provides noise immunity and
ensures stable operation.
Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to 10-
nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored
signal.
When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output (RESET) is
high impedance when voltage at the SENSE pin is between upper and lower boundary of threshold.

tPD
VSENSE
UV Limit
VIT+(OV)
VIT+(OV) - VHYS
VIT-(UV)
VIT-(UV) + VHYS
RESET
OV Limit
tD tD
tPD
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Feature Description (continued)
8.3.3 RESET
In a typical TPS3703 application, the RESET output is connected to a reset or enable input of a processor [such
as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the
enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator (LDO)].
The TPS3703 has an open drain active low output that requires a pull-up resistor to hold these lines high to the
required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be connected
to other devices at the correct interface voltage levels. To ensure proper voltage levels, give some consideration
when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, output capacitive
loading, and output leakage current. These values are specified in Specifications. The open drain output can be
connected as a wired-OR logic with other open drain signals such as another TPS3703 RESET pin.
Table 1 describes the scenarios when the output (RESET) is either asserted low or high impedance.
Figure 24. RESET output
8.3.4 Capacitor Time (CT)
The CT pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing
options and user-programmable, reset delay timing. The CT pin can be pulled up to VDD through a resistor, have
an external capacitor to ground, or can be left unconnected. The configuration of the CT pin is re-evaluated by
the device every time the voltage on the SENSE line enters the valid window (VIT-(UV) < VSENSE < VIT+(OV)). The
pin evaluation is controlled by an internal state machine that determines which option is connected to the CT pin.
The sequence of events takes 450 μs to determine if the CT pin is left unconnected, pulled up through a resistor,
or connected to a capacitor. If the CT pin is being pulled up to VDD, then a pull-up resistor is required, 10 kΩis
recommended.
8.3.5 Manual Reset (MR)
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window
((VIT-(UV) < VSENSE < VIT+(OV)) , RESET is deasserted after the reset delay time (tD). If MR is not controlled
externally, then MR can either be connected to VDD or left floating because the MR pin is internally pulled up to
VDD. Figure Figure 25 shows the relation between MR and RESET.

VIT+(OV)
VIT+(OV) - VHYS
VIT-(UV)
VIT-(UV) + VHYS
Hysteresis
Hysteresis
tD(MR)
VMR_L
tMR_W
Pulse < tGI (MR)
tPD (MR)
RESET
SENSE
Pulse < VMR_L
MR
VMR_H
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Feature Description (continued)
(1) RESET pulls up to VDD with 10 kΩ.
(2) To initiate and continue time reset counter both conditions must be met MR pin above VMR_H or floating and VSENSE
between VIT-(UV) + VHYS and VIT+(OV) - VHYS
(3) MR is ignored during output RESET low event
Figure 25. Manual Reset Timing Diagram

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8.4 Device Functional Modes
Table 1. Functional Mode Truth Table
DESCRIPTION CONDITION MR PIN VDD PIN OUTPUT (RESET PIN)
Normal Operation VIT–(UV) < SENSE < VIT+(OV) Open or above VMR_H VDD > VDD(MIN) High
Normal Operation
(UV Only) SENSE > VIT-(UV) Open or above VMR_H VDD > VDD(MIN) High
Over Voltage
detection SENSE > VIT+(OV) Open or above VMR_H VDD > VDD(MIN) Low
Under Voltage
detection SENSE < VIT-(UV) Open or above VMR_H VDD > VDD(MIN) Low
Manual reset VIT–(UV) < SENSE < VIT+(OV) Below VMR_L VDD > VDD(MIN) Low
UVLO engaged VIT–(UV) < SENSE < VIT+(OV) Open or above VMR_H VPOR < VDD < UVLO Low
8.4.1 Normal Operation (VDD > VDD(MIN))
When the voltage on VDD is greater than VDD(MIN) for approximately (tSD+ tD), the RESET output state will
correspond to the SENSE pin voltage with respect to the threshold limits, when SENSE voltage is outside of
threshold limits the RESET voltage will be low (VOL).
8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage
(VPOR), the RESET pin will be held low , regardless of the voltage on SENSE pin.
8.4.3 Power-On Reset (VDD < VPOR)
When the voltage on VDD is lower than the required voltage (VPOR) to internally pull the asserted output to GND,
RESET signal is undefined and is not to be relied upon for proper device function.

DC/DC nominal output
Regulator output voltage accuracy
Margin for ripple and transients
0.7% Allowed threshold tolerance
- 0.7% Minimum system voltage
0%
4%
5%
Potential Failure or Malfunction
+
Supply
Voltage
Margin
Voltage
Threshold
Accuracy
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Voltage Threshold Accuracy
Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.
Due to the high precision of the TPS3703 (±0.7% Max), the device allows for a wider supply voltage margins and
threshold headroom for tight tolerance applications.
For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a
tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%
which allows for ±1% of threshold accuracy. Since the TPS3703 threshold accuracy is higher than ±1%, the user
has more supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to the
DC/DC to use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple and
transients. There is also headroom between the minimum system voltage and voltage tolerance of the MCU to
ensure that the voltage supply will never be in the region of potential failure of malfunction without the TPS3703
asserting a reset signal.
Figure 26 illustrates the supply undervoltage margin and accuracy of the TPS3703 for the example explained
above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and
transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.
Figure 26. TPS3703 Voltage Threshold Accuracy

VDD
ICT
CT
VDD
CT
10 k
CT
User Programmable
Capacitor to GND 10 NŸ5HVLVWRUWR9'' CT Unconnected
VDD
VDD
ICT
VDD
ICT
VDD
Cap
Control
Cap
Control
Cap
Control
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Application Information (continued)
9.1.2 CT Reset Time Delay
The TPS3703 features three options for setting the reset delay (tD): connecting a capacitor to the CT pin,
connecting a pull-up resistor to VDD, and leaving the CT pin unconnected. Figure 27 shows a schematic drawing
of all three options. To determine which option is connected to the CT pin, an internal state machine controls the
internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs to determine
which timing option is used. Every time the voltage on the SENSE line enters the valid window (VIT-(UV) + VHYS <
VSENSE < VIT+(OV) -VHYS, the state machine determines the CT option.
Figure 27. CT Charging Circuit
9.1.2.1 Factory-Programmed Reset Delay Timing
To use the factory-programmed timing options, the CT pin must either be left unconnected or pulled up to VDD
through a 10 kΩpull-up resistor. Using these options enables a high-precision reset delay timing, as shown in
Table 2.
Table 2. Reset Delay Time for Factory-Programmed Reset Delay Timing
VARIANT RESET DELAY TIME (tD)VALUE
CT = Capacitor to GND CT = Floating CT = 10 kΩto VDD
TPS3703A Programmable tD10 200 ms
TPS3703B Programmable tD1 20 ms
TPS3703C Programmable tD5 100 ms
TPS3703D N/A 50 50 µs
9.1.2.2 Programmable Reset Delay-Timing
The TPS3703 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and
read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on
maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near
to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed for
a given delay time can be calculated using Equation 1, where CCT is in nanofarads (nF) and tDis in ms:
tD= 3.066 × CCT + 0.5 ms (1)
To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.
tD(min) = 2.7427 × CCT + 0.3 ms (2)
tD(max) = 3.4636 × CCT + 0.7 ms (3)

VDD
ICT
CT
10 kResistor to
GND to Latch
VDD
Cap
Control
10 k
Voltage at CT
to Unlatch
10 k
V > VCT
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The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged
through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal precision current
source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is unasserted. Note
that in order to minimize the difference between the calculated RESET delay time and the actual RESET delay
time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board
capacitance around this pin. Table 3 lists the reset delay time ideal capacitor values for CCT.
Table 3. Reset Delay Time for Ideal Capacitor Values
CCT RESET DELAY TIME (tD), TYPICAL
250 pF 1.27 ms
1 nF 3.57 ms
3.26 nF 10.5 ms
32.6 nF 100.45 ms
65.2 nF 200.40 ms
1uF 3066.50 ms
9.1.3 RESET Latch Mode
The TPS3703 features a voltage latch mode on the RESET pin when connecting the CT pin to common ground .
A pull-down resistor is recommended to limit current consumption of the system. In latch mode, if the RESET pin
is low or triggers low, the pin will stay low regardless if VSENSE is within the acceptable voltage boundaries
(VIT–(UV) < VSENSE < VIT+(OV)). To unlatch the device provide a voltage to the CT pin that is greater than the CT pin
comparator threshold voltage, VCT. The RESET pin will trigger high instantaneously without any reset delay. A
voltage greater than 1.2 V to recommended to ensure a proper unlatch. Use a series resistance to limit current
when an unlatch voltage is applied. For more information, Design 2: RESET Latch Mode gives an example of a
typical latch application.
Figure 28. RESET Latch Circuit

MR
TPS3703
SENSE RESET
VDD
CT GND
VDD
VDD
R2
10 lQ
R1
VMON
Vsense
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9.1.4 Adjustable Voltage Thresholds
The TPS3703 0.7% maximum accuracy allows for adjustable voltage thresholds using external resistors without
adding major inaccuracies to the device. In case that the desired monitored voltage is not available, external
resistor dividers can be used to set the desired voltage thresholds. Figure 29 illustrates an example of how to
adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the
desired voltage threshold and device part number. TI recommends using the 0.8V voltage threshold device such
as the TPS3703B3080 because of the bypass mode of internal resistor ladder.
For example, consider a 2.0 V rail being monitored (VMON) using the TPS3703B3080 variant. Using Equation 4,
R1 = 15 kΩgiven that R2 = 10 kΩ, VMON = 2 V , and VSENSE = 0.8 V. This device is typically meant to monitor a
0.8 V rail with ±3% voltage thresholds. This means that the device undervoltage threshold (VIT-(UV)) and
overvoltage threshold (VIT-(OV)) is 0.776 V and 0.824 V respectively. Using Equation 4 , VMON = 1.94 V when
VSENSE = VIT-(UV). This can be denoted as VMON-, the monitored undervoltage threshold where the device will
assert a reset signal. Using Equation 4 again, the monitored overvoltage threshold (VMON+) = 2.06 V when VSENSE
= VIT+(OV). If a wider tolerance or UV only threshold is desired, use a device variant shown on Table 7 to
determine what device part number matches your application.
VSENSE = VMON × (R2÷ (R1+ R2)) (4)
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for design specifications. The internal sense resistance (RSENSE) can be calculated by the sense voltage
(VSENSE) divided by the sense current (ISENSE) as shown in Equation 6. VSENSE can be calculated using
Equation 4 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 5.
ISENSE = (VMON – VSENSE) ÷ R1– (VSENSE ÷ R2) (5)
RSENSE = VSENSE ÷ ISENSE (6)
Figure 29. Adjustable Voltage Threshold with External Resistor Dividers