Texas Instruments BQ7961-Q1 Series User manual

User's Guide
BQ7961x-Q1 Design Recommendations for High Voltage
Automotive BMS
Taylor Vogt
ABSTRACT
The BQ79616-Q1 provides high-accuracy cell voltage measurements for 6S to 16S battery modules in <200 µs.
The integrated front end filters enable the system to implement simple, low-cost, differential RC filters on the
cell input channels. The integrated, post-ADC, low-pass filters enable filtered, DC-like, voltage measurements for
better SOC calculation. This device supports autonomous internal cell balancing with temperature monitoring to
auto-pause and resume balancing to avoid an overtemperature condition.
The inclusion of the isolated, bidirectional, daisy chain ports supports both capacitor- and transformer-based
isolation, allowing the use of the most effective components for centralized or distribution architectures
commonly found in the xEV powertrain system. This device also includes eight GPIOs/auxiliary inputs that can
be used for NTC thermistor measurements.
Table of Contents
1 NPN LDO Supply.....................................................................................................................................................................3
2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM............................................................................................4
3 OTP Programming.................................................................................................................................................................. 6
4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)........................................................................................................... 7
5 Bus Bar Support................................................................................................................................................................... 13
6 TSREF.................................................................................................................................................................................... 22
7 General Purpose Input-Output (GPIO) Configurations..................................................................................................... 22
8 Base and Bridge Device Configuration.............................................................................................................................. 25
9 Daisy-Chain Stack Configuration........................................................................................................................................29
10 Multi-Drop Configuration................................................................................................................................................... 36
11 Main ADC Digital LPF......................................................................................................................................................... 38
12 AUX Anti Aliasing Filter (AAF)...........................................................................................................................................38
13 Layout Guidelines...............................................................................................................................................................39
14 BCI Performance.................................................................................................................................................................42
15 Common and Differential Mode Noise..............................................................................................................................42
16 Revision History................................................................................................................................................................. 43
List of Figures
Figure 1-1. Power Supply Schematic.......................................................................................................................................... 3
Figure 2-1. Regulator Connection for Base Device..................................................................................................................... 5
Figure 4-1. Cell Voltage Monitoring............................................................................................................................................. 7
Figure 4-2. Internal CB Diagram (no adjacent cell balancing)..................................................................................................... 8
Figure 4-3. Cell Balancing Resistor Example Calculation........................................................................................................... 9
Figure 4-4. Adjacent Cell Balancing.......................................................................................................................................... 10
Figure 4-5. External FET Cell Balancing....................................................................................................................................11
Figure 4-6. Connecting Fewer Than 16 Cells............................................................................................................................ 12
Figure 5-1. Alternative Bus Bar Connection to the Lower Stack Device....................................................................................14
Figure 5-2. Example of BBP/BBN Connections at Different Module Size..................................................................................15
Figure 5-3. BBP/N Connection With Bus Bar Connected in any Middle VC Channel .............................................................. 16
Figure 5-4. BBP/N Connection With Bus Bar Connected Above Top of a Module ................................................................... 17
Figure 5-5. Bus Bar Connected any Middle Individual VC Channel ......................................................................................... 18
Figure 5-6. Bus Bar Connected Individual VC Channel Above the Top of a Module.................................................................19
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Figure 5-7. Two Bus Bars Connections Using Two Different VC Channel.................................................................................20
Figure 5-8. Multiple Bus Bar Connections Utilizing the BBP/N Pins..........................................................................................21
Figure 5-9. Internal CB Diagram With the Bus Bar Connection.................................................................................................22
Figure 7-1. GPIO Ratiometric Measurement............................................................................................................................. 23
Figure 7-2. Example SPI Master Connections...........................................................................................................................24
Figure 7-3. 8 NTC Thermistors With SPI Slave Device............................................................................................................. 25
Figure 8-1. Communication With the Bridge Device BQ79600-Q1............................................................................................26
Figure 8-2. Using BQ79616-Q1 as Base Device with Isolation Circuit...................................................................................... 26
Figure 8-3. Communication Pings............................................................................................................................................. 27
Figure 8-4. Communication Tones.............................................................................................................................................27
Figure 8-5. Diagram for Ping/Tone Propagation........................................................................................................................ 28
Figure 9-1. Daisy Chain Structure With a Base Device............................................................................................................. 30
Figure 9-2. Daisy Chain Structure With a Bridge Device...........................................................................................................31
Figure 9-3. Components Required for Cap Coupled Daisy Chain in the Same PCB................................................................ 32
Figure 9-4. Components Required for Cap Coupled Daisy Chain in Different PCB.................................................................. 32
Figure 9-5. Components Required for Cap-Choke Daisy Chain With Cabling.......................................................................... 32
Figure 9-6. Components Required for Transformer Coupled Daisy Chain................................................................................ 33
Figure 9-7. Example of Changing Communication Direction in Daisy Chain.............................................................................34
Figure 9-8. Heartbeat or Fault Tone Traveling Direction............................................................................................................35
Figure 9-9. Re-Clocking Bit Compression Example.................................................................................................................. 36
Figure 10-1. Multi-Drop Configuration....................................................................................................................................... 37
Figure 13-1. Grounding Layout Consideration...........................................................................................................................40
Figure 13-2. Separate Ground Plane per Device on the Same PCB.........................................................................................41
Figure 13-3. Daisy Chain Layout Considerations...................................................................................................................... 42
Figure 15-1. XY Caps................................................................................................................................................................ 43
List of Tables
Table 8-1. UART Physical Layer Check List.............................................................................................................................. 29
Table 11-1. Main ADC LPF fcutoff for VCELL and Bus Bar Measurement.................................................................................. 38
Table 12-1. AAF Settling Time................................................................................................................................................... 38
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 NPN LDO Supply
The device is powered by BAT pin and the LDOIN pin, with which the LDOIN pin is regulated by the pre-
regulation circuit form with an external NPN. The device can be powered by a battery module with as low as 9V
(without OTP programming) on the BAT pin.
The BAT and LDOIN pins should be filtered separately from the cell. This is to protect against hotplug, in-rush
current, and other relevant noise. Recommended filters are RBAT = 30 Ω / .25 W, CBAT = 0.01 µF / 100 V for the
BAT pin, two resistors in series for best thermal performance: RNPNC1 = 100 Ω / .75W, RNPNC2 = 200 Ω / .75 W
and capacitor CNPNC = 0.22 µF / 100 V for the collector. LDOIN is the input for the external LDO supply for the
BQ79616-Q1. Figure 1-1 shows the typical circuit.
30 
10 nF
0.1 …F
0.22 …F
RNPN
cell modulecell module
Small current path to BAT
for an Always-on circuit
Q1
Main current path to power the device
BAT
NPNB
LDOIN
Figure 1-1. Power Supply Schematic
The resistor values and NPN can be further optimized from the reference schematic values based on the min
and max module voltages for different projects.
Select the NPN Transistor based on the following criteria:
1. Collector-Emitter Breakdown Voltage (BVCEO) > 80- 100 V (or the module voltage, plus any derating)
2. DC gain (β, or approximately equal to hfe (AC gain)) > 80 at the expected load current
3. Collector-based capacitance < 35 pF at typical base-voltage range
4. Power handling ≥ 1 W
5. Current handling > 100 mA
The resistor RNPNB in Figure 1-1 serves several purposes:
1. Limits inrush current
2. Shares some power dissipation away from the NPN transistor
3. Combine with the CNPN to serve as a filter
RMAX =VBAT min −VLDOOIN max +VCE SAT
ILOAD max (1)
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where
• VBAT(min) is minimum battery module voltage which depends on the number of cells in series and minimum
voltage per cell
• VCE(SAT) = VCE min at VBE(on), from transistor data sheet
• ILOAD is inrush current during startup or maximum active current and any external loading on CVDD
Connect the filter on the LDOIN supply (CLDOIN ) for stability. Use CLDOIN = 0.1 µF with a voltage rating of 10 V.
2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
AVDD, CVDD, and DVDD are regulated outputs derived from the LDOIN input. Each of these regulator outputs
should have a bypass capacitor to avoid noise with a 10% tolerance due to the fact that a larger capacitance
slows startup. REFHP is an internal reference voltage and NEG5V is a regulated voltage provided by an internal
charge pump.
Each regulator provides power for delicate internal subsystems. Do not connect external circuitry or additional
loads to these regulators beyond those described in the data sheet.
The bypass capacitors of the following pins shall be placed as close to the device pins as possible to ensure
proper performance, especially the REFHP capacitor. It is also recommended to help performance with derating
and emissions performance to utilize a small capacitor in parallel with each bypass LDO capacitor of 10-22%.
For example, on CVDD, we recommend both a 22-nF and 100-nF capacitors in parallel with 4.7-μF decoupling
capacitor to help reduce emissions. These need to be designed extremely close to the pins of the IC in the
layout for best effect.
2.1 Base Device
• AVDD is a 5-V regulated output which supplies internal circuits. AVDD must be bypassed to AVSS with a
1-µF/10-V capacitor. Do not connect any additional loads to AVDD.
• CVDD is a power supply for stack communication and tied to internally as I/O power supply. CVDD supplies
the stack daisy chain communication transceiver circuit. Bypass CVDD with a 4.7 µF / 10 V and 100 nF and
22 nF for improved emissions and performance. capacitor to CVSS.
• DVDD is a 1.8-V regulated output that is used to power the digital logic inside the chip. Connect with a
1-μF/10-V capacitor to DVSS. Do not connect any additional loads to DVDD.
• NEG5V is a -5-V supply provided by an internal charge pump. Connect with a 0.1-µF/10-V capacitor to AVSS.
• REFHP is a precision reference output pin. A 1-µF/10-V bypass capacitor must be connected from REFHP to
REFHM directly for proper operation of the part.
• REFHM is the precision reference ground for the internal precision reference. Connect DVSS, CVSS,
ADC_AVSS, REFHM, and AVSS externally. All VSS pins must not be left unconnected.
AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM www.ti.com
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VCC
TX
RX
INB
INC
OUTC INT
MCU
BAT
LDOIN
NPNB
COMHP
COMHN
VC16
VC0
CB0
REFHP
AVDD
REFHM
DVDD
DVSS
CVSS
CVDD
Isolation
Circuit
GND1
GND2 GND
ISO774x
COMLP
COMLN
To COMH of the
Top of Stack
Isolation
circuit
OPTIONAL: Only necessary for ring
architecture applications
NEG5V
AVSS
RX
NFAULT
TX
GPIO2
TSREF
GPIO1
To CVDD
4.7 F
N
N
N
1 F
1 F
N
N
1 F
N
N
0.1 F
N
0.1 F
N
0.22 F
200 100 
30 
10 nF
N
100 
100 
0.47 uF
CELL 16 +
0.47 uF
+
CELL 1
10 
0.47 uF
1 µF
10 k
10 k1
1
1
CELL 16
SYS
OPTIONAL
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
INA OUTB
OUTA
VCC1
100 k100 k
RX
TX
NFAULT
COMLP
COMLN
Leave
Unconnected
For Base Device
To CVDD
1
optional1 HV to LV
Isolation
(Transformer)
COMHP
COMHN
BAT
RS
TX
TX
RX
NFAULT
optional
PMIC
VCC
If communication device is used on the system side
BQ79600
Communication Device
(Base Device)
MCU
If NO (system side) communication device is in use
BBP BBN
To COML of the
North Device
100 
CELL 15 +
100 
0.47 uF
0.47 uF
VC1
10 
CELL 15
10 
0.47 uF
CELL 1
10 
CELL 1-
CB1
CB15
CB16
VC15
AVSS
Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
figure, see data sheet for details.
Figure 2-1. Regulator Connection for Base Device
2.2 Design Summary
• Decouple bypass capacitors on AVDD, CVDD, DVDD, and REFHP pins to the ground plane. (Refer to layout
guidelines for details.)
• Bypass the NEG5V pin to AVSS with a 0.1-µF/10-V capacitor.
• Put all capacitors as close to pins as possible.
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3 OTP Programming
There are memory locations that are programmable in non-volatile memory (NVM) using OTP (One Time
Progammable). The memory space is divided in two groups: factory space and customer space. The factory
space stores the device configurations that are essential for normal operation. This space is not accessible by
the host. The customer space contains the default device settings that the host system can customize for their
application configuration. This space is readable and programmable by the host.
Follow the procedures found below for OTP programming:
1. Unlock the OTP programming.
a. Write the following data to OTP_PROG_UNLOCK1A to OTP_PROG_UNLOCK1D:
i. OTP_PROG_UNLOCK1A <- data 0x02
ii. OTP_PROG_UNLOCK1B <- data 0xB7
iii. OTP_PROG_UNLOCK1C <- data 0x78
iv. OTP_PROG_UNLOCK1D <- data 0xBC
b. Do another write with following data to OTP_PROG_UNLOCK2A to OTP_PROG_UNLOCK2D registers.
i. OTP_PROG_UNLOCK2A <- data 0x7E
ii. OTP_PROG_UNLOCK2B <- data 0x12
iii. OTP_PROG_UNLOCK2C <- data 0x08
iv. OTP_PROG_UNLOCK2D <- data 0x6F
Note
Each block of registers must be written in order (that is A,B,C, then D) with no other writes or
reads between. The best practice is to use the same Write command to update. If there is any
attempt to update the registers out of sequence or if another register is written/read between
writes, the entire sequence must be redone.
2. Check to confirm the OTP unlock procedure is successful.
a. Read to confirm OTP_PROG_STAT[UNLOCK] = 1.
Note
Issuing a Read command after step 1 is allowed, but issuing a [PROG_GO] must be the next write
command after the unlock procedures.
3. Select the proper OTP page and start the OTP programing.
a. To program page1, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x01, OR
b. To program page2, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x03.
4. Wait tPROG for the OTP programming to complete.
5. Check to ensure there is no error during OTP programming. The following bits are expected to be ‘1’ after a
successful OTP programming.
a. OTP_PROG_STAT[DONE] = 1, OTP programming is done. No other bit shall be set in this register.
b. If page 1 is programmed, OTP_CUST*_STAT*[PROGOK], [TRY], [OVOK] and [UVOK] bits shall be ‘1’.
Other bits shall be ‘0’.
c. If page 2 is programmed, OTP_CUST1_STAT[LOADED], [PROGOK], [TRY], [OVOK], and [UVOK] bits
shall be ‘1’. Other bits in OTP_CUST*_STAT shall be '0'.
6. Issue a digital reset to reload the registers with the updated OTP values.
a. CONTROL1[SOFT_RESET] = 1
During the programming procedure, the device performs a programming voltage stability test prior to actually
programming the OTP. If a programming voltage fails the stability test, the device does not set the
OTP_CUST*_STAT[TRY] bit, giving the customer another attempt to program the page again.
If the host incorrectly selected a page for programming, the OTP_PROG_STAT[PROGERR] bit is set. This
indicates that the selected page is not available to be programmed. Select the correct page and retry
programming.
OTP Programming www.ti.com
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4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
Voltage monitoring is done through the VCn pins while cell balancing is done through the CBn pins. Each of the
VCn pins is measured by the main SAR ADC to ensure the most accurate readings. Getting an accurate reading
for these connections is critical to achieve maximum performance so the following design recommendations
should be followed.
4.1 Cell Voltage Sense (VCn)
The VCn pins are the primary inputs for measuring the cell voltages. VC0 is the low side reference to the
negative terminal of the bottom cell and VC16 is the high side reference to the positive terminal of the top cell.
The inputs should be connected to the cells using series resistors to limit current into the pins and protect the IC
from system transients. When fewer than 16 cells are used on the BQ79616-Q1, the lower cells must be used in
order. Unused cell connections can be found in the scenarios shown in Figure 4-1.
Recommended filter capacitor for VCn pins is 0.47 μF/16 V.
A 100 Ω is recommended as a series filter resistor for VCn pins. A 100 Ω is an optimized value to protect VCn
pins from hotplug and provide better filtering. But if another value is considered other than 100 Ω, it should be
simulated for selecting the optimized value for the system.
Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
figure, see data sheet for details.
Figure 4-1. Cell Voltage Monitoring
4.2 Cell Balancing (CBn)
The device integrates internal cell balancing MOSFETs (CBFET) across each CB channel to enable passive
cell balancing. The cell balancing control can be configured in two ways: auto and manual - using the
BAL_CTRL2[AUTO_BAL] bit. To set up cell balancing control, refer to Set Up Cell Balancing section in the
BQ79616-Q1 data sheet.
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The balancing current is determined by the cell voltage, the external resistor in series with the CB pin, and the
internal CBFET RDS(ON). This document will introduce how to select an external resistor to get the desired cell
balancing current.
4.2.1 Non-Adjacent Cell Balancing
Auto balancing control is configured by setting [AUTO_BAL] = 1. In auto balancing control mode, CBFETs are
enabled in an odd and even sequence.
Figure 4-2. Internal CB Diagram (no adjacent cell balancing)
Figure 4-2 shows the cell balancing current path. Cell balancing current (ICB ) is dependent on cell voltage
(VCELL) and the resistance of the balancing path (2 × RCB+ RDS(ON)). The equation is shown in Equation 2. RCB
is the series resistor. RDS(ON) is the resistance of the internal FET when it is on. The higher the total resistance of
the path, the lower the cell balancing current that flows.
To get a target cell balancing current, RCB can be chosen by following two steps.
Step 1 : Select RCB value
The RCB value can be calculated considering the desired cell balancing current at the highest RDS(ON) at the
highest operating temperature using the equation in Equation 3.
Step 2 : Calculate RCB power rating
Power rating for RCB can be calculated with the highest cell balancing current at the minimum RDS(ON). An
example calculation for how to select the value of RCB and power rating to get the desired cell balancing current
is shown in Figure 4-3.
ICB=
VCELL
RDS ON  +  2 × RCB (2)
RCB=1
2VBAT
ICB −RDS ON (3)
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Figure 4-3. Cell Balancing Resistor Example Calculation
Passive balancing dissipates heat to the die, increasing the die temperature as balancing current increases.
Refer to the BQ79616-Q1 data sheet for the recommended maximum balancing current according to the
ambient temperature.
4.2.2 Adjacent Cell Balancing
Manual balancing control is configured by setting [AUTO_BAL] = 0. In manual balancing control mode, the host
can enable two consecutive CBFETs, and a maximum of eight total CBFETs can be enabled (see Figure 4-4).
However, when two adjacent channels are enabled, the balancing current is twice as high or higher than
the non-adjacent channel balancing current. The system designer shall take this into account if adjacent cell
balancing is used. See Equation 4 to select the right adjacent cell balancing series resistor (RCB).
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Figure 4-4. Adjacent Cell Balancing
ICB =
2  ×  VCn
2  × RCB +Rdson QCBn  +  Rdson QCBn − 1(4)
4.2.3 Cell Balancing With External FET
The BQ79616-Q1 can handle 240 mA max at 105°C. Should more current be needed, the cell balancing pins
are able to support an external FET as shown in Figure 4-5. Cell balancing current with external FET can be
calculated using equation below. Details for that configuration can be found in the BQ79616-Q1 data sheet.
There are a few things to keep in mind regarding external balancing. First, the series resistors between the FET
and pin are there to protect the pins during hot plug and the capacitor is there to ensure that the FET does not
turn on during hot plug. Also be aware of the following conditions that should be considered when selecting the
FET.
1. The VDS must be selected based on derating requirements determined by the stack voltage.
2. The VGS threshold must be low enough to turn on with the lowest battery voltage planned for balancing.
The gate of the MOSFET sees half of the battery voltage, so the VGS of the MOSFET must be selected to
provide sufficiently low RDS(ON) at half of the lowest battery voltage.
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Figure 4-5. External FET Cell Balancing
4.3 Using Fewer Than 16 Cells
As stated earlier, the BQ79616-Q1 can support between six and 16 cells. The VCn inputs must be used in
ascending order starting with VC0. See Figure 4-6 scenarios for more information on connecting fewer than 16
cells.
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(c) One PCB for all channels applications ±For BQ79616: Configured for 15 VC and CB
If floating the unused VC and CB pins, capacitors in black corresponding to CB pins need
to be populated, but capacitors and resistors in grey corresponding to VC and CB pins
need to be unpopulated
VC16
VC15
. . .
CB16
CB15
CB14
. . .
(b) One PCB for all channels applications ±For BQ79616: Configured for 16 VC and CB
100 
10 
100 
10 
100 
10 
BAT
30 
VCn
. . .
. . .
100 
+
CELL n
+
CELL15
+
CELL16
+
CELL14
. . .
VC16
VC15
. . .
CB16
CB15
CB14
. . .
100 
10 
100 
10 
100 
10 
BAT
30 
VCn
. . .
. . .
100 
+
CELL n
+
CELL15
+
CELL16
+
CELL14
. . .
(d) One PCB for all channels applications ±For BQ79612: Configured for 12 VC and CB
If floating the unused VC and CB pins, capacitors in black corresponding to CB pins need
to be populated, but capacitors and resistors in grey corresponding to VC and CB pins
need to be unpopulated
VC16/NC
VC15/NC
. . .
CB16/NC
CB15/NC
CB14/NC
. . .
100 
10 
100 
10 
100 
10 
BAT
30 
VCn
. . .
. . .
100 
+
CELL n
+
CELL15
+
CELL16
+
CELL14
. . .
VC14
VC14
VC14/NC
CB13/NC
100 
10 
+
CELL13
VC13/NC
CB12
100 
10 
+
CELL12
VC12
(a) Customized PCB for certain channels applications - Short unused pins to BAT Pin
VC16 (or NC in 14S/12S device)
VCn+1
VCn
. . .
. . .
CB16 (or NC in 14S/12S device)
CBn+1
100 
CELL n
+
BAT
30 
... ...
VC15 (or NC in 14S/12S device)
CB15 (or NC in 14S/12S device)
CBn
10 
. . .
Figure 4-6. Connecting Fewer Than 16 Cells
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4.3.1 Design Summary
• Cell balancing current, ICB, is dependent on cell voltage and resistance of the path.
• The CBn resistor value must be selected considering desired balancing current at the highest ambient
temperature. Use the formula in Equation 3 to calculate the correct resistance.
• A 100-Ω resistor is recommended as a series resistor for VCn pins. A 100 Ω is an optimized value to protect
VCn pins and provide accuracy in cell voltage readings.
• VCn input connections must start with the lowest input, VC0, and then be connected in ascending order.
• CBn inputs used must correspond to the VCn used.
• For more than 240 mA of charging current, use an external FET. Details can be found in the BQ79616-Q1
data sheet.
5 Bus Bar Support
The device supports bus bar measurement in two type of connections. First, the bus bar can be connected to a
dedicated bus bar channel through the BBP and BBN pins. Alternatively, the bus bar can be connected to a VC
channel. This section will introduce both methods of connecting the bus bar and cell balancing handling for each
configuration.
5.1 Bus Bar on BBP/BBN
The device provides a dedicated bus bar channel through the BBP/BBN pins for bus bar connection and
measurement. It is a “floating” channel allowing the bus bar to be connected to any cell except the bottom cell of
a module.
Instead of using the BBP/BBN with the bottom cell (VC1-VC0), the bus bar could be connected to the BBP/BBN
of the lower stack device alternatively as shown as Figure 5-1.
Using the bus bar channel maximizes the use of cell channels in the device across different module size. As
described in Figure 5-2, 4 x 12 cell can be monitored by 3 CMC without wasting any pins while connecting the
bus bar to BBP/BBN.
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Figure 5-1. Alternative Bus Bar Connection to the Lower Stack Device
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The * represents the bus bar location at each module size example.
Figure 5-2. Example of BBP/BBN Connections at Different Module Size
5.2 Typical Connection
With the bus bar connected to BBP/BBN, it is intended to allow a single cell channel (VC channel) to be shared
with a cell + a bus bar (see Figure 5-3 connection). Usually, such a connection introduces additional IR error to
the cell measurement to the system. The dedicated bus bar channel through BBP/BBN supported in the device
allows the host to measure the bus bar voltage to obtain the actual cell measurement.
The connection in Figure 5-3 applies if the bus bar is connected to any middle VC channel. That is, in a single
device, there is a cell connected above and below the BBP/BBN channel. To support hotplug on the bus bar
channel, the device only requires a 400-Ω filter resistor each on BBP/N pins and a 0.47-µF/16-V differential
capacitor across BBP/N pins.
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Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
above figure, see data sheet for details.
Figure 5-3. BBP/N Connection With Bus Bar Connected in any Middle VC Channel
If the bus bar connected to BBP/N is placed at the top of a module (see Figure 5-4 connection), such connection
is the exception in the BBP/N case that a cell channel is NOT being shared. In this connection, actual cell
measurements are made through the VC channels and the host does not require performed addition calculation.
The connection in Figure 5-4 applies if the bus bar is connected to the top of the module, where in a single
device, no cell is connected above the bus bar. To support hotplug on the bar channel, besides the 400-Ω filter
resistor each on BBP/N pins and a 0.47-µF/16-V differential capacitor across BBP/N pins. If the bus bar is used
above the top cell then also an additional 0.47-µF/16-V differential capacitor is needed to connect from BBN to
the top CB pin. This additional capacitor forms a complete capacitor ladder from all the cells in the module to the
bus bar, allowing high spike voltage during hotplug to distributor across the capacitor ladder.
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Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
figure, see data sheet for details.
Figure 5-4. BBP/N Connection With Bus Bar Connected Above Top of a Module
5.2.1 Cell Balancing Handling
Since the bus bar is shared with a cell to a cell channel, there is no special handling on the cell balancing
control. The host shall be aware that additional IR error is introduced to the VCB_DONE detection (through VC
channel) on the shared channel.
5.3 Bus Bar on Individual VC Channel
With the bus bar connected to a VC channel individually, the upper CB pin on that channel shall be left floating
to avoid forward biasing the internal CBFET (see Figure 5-5 connection). This connection applies to the bus bar
connecting to any middle VC channel individually. That is, in a single device, there is a cell connected above and
below the VC channel with the bus bar connected.
To ensure hotplug performance, the CB channel where the bus bar is connected shall still have the differential
capacitor CCB in Figure 5-5 , even if the upper CB pin is floating. This capacitor forms a complete capacitor
ladder from all the cells and the bus bar connected to the device, allowing high voltage spikes during hotplug to
be distributed across the capacitor ladder.
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Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
figure, see data sheet for details.
Figure 5-5. Bus Bar Connected any Middle Individual VC Channel
If the bus bar is connected to above the top of a module to an individual VC channel (see Figure 5-6 connection),
the upper CB pin on that channel shall left floating, but the CB differential capacitor (CCB in Figure 5-6) shall still
be connected. Additionally, an RC filter shall be connected from the top CB pin to the BAT pin. This additional
RC filter (using the same RC values as the other RC filters on the CB pins) is to ensure a complete capacitor
ladder. It is used to distribute high voltage spikes with the same RC constant as the rest of the CB pins during a
hotplug event.
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Note
New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in
figure, see data sheet for details.
Figure 5-6. Bus Bar Connected Individual VC Channel Above the Top of a Module
5.4 Multiple Bus Bar Connections
5.4.1 Two Bus Bar Connections to One Device
Two bus bars can be connected to VC channels individually as shown in Figure 5-7. The first bus bar is
connected to the channel VC4-VC3. CB4 is floated for a cell balancing path. Likewise, the second bus bar is
connected to the channel VC6 -VC7. CB7 is also floated. Each bus bar must be at least two channels apart.
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Figure 5-7. Two Bus Bars Connections Using Two Different VC Channel
5.4.2 Three Bus Bar Connections to One Device
A BQ79616-Q1 supports up to three bus bar connections to a single device. An additional bus bar can be
connected to dedicated bus bar pins (BBP/N) while connecting two bus bars to each VC channel as described
in Figure 5-8. The first and the third bus bars are connected to each channels, VC4-VC3, and VC7-VC6,
respectively. The second bus bar is connected to the dedicated bus bar pins, BBP/N.
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