Texas Instruments ADC3EVM User manual

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ADC3xxxEVM and ADC3xJxxEVM
User's Guide
SLAU579D–June 2014–Revised August 2018
ADC3xxxEVM and ADC3xJxxEVM
This document is a user’s guide for the ADC3xxxEVM and ADC3xJxxEVM. The EVMs provide a platform
for evaluating the ADC3xxx and ADC3xJxx. The ADC3xxx is a dual-channel or quad-channel, 12-bit or 14-
bit, serial LVDS interface analog-to-digital converter (ADC). The ADC3xxx comes with sampling speed
grades of 25 MSPS, 50 MSPS, 80 MSPS, and 125 MSPS. The ADC3xJxx is a dual-channel or quad-
channel, 12-bit or 14-bit, JESD204B-compliant interface ADC. The ADC3xJxx comes with sampling speed
grades of 50 MSPS, 80 MSPS, 125 MSPS, and 160 MSPS. This family of converters requires only a
single 1.8-V supply, provides flexible input clock dividers, and provides internal features for improved 1/f
(ADC32xx, ADC34xx) and SFDR performance. Throughout this document, the abbreviations EVM and
ADC3xxxx, and the term evaluation module are synonymous with the ADC3xxx EVM and ADC3xJxx EVM,
unless otherwise noted.
Contents
1 Introduction ................................................................................................................... 3
1.1 EVM Block Diagram................................................................................................ 4
1.2 EVM Power Supply................................................................................................. 6
1.3 EVM Connectors and Jumpers ................................................................................... 8
1.4 EVM ADC Input Circuit Configurations......................................................................... 12
1.5 EVM DC-Coupling Configuration ............................................................................... 12
2 Software Control............................................................................................................ 15
2.1 Installation Instructions ........................................................................................... 15
2.2 Software Operation ............................................................................................... 15
3 Basic Test Procedure...................................................................................................... 24
3.1 Test Block Diagram with ADC32xx and ADC34xx............................................................ 24
3.2 Test Set-up Connection .......................................................................................... 25
3.3 ADC32/34xx and TSW1400 Setup Guide...................................................................... 25
3.4 Test Block Diagram with ADC32Jxx and ADC34Jxx ......................................................... 27
3.5 Test Set-up Connection (Onboard LMK04828 Clock)........................................................ 28
3.6 ADC32J/34Jxx and TSW14J56 Setup Guide.................................................................. 29
List of Figures
1 Simplified ADC344x EVM Block Diagram................................................................................ 4
2 Simplified ADC34J4x EVM Block Diagram............................................................................... 5
3 Simplified EVM Power Supply ............................................................................................. 6
4 ADC34Jxx EVM Connector and Jumper Locations..................................................................... 8
5 ADC34xx EVM Connector and Jumper Locations ...................................................................... 9
6 ADC3xxxx ADC Input Circuit Options ................................................................................... 12
7 ADC34xx Clock Input Circuit ............................................................................................. 12
8 ADC32xxVM Input Coupling Configuration Resistors ................................................................ 13
9 ADC3xJxx Input Coupling Configuration Resistors ................................................................... 14
10 Common Tab ............................................................................................................... 16
11 ADC32xx Tab............................................................................................................... 17
12 ADC34xx Tab............................................................................................................... 19
13 ADC32Jxx Tab ............................................................................................................. 21
14 ADC34Jxx Tab ............................................................................................................. 23
15 ADC32xx/ADC34xx and TSW1400 Test Setup Block Diagram...................................................... 24

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ADC3xxxEVM and ADC3xJxxEVM
16 Select ADC32xx or 34xx in the HSDC Pro GUI Program............................................................. 25
17 ADC3xxx Operating in 14-Bit Mode at 125 MSPS With a 10-MHz Input Signal................................... 26
18 ADC32Jxx/ADC34Jxx and TSW14J56 Test Setup Block Diagram.................................................. 27
19 Select ADC32Jxx or 34Jxx in the HSDC Pro GUI Program.......................................................... 29
20 ADC32Jxx Operating in 14-Bit Mode at 160 MSPS With a 10-MHz Input Signal ................................. 30
List of Tables
1 ADC3xxx Family of Devices and EVMs .................................................................................. 3
2 Power Supply Options ...................................................................................................... 7
3 ADC3xxxx EVM Connectors.............................................................................................. 10
4 ADC3xxxx EVM Jumper Options......................................................................................... 11
5 ADC3xxxx EVM LED Indicators.......................................................................................... 11
6 ADC32xxEVM AC-DC Coupling Resistor Swap ....................................................................... 13
7 ADC3xJxxEVM AC-DC Coupling Resistor Swap ...................................................................... 14
Trademarks
All trademarks are the property of their respective owners.

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ADC3xxxEVM and ADC3xJxxEVM
1 Introduction
The family of parts and 32 associated EVMs are categorized in Table 1.
Table 1. ADC3xxx Family of Devices and EVMs
Interface Number of Channels ADC Device Number of Bits Maximum MSPS EVM
sLVDS Dual
ADC3221 12 25 ADC3221EVM
ADC3222 12 50 ADC3222EVM
ADC3223 12 80 ADC3223EVM
ADC3224 12 125 ADC3224EVM
ADC3241 14 25 ADC3241EVM
ADC3242 14 50 ADC3242EVM
ADC3243 14 80 ADC3243EVM
ADC3244 14 125 ADC3244EVM
sLVDS Quad
ADC3421 12 25 ADC3421EVM
ADC3422 12 50 ADC3422EVM
ADC3423 12 80 ADC3423EVM
ADC3424 12 125 ADC3424EVM
ADC3441 14 25 ADC3441EVM
ADC3442 14 50 ADC3442EVM
ADC3443 14 80 ADC3443EVM
ADC3444 14 125 ADC3444EVM
JESD204B Dual
ADC32J22 12 50 ADC32J22EVM
ADC32J23 12 80 ADC32J23EVM
ADC32J24 12 125 ADC32J24EVM
ADC32J25 12 160 ADC32J25EVM
ADC32J42 14 50 ADC32J42EVM
ADC32J43 14 80 ADC32J43EVM
ADC32J44 14 125 ADC32J44EVM
ADC32J45 14 160 ADC32J45EVM
JESD204B Quad
ADC34J22 12 50 ADC34J22EVM
ADC34J23 12 80 ADC34J23EVM
ADC34J24 12 125 ADC34J24EVM
ADC34J25 12 160 ADC34J25EVM
ADC34J42 14 50 ADC34J42EVM
ADC34J43 14 80 ADC34J43EVM
ADC34J44 14 125 ADC34J44EVM
ADC34J45 14 160 ADC34J45EVM
There are three package sizes and pinouts for all of these parts. The sLVDS dual devices use a 7-mm ×
7-mm, 48-pin QFN package. The sLVDS quad devices use an 8-mm × 8-mm, 56-pin QFN package. The
dual and quad JESD204B device share the same package using a 7-mm × 7-mm, 48-pin QFN package
The dual ADCs comprise two buffered inputs, two ADC cores, and a common input clock circuit. The quad
ADCs comprise four buffered inputs, four ADC cores, and a common input clock circuit. The sLVDS
versions have a 2-wire interface per ADC (two pairs of p/n signals)—for the dual, this means two sets of 2-
wire interfaces (four p/n pairs), the quad has four sets of 2-wire interfaces (eight p/n pairs). Each of these
2-wire interfaces can be operated in 1-wire mode (14x serialization), or 2-wire mode (7x serialization). For
the 12-bit devices, this equates to 12x and 6x serialization. The JESD204B versions have one lane per
ADC core. For the dual, this means there are two lanes per device, and four lanes per device for the
quad. See the respective device data sheet for more information on sLVDS serialization and JESD204B
lane configurations.

CLK IN
14bit
ADC
14bit
ADC
14bit
ADC
14bit
ADC
Digital
Block
+
Output
Formatter
DCLK
DAB P/M sLVDS
2
DCD P/M sLVDS
2
Power
Supply
Circuits
USB
To
SPI
5V
USB
ADC34xx
CH A
CH B
CH C
CH D
FCLK
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1.1 EVM Block Diagram
Figure 1 and Figure 2 show simplified block diagrams of the default configuration of the EVM. The two or
four analog inputs are supplied to the EVM through a single-ended SMA connection, then transformer
coupled to turn the single-ended signal into a balanced differential signal, and then input to the ADC32xxx
or ADC34xxx. A dual transformer input circuit is used for better phase and amplitude balance of the input
signal than is typically produced by a single transformer input circuit.
Figure 1. Simplified ADC344x EVM Block Diagram

14bit
ADC
14bit
ADC
14bit
ADC
14bit
ADC
Digital
Block
+
Output
Formatter
SYNC
SERDES Lane 0,1
2
SERDES Lane 3,4
2
Power
Supply
Circuits
USB
To
SPI
5V
USB
ADC34Jxx
CLK IN
CH A
CH B
CH C
CH D
SYSREF
LMK04828
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Figure 2. Simplified ADC34J4x EVM Block Diagram
The clock input is supplied by way of a single-ended signal to an SMA connector, and transformer coupled
to produce a differential clock signal for the ADC32/34xx EVM. For the ADC32J/34Jxx EVM, the clock
input can be generated onboard using the LMK04828.
Power to the ADC3xxx EVM is typically supplied from a 5-V bench supply using the onboard barrel
connector and the provided cable, or from an appropriate 5-V, 3-A minimum power brick. All necessary
voltages for the ADC EVM are derived from the 5-V input connection.

GND
5V TPS62080
1
TPS7A4700 1.8V To
ADC
4V to Amp
PWR IN
TPS2400
1
TPS7A4700
Overvoltage
Protection Circuit
DC/DC Converter
Low Noise LDO
Low Noise LDO
ADC32/34xx EVM
GND
5V TPS62080
1
TPS7A4700 1.8V To
ADC
4V to Amp
PWR IN
TPS2400
1
TPS7A4700
Overvoltage
Protection Circuit
DC/DC Converter
Low Noise LDO
Low Noise LDO
ADC32J/34Jxx EVM
TPS62080
1
TPS7A4700 3.3V to
LMK04828
1
Low Noise LDO
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ADC3xxxEVM and ADC3xJxxEVM
1.2 EVM Power Supply
Figure 3 illustrates the power supply options available on the ADC3xxx EVM. Jumpers are used to choose
the power-supply options, with the default jumper positions indicated by the darker portion of the jumper
that represents the presence of the jumper. See Table 2 for jumper and feedback resistor configuration.
Figure 3. Simplified EVM Power Supply

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Table 2. Power Supply Options
Device Description
ADC32xx
JP6: 1-2, JP7: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U4, install R79 for 1.8-V
switcher output
ADC34xx
JP6: 1-2, JP7: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U4, install R79 for 1.8-V
switcher output
ADC342J/34Jxx
JP9: 1-2, JP10: 1-2 Default connection for LDO 1.8-V supply, switch both to 2-3 to use the switcher U8, install R152 for 1.8-V
switcher output
JP12: 1-2, JP13: 1-2 Default connection for LDO 3.3 V for LMK04828 power and onboard SPI/CPLD, switch both to 2-3 to use
U11 switcher output, install R163 for 3.3-V switcher output
The default power path has an efficient, dual-output, DC/DC switching power supply to first step down the
input supplies from 5 V to 4 V, and 2.8 V for the subsequent low-noise LDOs. The 4 V is used by an LDO
to derive 3.3 V for the LMK04828 clock circuits on the ADC3xJxx EVMs. The 2.8 V is used by an LDO to
derive a 1.8-V supply for the ADC and USB circuits.
The low-noise LDOs can be bypassed to allow the DC/DC power supply to directly provide the ADC
power. Note that the feedback resistors of the DC/DC converter must be adjusted accordingly. See the
respective ADC EVM user's guide schematic for details.

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1.3 EVM Connectors and Jumpers
Figure 4 and Figure 5 show the locations of the connectors, jumpers, pushbutton switches, and LEDs.
Figure 4. ADC34Jxx EVM Connector and Jumper Locations

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Figure 5. ADC34xx EVM Connector and Jumper Locations
The EVM has a barrel connector for 5-V power. The SMA connectors connect the ADC input and ADC
clock input to the ADC. Typically, the ADC inputs are transformer-coupled to accept single-ended
connections. The input circuit can be configured to connect to two SMA connectors for differential
signaling, if desired. Table 3 lists the connector information for the ADC3xxxx.

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Table 3. ADC3xxxx EVM Connectors
Device Connector Description
ADC32xx J1 AINP – positive input for A, Ch1 single ended input
J2 AINM – negative input for A, DNI
J3 BINM – negative input for B, DNI
J4 BINP – positive input for B, Ch2 single ended input
J9 CLK_INP – positive CLK input, single ended clock input
J10 CLK_INM – negative CLK input, DNI
J11 SYSREF_INP – positive input for SYSREF frame clock, single ended input
J12 SYSREF_INM – negative SYSREF input, DNI
J13A, B HSMC data connector to TSW1400 evaluation platform
J14 Mini USB connector for SPI control
J15 Power connector for 5-V adapter
ADC34xx J1 AINP – positive input for A, Ch1 single ended input
J2 AINM – negative input for A, DNI
J3 BINM – negative input for B, DNI
J4 BINP – positive input for B, Ch2 single ended input
J5 CINP – positive input for C, Ch3 single ended input
J6 CINM – negative input for C, DNI
J7 DINM – negative input for D, DNI
J8 DINP – positive input for D, Ch4 single ended input
J9 CLK_INP – positive CLK input, single ended clock input
J10 CLK_INM – negative CLK input, DNI
J11 SYSREF_INP – positive input for SYSREF frame clock, single ended input
J12 SYSREF_INM – negative SYSREF input, DNI
J13A, B HSMC data connector to TSW1400 evaluation platform
J14 Mini USB connector for SPI control
J15 Power connector for 5-V adapter
ADC32J/34Jxx J1 AIN_CH-AP – positive input for CHA, single ended input (DNI for ADC32Jxx)
J2 AIN_CH-AM – negative input, (DNI for ADC32Jxx and ADC34Jxx)
J3 BIN_CH-BP – positive input for CHB (CHA input for ADC32Jxx), single ended input
J4 BIN_CH-BM – negative input for CHB (CHA input for ADC32Jxx and ADC34Jxx)
J5 CIN_CH-CP – positive input for CHC (CHB input for ADC32Jxx), single ended input
J6 CIN_CH-CM – negative input for CHC (CHB input for ADC32Jxx and ADC34Jxx)
J7 DIN_CH-DP – positive input for CHD, single ended input (DNI for ADC32Jxx)
J8 DIN_CH-DM – negative input, (DNI for ADC32Jxx and ADC34Jxx)
J9 EXT_ADC_CLK – external ADC clock connection for ADC, if needed
J23 EXT SYSREF+ - external SYSREF connection for ADC, if needed (positive input)
J24 EXT SYSREF– - external SYSREF connection for ADC, if needed (negative input)
J10 LMK_CLKIN – external input clock for LMK use, if needed (for clock distribution mode)
J13 DCLKOUT6P – LMK output test point, positive
J14 DCLKOUT6N – LMK output test point, negative
J15 DCLKOUT7P – LMK output test point, positive
J16 DCLKOUT7N – LMK output test point, positive
J20 5-V input power jack
J18 Mini USB connector for SPI GUI control
J19 CPLD JTAG port

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The onboard jumper options allow configuration of onboard power supplies and ADC options. Many of the
jumper selections that involve dc inputs or static control signals are by way of push-on square post
jumpers. The jumper options listed in Table 4 show the default settings of the jumpers for the EVM as
normally shipped.
Table 4. ADC3xxxx EVM Jumper Options
Device Jumper Description
ADC32xx/ADC34xx JP1 3 pin Jumper – 2-3 Default connection, 1-2 to enable PwDn function
JP2, J3, JP4,JP5 2 pin Jumper - SPI access points, if needed – default should be installed
JP6, JP7 3 pin , default 1-2 to use 1.8V LDO. Use pins 2-3 to bypass 1.8-V LDO
ADC32J/34Jxx JP1 3 pin Jumper – 2-3 Default connection, 1-2 to enable PwDn function
JP2, J3, JP4,JP5 2 pin Jumper - SPI access points, if needed – default should be installed
JP6 2 pin, default is connected for powering onboard VCXO
SJP1 3 pin, DNI, optional for VCXO that require enable on pin 2
JP8 3 pin, default 2-3 for USB SPI selection through CPLD, 1-2 used for FMC
connector based SPI port
JP9, JP10 3 pin, default 1-2 to use 1.8V LDO. Use pins 2-3 to bypass LDO
JP12, JP13 3 pin, default 1-2 to use 3.3V LDO. Use pins 2-3 to bypass LDO
There is a pushbutton on the ADC3xxxx EVM – SW1. At power up, the ADC can either accept a hardware
reset by pressing SW1 or toggling the software reset switch on the ADC3xxxx EVM GUI. The default reset
configuration of the ADC is given in its respective data sheet.
LED D1 on the ADC32/34xxx is lit to show the presence of the 5-V supply voltage to the EVM. On the
ADC32J/34Jxx EVMs, LED D8 is used to show the presence of the 5-V supply voltage to the EVM.
Table 5 lists the description of each LED indicator.
Table 5. ADC3xxxx EVM LED Indicators
Device LED Description
ADC32xx/ADC34xx D1 5-V power indicator
ADC32J/34Jxx D1, D2 Status LED from CLKin SEL0/1 on LMK
D3, D4 Status LED used to indicate LMK Lock or PLL Lock
D5 Status LED for JESD SYNC
D6, D7 Spare LED indicators for FMC connector
D8 5-V power indicator

CLK IN 1:4 0.1PF
0.1PF
:
:
0.1PF
14bit
ADC
Jp
Jn
39nH
39nH
:
:
:
:
0.1PF 0.1PF 0.1PF0.1PF
15:
15:
:
:
10pF10pF
1:1 1:1
VCM
0:
0:
0.1PF
0.1PF
14bit
ADC
Jp
Jn
:
:
:
:
0.1PF 0.1PF 0.1PF0.1PF
:
:
:
:
56nH10pF
1:1 1:1
VCM
10:
10:
0.1PF
0.1PF
Default ±Low Input Frequency
High Input Frequency
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1.4 EVM ADC Input Circuit Configurations
Figure 6 shows the ADC3xxxx ADC input circuit. The default setup has a dual 1:1 impedance ratio
transformer input circuit to achieve better phase and amplitude balance of the input signal than is typically
be produced by a single transformer input circuit.
The default input termination is 50 Ω, which is formed by two 25-Ωresistors connected to the ADC VCM
node. By default, the input circuit is set for operation within the 1st two Nyquist zones. For higher
frequency inputs, use the high-frequency input circuit shown in Figure 6.
Figure 6. ADC3xxxx ADC Input Circuit Options
Figure 7 shows the ADC3xxxx clock input circuit. The clock signal goes through 1:4 impedance ratio
transformer to increase the clock amplitude by two (that is, 1:4 impedance ratio equals to 1:2 voltage
ratio). The two 100-Ωresistors impedance transform back to the primary side as 50-Ωload impedance for
the signal source generator. For ADC evaluation, set the signal generator output to approximately
+10 dBm.
Figure 7. ADC34xx Clock Input Circuit
1.5 EVM DC-Coupling Configuration
The ADC3xxxx EVM family has three different hardware configurations: dual-channel serial LVDS, quad-
channel serial LVDS, and quad-channel JESD204B compliant. The following instructions are a guideline to
enable dc-coupling on the revision B EVM hardware, but can be used as a guide for other EVM revisions.

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1.5.1 ADC32xxEVM
The ADC32xx-EVM boards can be operated in either ac-coupling or dc-coupling mode. To operate the
board in dc-coupling mode, a few modifications must be made. On the back side of the EVM, the
unpopulated pads must be populated with the devices listed on the AMPLIFIER schematic diagram (page
4) of the ADC32XXXEVM-SCH_X.pdf located in the ADC32xx schematic design zip file. This schematic
details the components needed for dc-coupling using the THS4541RGT and all required circuitry.
After the amplifier components are installed on the bottom of the ADC32xx-EVM, the resistors on the top
of the board must be altered to change the output from ac-coupled to dc-coupled. Figure 8 shows the
three shared pad footprints per channel that must be modified. See Table 6 and the ADC32xx design files
to change the appropriate resistors.
Table 6. ADC32xxEVM AC-DC Coupling Resistor Swap
Mode Install Uninstall
AC-Coupled R3, R4, R14R18, R142, R139 R135, R7, R120, R121R138, R20, R144,
R141
DC-Coupled R135, R7, R120, R121R138, R20, R144,
R141 R3, R4, R14R18,R142, R139
Figure 8. ADC32xxVM Input Coupling Configuration Resistors

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1.5.2 ADC3xJxxEVM
The ADC34JxxEVM boards come with the THS4541RGT amplifiers installed. To operate the EVM in dc-
coupled mode, only the topside resistors must be changed. The output channels for dc-coupled signals
are B and C, and the resistors are located near the baluns of the channel, as shown in Figure 9. See
Table 7 and the ADC34JxxEVM design files to change the appropriate resistors.
Table 7. ADC3xJxxEVM AC-DC Coupling Resistor Swap
Mode Install Uninstall
AC-Coupled R217, R258, R226R219, R233, R234 R137, R216, R225, R227R228, R218,
R232,R235
DC-Coupled R137, R216, R225, R227R228, R218,
R232,R235 R217, R258, R226R219, R233, R234
Figure 9. ADC3xJxx Input Coupling Configuration Resistors

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2 Software Control
2.1 Installation Instructions
1. Open the folder named ADC3xxxx_Installer_vxpx (xpx represents the latest version)
2. Run Setup.exe
3. Follow the on-screen instructions
4. Once installed, launch by clicking on the ADC3xxxx_GUI_vxpx program in Start →All Programs →
Texas Instruments ADCs
5. When plugging in the USB cable for the first time, you are prompted by the Found-New-Hardware-
Wizard to install the USB drivers.
a. When a pop-up screen opens, select Continue Downloading.
b. Follow the on-screen instructions to install the USB drivers
c. If needed, access the drivers directly in the install directory
2.2 Software Operation
The software allows programming control of the ADC3xxxx device. The front panel provides a tab for full
programming of the register map of the ADC3xxxx and an advanced tab that allows for custom register
accesses. The GUI tabs provide a convenient and simplified interface to the most used registers of each
device.
2.2.1 ADC3xxxx Control Options
The ADC3xxxx family shares some common registers. These common registers are organized within the
Common tab. Other specific device registers are in specific device tabs for the ADC3xxxx family and the
LMK04828 for the JESD204B devices. For a more detailed description of each register, see the respective
device data sheet.

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2.2.1.1 Common Register Tab
Figure 10 illustrates the following parts of the common tab.
• Software Reset – Resets the registers to default configuration – similar to pressing SW1, self clearing
• Global Power Down – power down the entire chip, default 0
• ADC Standby – All ADCs enter standby mode, default 0
• Configure PwDn pin function – either global power down or ADC standby mode
• Data Format – 0 – 2s Complement, 1- Offset Binary, default 0
• Disable SYSREF BUF – Disable SYSREF Buffer, default 0
• Clk Diver – Internal clock divider to allow harmonic clocking, a higher frequency clock can be provided
to the ADC and then divided down to the desired sample rate.
Figure 10. Common Tab

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2.2.1.2 ADC32xx Tab
Figure 11 illustrates the following parts of the ADC32xx tab.
• Disable Dither CHA – disables the dither circuit, if asserted, dither is on by default
• Disable Dither CHB – disables the dither circuit, if asserted, dither is on by default
• CHA PwDn – power down CHA
• CHB PwDn – power down CHB
• CHA Gain Enable – enable the digital gain block for CHA
• CHB Gain Enable – enable the digital gain block for CHB
• Gain CHA – digital gain setting from 0 dB to 6 dB
• Gain CHB – digital gain setting from 0 dB to 6 dB
• Enable Test Pattern – enable the use of test patterns instead of sample data
• Align Test Data – align all test data on the outputs
• Test Pattern CHA – different available test patterns
• Test Pattern CHB – different available test patterns
• Custom Pattern – 14-bit custom bit pattern used when Custom Pattern is selected
• Disable Chopper CHA – disable the chopper function which shifts 1/f nose to Fs/2, by default it is on
• Disable Chopper CHB – disable the chopper function which shifts 1/f nose to Fs/2, by default it is on
• Low Freq Mode – enable for sampling frequencies lower than 35 MHz
• OVR on LSB – over range indication on LSB, by default it is normal LSB function
• LVDS Swing – control the LVDS swing on the LVDS signals
Figure 11. ADC32xx Tab

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ADC3xxxEVM and ADC3xJxxEVM
2.2.1.3 ADC34xx Tab
• Disable Dither CHA – disables the dither circuit, if asserted, dither is on by default
• Disable Dither CHB – disables the dither circuit, if asserted, dither is on by default
• Disable Dither CHC – disables the dither circuit, if asserted, dither is on by default
• Disable Dither CHD – disables the dither circuit, if asserted, dither is on by default
• CHA PwDn – power down CHA
• CHB PwDn – power down CHB
• CHC PwDn – power down CHC
• CHD PwDn – power down CHD
• CHA Gain Enable – enable the digital gain block for CHA
• CHB Gain Enable – enable the digital gain block for CHB
• CHC Gain Enable – enable the digital gain block for CHC
• CHD Gain Enable – enable the digital gain block for CHD
• Gain CHA – digital gain setting from 0 dB to 6 dB
• Gain CHB – digital gain setting from 0 dB to 6 dB
• Gain CHC – digital gain setting from 0 dB to 6 dB
• Gain CHD – digital gain setting from 0 dB to 6 dB
• Enable Test Pattern – enable the use of test patterns instead of sample data
• Align Test Data – align all test data on the outputs
• Test Pattern CHA – different available test patterns
• Test Pattern CHB – different available test patterns
• Test Pattern CHC – different available test patterns
• Test Pattern CHD – different available test patterns
• Custom Pattern – 14-bit custom bit pattern used when Custom Pattern is selected
• Disable Chopper CHA – disable the chopper function which shifts 1/f nose to Fs/2, default is on
• Disable Chopper CHB – disable the chopper function which shifts 1/f nose to Fs/2, default is on
• Disable Chopper CHC – disable the chopper function which shifts 1/f nose to Fs/2, default is on
• Disable Chopper CHD – disable the chopper function which shifts 1/f nose to Fs/2, default is on
• Low Freq Mode – enable for sampling frequencies lower than 35 MHz
• OVR on LSB – over range indication on LSB, by default it is normal LSB function
• LVDS Swing – control the LVDS swing on the LVDS signals

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SLAU579D–June 2014–Revised August 2018
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ADC3xxxEVM and ADC3xJxxEVM
Figure 12. ADC34xx Tab

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20 SLAU579D–June 2014–Revised August 2018
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Copyright © 2014–2018, Texas Instruments Incorporated
ADC3xxxEVM and ADC3xJxxEVM
2.2.1.4 ADC32Jxx Tab
• Disable Dither CHA – disables the dither circuit if asserted, dither is on by default
• Disable Dither CHB – disables the dither circuit if asserted, dither is on by default
• CHA PwDn – power down CHA
• CHB PwDn – power down CHB
• CHA Gain Enable – enable the digital gain block for CHA
• CHB Gain Enable – enable the digital gain block for CHB
• Gain CHA – digital gain setting from 0 dB to 6 dB
• Gain CHB – digital gain setting from 0 dB to 6 dB
• Enable Test Pattern – enable the use of test patterns instead of sample data
• Align Test Data – align all test data on the outputs
• Test Pattern CHA – different available test patterns
• Test Pattern CHB – different available test patterns
• Custom Pattern – 14-bit custom bit pattern to be used when Custom Pattern is selected
• SerDes Test Pattern – available test patterns at the SerDes block
• Idle Sync Pattern – pattern used for SYNC request (K28.5 default)
• Test Mode Enable – option to enable long test pattern as per clause 5.1.6.3
• Flip ADC Data – normal operation is LSB first, enable for MSB first
• Insert Lane Alignment Chars – option to insert lane alignment chars as per clause 5.3.3.4
• TX Link Config – option to disable ILA when SYNC is de-asserted
• Ctrl K – default is 9 (20x mode), enable to use 0x31 for control
• Ctrl F – default is 2 (20x mode), enable to use 0x30 for control
• Scramble EN – optional scrambler
• Subclass – select subclass, default subclass 2
• Generate SYNC Request – generate Sync request
• JESD Buffer Output Current – change output buffer current, default 16 mA
• Link Layer RPAT – change running disparity in RPAT pattern test mode
• Link Layer Test Mode – generate test pattern per clause 5.3.3.8.2
• Pulse Detect Modes – select different Pulse Detection for SYSREF and SYNC
• Force LMF count – force LMF count
• LMF Count INIT – LMF count INIT
• Release ILA SEQ – delay generation of ILA sequence by 0, 1, 2, 3 MF after CGS