2 TSW4100 Interfaces
2.1 USB Port J26
2.2 USB Connector J25
3 Hardware Configuration
3.1 Power Requirements
3.2 Jumper Settings
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TSW4100 Interfaces
USB port connector J26 provides a PC interface to allow writes and reads between a PC/Laptop and theFPGA and the two GC5016 (SLWS142 ) devices. This interface helps program the two GC5016 deviceswith existing software provided by TI. The parallel port connector provides the same functionality whenconfigured. The default TSW4100 configuration has the USB port enabled and leaves the parallel portdisabled.
USB connector J25 provides a PC interface to allow writes and reads between a PC/Laptop and theDAC5688 and the CDCM7005 (SCAS793 ) devices. There is an option to allow this interface to write to theADS5545 (SLWS180 ) device when configured for serial interface, but the board has this part configuredfor parallel interface mode. With this configuration, the part operation is determined by jumpers.
By using the provided software and on-board jumpers, the TSW4100 can be set up in a variety ofconfigurations to accommodate a specific operation mode. Before starting evaluation, the user shoulddecide on the configuration and make the appropriate connections and load the appropriate parametersfor the GC5016's, DAC5688, ADS5545, and CDCM7005 devices.
The TSW4100 requires 5V-6V DC at approximately 3.0 Amps. The board contains several on-boardregulators that generate the necessary voltages from the 5V-6V DC source The board provides bananajacks J4 (red) and J5 (black) for use with a separate power supply. When using this mode, connect5V-6V DC to J4 and the return to J5.
The board jumper description and default settings are shown in Tables 1, 2, and 3. Details of the softwareoperation modes can be found in the software section of this document. Table 1 ,Table 2 , and Table 3explain the functionality of the board jumpers.
Table 1. Two Pin Jumper List
Jumper Function Installed Removed Default
J7 DUC clock input test point N/A N/A N/AJ10 DDC clock input test point N/A N/A N/AJ18 Sets Parallel port J2 interface device drive mode Open drain Totem pole RemovedJ19 Used to disable VCXO U19 when providing external oscillator at Enables U19 Disables U19 InstalledJ20
Table 2. Three Pin Jumper List
Jumper Function Location: Pins 1-2 Location: Pins 2-3 Default
JP7 CDCM7005 reference select Reference clock provided by J21 Reference clock provided by Y1 2-3or Y2JP5 CDCM7005 complimentary clock input select Clock provided from Input connected to VBB of 1-2VCXO U19 CDCM7005JP6 CDCM7005 clock input select Clock provided from VCXO U19 Input clock provided from J20 1-2JP1 ADS5545 output enable Output enabled Output disabled 1-2SJP3 ADS5545 output clock direction Sends output clock to DDC Sends output clock to FPGA 1-2
SLWU052A – December 2007 – Revised September 2008 TSW4100EVM 5Submit Documentation Feedback
