Texas Instruments TPS7A39EVM-865 User manual

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TPS7A39EVM-865 Evaluation Module
User's Guide
SBVU034–July 2017
TPS7A39EVM-865 Evaluation Module
This user’s guide describes the operational use of the TPS7A39EVM-865 evaluation module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7A3901DSC, low-dropout linear
regulator (LDO). Included in this user’s guide are setup and operating instructions, layout guidelines, a
printed circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM).
Throughout this document, the terms demonstration kit,evaluation board, and evaluation module are
synonymous with the TPS7A39EVM-865.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
TPS7A39 SBVS263

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Contents
1 Introduction ................................................................................................................... 3
1.1 Before You Begin................................................................................................... 3
2 EVM Setup.................................................................................................................... 4
2.1 Input/Output Connectors and Jumper Descriptions............................................................ 4
2.2 TP12 – BUF ......................................................................................................... 5
2.3 Soldering Guidelines ............................................................................................... 6
2.4 Equipment Connection............................................................................................. 6
3 Operation ..................................................................................................................... 6
4 PCB Layout................................................................................................................... 7
5 Schematic..................................................................................................................... 8
6 Bill of Materials............................................................................................................... 9
List of Figures
1 Assembly Layer.............................................................................................................. 7
2 Top Layer Routing........................................................................................................... 7
3 Bottom Layer Routing....................................................................................................... 7
4 TPS7A39EVM-865 Schematic............................................................................................. 8
List of Tables
1 TPS7A39EVM-865 BOM.................................................................................................... 9
Trademarks
All trademarks are the property of their respective owners.

www.ti.com Introduction
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1 Introduction
The Texas Instruments' TPS7A39EVM-865 EVM helps design engineers evaluate the operation and
performance of the TPS7A39 for possible use in their own circuit application. This particular EVM
configuration contains a single TPS7A39 device which integrates a positive and a negative monolithic
bipolar LDO to simplify signal chain dual-rail power-supply design. The regulator is capable of delivering
up to 150 mA per channel to the load. For stability, use a 10-µF (or larger) input and a 10-µF (or larger)
output capacitor for each channel of the TPS7A39.
1.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS7A39EVM-865. Observe all safety precautions.
Warning Warning Hot surface. Contact may cause burns. Do not touch.
CAUTION
The circuit module may be damaged by overtemperature. To avoid damage,
monitor the temperature during evaluation and provide cooling, as needed, for
your system environment.
CAUTION
Some power supplies can be damaged by application of external voltages. If
using more than one power supply, check your equipment requirements and
use blocking diodes or other isolation techniques, as needed, to prevent
damage to your equipment.
CAUTION
The circuit module is not a finished product or electrical appliance. The module
does not contain current or voltage thresholds for circuit protection. It must be
used by qualified personnel with additional equipment for evaluation only.

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2 EVM Setup
This section describes how to properly connect and setup the TPS7A39EVM-865, including the jumpers
and connectors on the EVM board.
2.1 Input/Output Connectors and Jumper Descriptions
2.1.1 J1 – OUTP_S
Positive output sense test point. An SMA connector (not provided) can be added here.
2.1.2 J2 – OUTP
Regulated positive output voltage connector.
2.1.3 J3 – INP_S
Positive input sense test point. An SMA connector (not provided) can be added here.
2.1.4 J4 – INN_S
Negative input sense test point. An SMA connector (not provided) can be added here.
2.1.5 J5 – GND
Positive output ground return connector.
2.1.6 J6 – GND
Positive input ground return connector.
2.1.7 J7 – OUTN_S
Negative output sense test point. An SMA connector (not provided) can be added here.
2.1.8 J8 – INP
Positive input voltage power-supply connector. Keep the positive input lead as short as possible to
minimize input inductance.
2.1.9 J9 – Positive LDO Resistor Divider
TPS7A39EVM-865 is prepopulated with four resistor dividers for the positive output voltage. Place a short
to select the desired output voltage from the silkscreen.
2.1.10 J10 – INN
Negative input voltage power-supply connector. Keep the negative input lead as short as possible to
minimize input inductance.
2.1.11 J11 – OUTN
Regulated negative output voltage connector.
2.1.12 J12 – GND
Negative input ground return connector.
2.1.13 J13 – GND
Negative output ground return connector.

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2.1.14 J14 – NR/SS
TPS7A39EVM-865 is prepopulated with two NR/SS capacitors. Select the desired value.
2.1.15 J15 – EN
Output enable. To enable the outputs, connect a jumper to short INP to EN.
2.1.16 J16 – Negative LDO Resistor Divider
TPS7A39EVM-865 is prepopulated with five options for the negative output voltage. Place a short to
select the desired output voltage from the silkscreen.
2.1.17 TP1 – OUTP_S
Positive output sense test point.
2.1.18 TP2 – INP_S
Positive input sense test point.
2.1.19 TP3 – FBP_S
Positive feedback sense test point.
2.1.20 TP4 – INN_S
Negative input sense test point.
2.1.21 TP5 – NR/SS
NR/SS sense test point.
2.1.22 TP6 – FBN_S
Negative feedback sense test point.
2.1.23 TP7 – OUTN_S
Negative output sense test point.
2.1.24 TP8 – EN_S
Enable sense test point.
2.1.25 TP9 – GND
Ground test point.
2.1.26 TP10 – GND
Ground test point.
2.1.27 TP11 – GND
Ground test point.
2.2 TP12 – BUF
Buffer pin test point.

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2.3 Soldering Guidelines
To avoid damaging the integrated circuit (IC), use a hot-air system for any solder rework to modify the
EVM for the purpose of repair or other application reasons.
2.4 Equipment Connection
Use the following guidelines when connecting the equipment:
1. Set the positive input supply to 33 V (max), and turn the power supply off.
2. Set the negative input supply to –33 V (min), and turn the power supply off.
3. Connect the positive voltage lead from the input power supply to INP at the J8 connector of the EVM.
4. Connect the negative voltage lead from the input power supply to INN at the J10 connector of the
EVM.
5. Connect the ground lead from the input power supply to GND at the J6 and J12 connector of the EVM.
6. Connect a 0 mA to 150 mA load between OUTP and GND.
7. Connect a 0 mA to 150 mA load between OUTN and GND.
8. Disable the output by floating J15.
3 Operation
Operate the EVM using the following steps:
1. Turn on the power supplies.
2. Enable the output by jumping J15, the EN pin, to VIN.
3. Vary the respective load and input voltage, as necessary, for test purposes.

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4 PCB Layout
Figure 1 to Figure 3 illustrate the PCB layout for this EVM.
Figure 1. Assembly Layer Figure 2. Top Layer Routing
Figure 3. Bottom Layer Routing

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5 Schematic
Figure 4 is the schematic for this EVM.
Figure 4. TPS7A39EVM-865 Schematic

www.ti.com Bill of Materials
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6 Bill of Materials
The BOM for this EVM is shown in Table 1.
(1) These assemblies are ESD sensitive, observe ESD precautions.
(2) These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
(3) These assemblies must comply with workmanship standards IPC-A-610 Class 2.
(4) Unless otherwise noted in the Alternate Part Number or Alternate Manufacturer columns, all parts may be substituted with equivalents.
Table 1. TPS7A39EVM-865 BOM(1)(2)(3)(4)
Designator Qty Value Description Package
Reference Part Number Manufacturer Alternate Part Number Alternate Manufacturer
!PCB1 1 Printed Circuit Board PWR865 Any - -
C1, C3, C8, C12 4 10uF CAP, CERM, 10 µF, 50 V, + /- 10%, X7 S, 1210 1210 C3225X7 S1 H106K250AB TDK
C6 1 0.1uF CAP, CERM, 0.1 µF, 100 V, + /- 10%, X7 S, AEC-Q200
Grade 1, 0603 0603 CGA3E3X7 S2A104K080AB TDK
C7, C10, C11 3 0.01uF CAP, CERM, 0.01 µF, 50 V, + /- 5%, C0 G/NP0, 0603 0603 C1608 NP01 H103 J080AA TDK
J2, J8 2 Standard Banana Jack, Insulated, Red 6091 6091 Keystone
J5, J6, J12, J13 4 Standard Banana Jack, Insulated, Black 6092 6092 Keystone
J9 1 Header, 2.54 mm, 4x2, Gold, SMT Header, 2.54
mm, 4x2, SMT TSM-104-01-L-DV Samtec
J10, J11 2 BANANA JACK, 15A, Insulated, Nylon, Yellow 940x438x438 mil 108-0907-001 Emerson Network Power
J14 1 Header, 100 mil, 3x1, Gold, SMT Samtec_TSM-
103-01-X-SV TSM-103-01-L-SV Samtec
J15 1 Header, 2.54 mm, 2x1, Gold, R/A, SMT Header, 2.54 mm, 2x1, R/A,
SMT 0878980204 Molex
J16 1 Header, 2.54 mm, 5x2, Gold, SMT Header, 2.54
mm, 5x2, SMT TSM-105-01-L-DV Samtec
R1 1 76.8k RES, 76.8 k, 1%, 0.1 W, 0603 0603 CRCW060376K8FKEA Vishay-Dale
R2 1 21.5k RES, 21.5 k, 1%, 0.1 W, 0603 0603 CRCW060321K5FKEA Vishay-Dale
R3 1 13.0k RES, 13.0 k, 1%, 0.1 W, 0603 0603 CRCW060313K0FKEA Vishay-Dale
R4 1 10.2k RES, 10.2 k, 1%, 0.1 W, 0603 0603 CRCW060310K2FKEA Vishay-Dale
R5 1 249k RES, 249 k, 1%, 0.1 W, 0603 0603 CRCW0603249KFKEA Vishay-Dale
R6, R9 2 280k RES, 280 k, 1%, 0.1 W, 0603 0603 CRCW0603280KFKEA Vishay-Dale
R7 1 0 RES, 0, 5%, 0.1 W, 0603 0603 ERJ-3 GEY0R00 V Panasonic
R8 1 100k RES, 100 k, 1%, 0.1 W, 0603 0603 CRCW0603100KFKEA Vishay-Dale
R10 1 66.5k RES, 66.5 k, 1%, 0.1 W, 0603 0603 CRCW060366K5FKEA Vishay-Dale
R11 1 22.1k RES, 22.1 k, 1%, 0.1 W, 0603 0603 CRCW060322K1FKEA Vishay-Dale
R12 1 14.0k RES, 14.0 k, 1%, 0.1 W, 0603 0603 CRCW060314K0FKEA Vishay-Dale
R13 1 11.0k RES, 11.0 k, 1%, 0.1 W, 0603 0603 CRCW060311K0FKEA Vishay-Dale
SH-J1, SH-J2, SH-
J3 3 1x2 Shunt, 100 mil, Gold plated, Black Shunt 969102-0000-DA 3M SNT-100-BK-G Samtec

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Table 1. TPS7A39EVM-865 BOM(1)(2)(3)(4) (continued)
Designator Qty Value Description Package
Reference Part Number Manufacturer Alternate Part Number Alternate Manufacturer
TP1, TP2, TP3,
TP4, TP5, TP6,
TP7, TP8, TP9,
TP10, TP11, TP12
12 Test Point, Compact, SMT Testpoint_Keysto
ne_Compact 5016 Keystone
U1 1 Wide-VIN (±33 V), 150-mA, Spilt-Rail Output, Positive and Negative LDO Voltage Regulator with Startup
Tracking, DSC0010 J DSC0010 J TPS7A3901DSC Texas Instruments
C2, C4, C9, C13 0 10uF CAP, CERM, 10 µF, 25 V, + /- 20%, X5R, 0603 0603 C1608X5R1E106M080AC TDK
C5 0 0.01uF CAP, CERM, 0.01 µF, 50 V, + /- 5%, C0 G/NP0, 0603 0603 C1608 NP01 H103 J080AA TDK
C14 0 0.1uF CAP, CERM, 0.1 µF, 100 V, + /- 10%, X7 S, AEC-Q200
Grade 1, 0603 0603 CGA3E3X7 S2A104K080AB TDK
D1, D2 0 60 V Diode, Schottky, 60 V, 1 A, SOD-123 SOD-123 RB160M-60 TR Rohm
FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or mount. Fiducial N/A N/A
J1, J3, J4, J7 0 Connector, SMA Jack, Vertical, Gold, SMD SMA 142-0711-201 Emerson Network Power