Texas Instruments ADS1278V2EVM-PDK User manual

EVM User's Guide: ADS1278V2EVM-PDK
ADS1278EVM-PDK Evaluation Module
Description
The ADS1278 evaluation module (EVM) is a platform
for evaluating the performance of the ADS1278,
which is a 24-bit, 8-channel simultaneous-sampling
delta-sigma (ΔΣ) analog-to-digital converter (ADC).
The ADS1278 combines high-precision industrial
measurement with excellent dc and ac specifications,
providing a usable signal bandwidth of up to 90% of
the Nyquist rate with less than 0.005dB of passband
ripple. The ADS1278 EVM eases the evaluation of
the device with hardware, software, and computer
connectivity through the universal serial bus (USB)
interface.
Get Started
1. Order the EVM from ti.com.
2. Download the latest software from ADS1278EVM-
PDK.
3. Launch the ADS1278 EVM GUI from the start
menu.
4. Power the ADS1278 EVM from a 6V supply.
5. Connect the ADS1278 EVM to the PHI controller
board and connect the PHI board to the computer
running the ADS1278 EVM GUI.
Features
• Hardware and software required for diagnostic
testing as well as accurate performance evaluation
of the ADS1278
• The PHI controller provides a convenient
communication interface to the ADS1278 over
USB 2.0 (or higher) for digital input and output
• Easy-to-use evaluation software for 64-bit
Microsoft® Windows® 10 operating system
• The software suite includes graphical tools for data
capture, histogram analysis, and spectral analysis.
This suite also has a provision for exporting data to
a text file for post-processing
Applications
• Vibration/modal analysis
•Multi-channel data acquisition
• Acoustics/dynamic strain gauges
•Pressure sensors
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1 Evaluation Module Overview
1.1 Introduction
The ADS1278EVM-PDK is a platform for evaluating the performance of the ADS1278, a 24-bit, 8-channel,
simultaneous sampling delta-sigma ADC. The evaluation kit includes the ADS1278 EVM board and the precision
host interface (PHI) controller board that enables the accompanying computer software to communicate with the
ADC over the USB for data capture and analysis. The ADS1278 EVM board includes the ADS1278 and all the
peripheral analog circuits and components required to evaluate the performance of the ADS1278. The PHI board
provides a communication interface from the ADS1278 EVM to the computer through a USB port.
This user's guide includes complete circuit descriptions, schematic diagrams, and a bill of materials. Throughout
this document, the abbreviation EVM and the term evaluation module are synonymous with the ADS1278 EVM.
Note
The ADS1278 EVM and software can also support the 4-channel ADS1274 device. However, the user
must manually remove the ADS1278 and install the ADS1274. See Section 4.2 for the location of the
ADS1278 on the EVM. The ADS1274 is not discussed further in this document.
1.2 Kit Contents
The ADS1278EVM-PDK includes:
1. The PHI controller board.
2. The ADS1278 EVM board which includes the ADS1278 and peripheral circuitry required for device operation
and communication with the PHI board.
3. An A-to-Micro-B USB cable for communication between the PHI board and the EVM GUI.
4. The EVM GUI, which can be found online in the EVM tool folder.
1.3 Specification
The ADS1278EVM-PDK uses three different input structure designs to allow for easy evaluation of the ADS1278
performance. The first two channels enable differential measurements using SubMiniature A (SMA) connectors,
the second two channels enable single-ended measurements using a single SMA connector each, and the
remaining four channels are routed to pin headers that can be used to input differential signals. Fully-differential
amplifier circuits drive the first four channels, while the remaining four channels are connected directly to the
ADS1278 through an input filter.
The EVM requires an external 6V power source to power three ultra-low noise TPS7A4700 low-dropout (LDO)
linear regulators that supply the ADS1278 voltage rails. The EVM supports the use of an external clock, as well
as setting the MODE, FORMAT, and CLKDIV pins with jumpers.
The EVM can also be configured by populating and depopulating the appropriate pin headers and zero-ohm
jumper resistors to manually measure or set the Vcm, Vref, and shutdown pins of the ADS1278 EVM.
Control and monitoring of the communications between the EVM and the PHI controller board is provided using
the pin header test points. Likewise, monitoring the analog input signals and power supply rails is supported
using the test points built into the board.
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VREFP VREFN AVDD DVDD
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
PWDN[8:1]
CLKDIV
Control
Logic
SPI
and
Frame-
Sync
Interface
IOVDD
DGNDAGND
DRDY/FSYNC
SCLK
DOUT[8:1]
DIN
Input2
Input1
Input4
Input3
Input6
Input5
Input8
Input7
DS
DS
DS
DS
DS
DS
DS
DS
PWDN[4:1]
ADS1278
Four
Digital
Filters
AVDD DVDD
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
CLKDIV
Control
Logic
SPI
and
Frame-
Sync
Interface
IOVDD
DGNDAGND
DRDY/FSYNC
SCLK
DOUT[4:1]
DIN
ADS1274
MODE[1:0]
MODE[1:0]
Eight
Digital
Filters
VREFP VREFN
Input2
Input1
Input4
Input3
DS
DS
DS
DS
Figure 1-1. ADS1274 and ADS1278 Block Diagram
1.4 Device Information
The ADS1278 is a 24-bit, 8-channel, simultaneous sampling delta-sigma ADC with data rates up to 144
kilosamples per second.
Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large pass-band
droop. As a result, these delta-sigma ADCs have limited signal bandwidth and are the best choice for low-
frequency measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the
offset and drift specifications are significantly weaker than respective industrial counterparts. The ADS1278
combines these types of converters, allowing high-precision industrial measurement with excellent dc and ac
specifications.
The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard
decimation filter suppresses modulator and signal out-of-band noise. This ADC provides a usable signal
bandwidth up to 90% of the Nyquist rate with less than 0.005dB of passband ripple.
Four operating modes allow for optimization of speed, resolution, and power. All operations are controlled
directly by pins; there are no registers to program. The device is fully specified over the extended industrial
range (–40°C to +105°C) and is available in an HTQFP-64 PowerPAD™ package.
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2 Hardware
The ADS1278 EVM is designed for easy interfacing with analog input sources. This section covers the details of
the front-end circuit, including jumper configuration for different input test signals and board connectors for signal
sources.
2.1 EVM Analog Input options
The ADS1278 EVM board offers different analog input circuits, including Section 2.1.1, Single-Ended SMA
Inputs, and Undriven Input Pins.
2.1.1 Fully Differential SMA Inputs
For best performance, connect differential analog input signals through the SMA connectors on channels 1 and
2, as shown in Figure 2-1. Alternatively, headers are provided to directly connect inputs for dc measurements, or
where best ac performance is not needed. A possibility is to use the fully-differential SMA inputs as single-ended
inputs. Connect the single-ended input to either the AINP or AINN SMA connector, then use the supplied shunt
to connect the unused input to GND via the header. The input driver circuits use the THS4551 fully-differential
amplifier in a low pass, unity-gain configuration with an additional single-pole RC filter at the output. Multiple
passive components around the amplifier are intentionally left uninstalled to give users the flexibility to customize
the input drive circuit for specific application.
AINP1
GND
AINN1
GND
1
2 3 4 5
AINP1
142-0701-801
1
2 3 4 5
AINN1
142-0701-801
GND
AINP3
GND
1
2 3 4 5
AINP3
142-0701-801
1
2
J13
0
R101
AINN3
GND
4
1
2
3
J11
TSW-104-07-G-S
Figure 2-1. SMA Input Connections
2.1.2 Single-Ended SMA Inputs
Connect single-ended input signals through the SMA connectors on channels 3 and 4 . These channels also
feature headers that can be used to short the inputs to ground using shunt connectors. The input driver circuits
are identical to the ones used in the fully differential SMA input circuits on channels 1 and 2 except the negative
inputs are grounded as shown in Figure 2-1.
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2.1.3 Differential Input Pins
Connect Differential input signals directly to the ADC on channels 5-8 using the input headers. These channels
are connected to the device pins though a small charge bucket filter to counteract the effects of the inrush
current on the device. Similar to Section 2.1.1, apply single-ended signals to these headers by grounding one
of the input pins. Figure 2-2 shows an example of the undriven input pin headers and associated charge bucket
circuitry for channel 5.
CHAN_P5
CHAN_N5
AINP5
AINN5
GND
4
1
2
3
J15
TSW-104-07-G-S
220pF
C83
0.01uF
C85
0.1%100
R125
0.1%100
R127
220pF
C87
Figure 2-2. Unbuffered Input Connections
2.2 ADC Input Drive Amplifiers
Figure 2-3 shows the fully differential amplifier (THS4551) circuit used to drive the ADC. The input applied to
AINP and AINN must be a low-distortion differential signal. Pin 7 on U13 (VOCM) controls the common-mode
output for the amplifier, and is set by the ADS1278 VCOM output (pin 55). The feedback network includes a low
pass filter (R74, R78, R94, R91, C36, and C52). The amplifier output connects to an RC filter that connects to
the ADC input (R37, R43, C30, C26, and C32). The amplified configuration has several do-not-populate (DNP)
components that provide flexibility, but are not required for good performance. The amplifier power supplies are
connected by default to the AVDD and GND supplies that are also used for the ADC.
IN-
6OUT+ 9
PD
3
VOCM
7
OUT- 1 IN+
4
VS+
10
VS- 5
NC 2
NC 8
THS4551IRUNR
U13
AVDD
470pF
C44
270pF
C38
1000pF
C45
270pF
C50
AINN1
AINP1
GND
GND
0
R86
GND
0
R72
R96
VCOM
/THSPD
0
R79
0
R92
1.00k
R91
1.00k
R78
50V
470pF
C36
50V
470pF
C52
1.00k
R74
1.00k
R94
50V
220pF
C40
50V
220pF
C48
25V
0.01uF
C46
10.0
R82
10.0
R87
15.0
R81
15.0
R90
CHAN_N1
CHAN_P1
Figure 2-3. Input Drive Amplifier Circuit
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2.3 VCOM Buffer
Figure 2-4 shows the buffer circuit for the ADC VCOM signal. The output of the VCOM buffer connects to the
VOCM signal of the input driver amplifiers. The J1 VCOM header pins (depopulated by default) can also be used
to provide an alternate source for VCOM by depopulating resistor R5. Jumper J1 can also be used to connect
the VCOM signal to an external piece of test equipment to set the common-mode voltage. A common use case
is to connect this signal to the Audio Precision SYS-2722 to set the signal generator's common-mode output.
AVDD
25V
0.1µF
C8
GND
GND
V+
8V- 4
OPA2320AQDGKRQ1
U2C
25V
0.1µF
C9
GND
1
2
J1
VCOM
2
3
1
A
OPA2320AQDGKRQ1
U2A
49.9R5
GND
VCOM_ADC
Figure 2-4. VCOM Buffer Circuit
2.4 ADC Connections and Decoupling
The circuit shown in Figure 2-5 shows all connections to the ADS1278 (U1). Each analog power supply
connection has a 100nF decoupling capacitor and each power supply has a 10µF decoupling capacitor. These
capacitors are physically close to the device and have a good connection to the GND plane. Also, each digital
input has a 50Ω series resistor. These resistors smooth the edges of the digital signals so that the signals have
minimal overshoot and ringing. Although not strictly required, these components can be included in final designs
to improve digital signal integrity.
25V
0.1µF
C2
25V
0.1µF
C3
25V
0.1µF
C4
25V
0.1µF
C5
GND
AVDD
DVDD
GND
49.9R7
IOVDD
GND
VCOM_ADC
CHAN_P1
CHAN_N1
CHAN_P2
CHAN_N2
CHAN_P3
CHAN_N3
CHAN_P4
CHAN_N4
CHAN_P5
CHAN_N5
CHAN_P6
CHAN_N6
CHAN_P7
CHAN_N7
CHAN_P8
CHAN_N8
49.9R8
49.9R9
49.9R10
49.9R11
49.9R12
49.9R13
49.9R14
/PWDN1
/PWDN2
/PWDN3
/PWDN4
/PWDN5
/PWDN6
/PWDN7
/PWDN8
CONTROL.MODE0
CONTROL.MODE1
CONTROL.FORMAT0
CONTROL.FORMAT1
CONTROL.FORMAT2
GND
CONTROL.CLKDIV
49.9R4
49.9R6
49.9R16
CLK
1.00k
R19
49.9
R15
DVDD_ADC
AVDD_ADC
IOVDD_ADC
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DATA
DOUT1
DATA
CONTROL
CLKDIV
MODE0
FORMAT0
MODE1
FORMAT1
FORMAT2
CONTROL
VREFP
GND
CONTROL.CLKDIV
AVDD
5
AVDD
44
AVDD
53
AVDD
60
DVDD
26
IOVDD
22
IOVDD
23
AINP1
3
AINP2
1
AINP3
63
AINP4
61
AINP5
51
AINP6
49
AINP7
47
AINP8
45
AINN1
4
AINN2
2
AINN3
64
AINN4
62
AINN5
52
AINN6
50
AINN7
48
AINN8
46 TEST0 8
TEST1 9
DOUT1 20
DOUT2 19
DOUT3 18
DOUT4 17
DOUT5 16
DOUT6 15
DOUT7 14
DOUT8 13
DRDY/FSYNC 29
PWDN1 42
PWDN2 41
PWDN3 40
PWDN4 39
PWDN5 38
PWDN6 37
PWDN7 36
PWDN8 35
SYNC 11
CLK 27
CLKDIV 10
DIN 12
SCLK 28
VCOM
55
VREFN
57 VREFP
56 FORMAT0 32
FORMAT1 31
FORMAT2 30
MODE0 34
MODE1 33
AGND 6
AGND 43
AGND 54
AGND 58
AGND 59
DGND 7
DGND 21
DGND 24
DGND 25
PowerPAD 65
ADS1278IPAPR
U1
VREFN
/DRDY_FSYNC
SCLK
DIN
/SYNC
IO
IO
0
R1
0
R3
0
R2
10V
10µF
C7
10V
10µF
C6
10V
10µF
C1
Figure 2-5. ADS1278 Connections and Decoupling
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2.5 Digital Interfaces
As noted in Section 1.1, the EVM interfaces with the PHI and communicates with the computer over the USB.
The PHI communicates with two devices on the EVM: the ADS1278 (over SPI or frame-sync) and the EEPROM
(over I2C). The EEPROM comes preprogrammed with the information required to configure and initialize the
ADS1278 platform. When the hardware is initialized, the EEPROM is no longer used. The ADS1278 uses SPI
serial communication in mode 1 (CPOL = 0, CPHA = 1) or frame-sync mode. Header J6, shown in Figure 2-6,
provides test points to measure the digital signals. The configuration inputs, which are configurable by the PHI
interface by default but can also be configured by placing jumpers on J3 and J4, are also shown in Figure 2-6.
GND
GND
ID_PWR
EVM_ID_SCL
EVM_ID_SDA
GND
A0
1
A1
2
A2
3
VSS
4SDA 5
SCL 6
WP 7
VCC 8
U8
BR24G32FVT-3AGE2
10.0k
R43
25V
0.1µF
C24
25V
0.1µF
C22
EEPROM_WP
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J6
TSW-108-07-G-D
GND
DATA.DOUT4
DATA.DOUT3DATA.DOUT2
DOUT1_PHICLK
IO.SCLKIO./DRDY_FSYNC
IO.DIN
DATA.DOUT5
DATA.DOUT6 DATA.DOUT7
DATA.DOUT8
IO./SYNC EEPROM_WP
GND
100kR27
100kR29
100kR31
100kR33
100kR35
100kR37
CONTROL.MODE0
CONTROL.MODE1
CONTROL.FORMAT0
CONTROL.FORMAT1
CONTROL.FORMAT2
CONTROL.CLKDIV
IOVDD_ADC
1 2
3 4
5 6
7 8
9 10
11 12
J4
TSW-106-07-G-D
GND GND
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND
MP1
GND
MP2 GND MP3
GND MP4
J5
QTH-030-01-L-D-A
ID_PWR
GND
EVM_ID_SCL
EVM_ID_SDA
EEPROM_WP
DIN
/DRDY_FSYNC
/SYNC
SCLK
IO
IO
IO
MODE0
FORMAT0
CLKDIV
MODE1
FORMAT1
FORMAT2
CONTROL
CONTROL
DATA.DOUT1
IO./SYNC
IO.DIN
MCLK_OUT
MCLK_IN
IO./DRDY_FSYNC
DATA.DOUT2
DATA.DOUT3
DATA.DOUT4
DATA.DOUT5
DATA.DOUT6
DATA.DOUT7
DATA.DOUT8
DATA
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT1
DATA
DATA
DATA.DOUT1
IO.SCLK
PHI_CLK
MCLKo
MCLK_OUT
CAP_CLK
CAPCLK
CAP_CLK
100kR25
100kR26
100kR28
100kR30
100kR32
100kR34
100kR36
100kR38
GND
/PWDN1
/PWDN2
/PWDN3
/PWDN4
/PWDN5
/PWDN6
/PWDN7
/PWDN8
IOVDD_ADC
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
16
18
J3
TSW-109-07-G-D
100kR24
/THSPD AVDD
Figure 2-6. Digital Interface Connections
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2.6 Onboard Voltage Reference
Figure 2-7 shows the REF5025 configuration. The OPA2320 buffer circuit drives the ADS1278 reference input
pins. The reference voltage can optionally be provided through the J2 VREFext header pins (depopulated by
default) by depopulating jumper resistor R22. Create a low pass filter by replacing the components connecting
the buffer to the ADS1278 (R18, C10, R20). Use test points VREFP and VREFN to read back the reference
voltage provided to the filter.
DNC 1
NC 7
DNC 8
REF5025AIDGKT
U3B
VREFP
GND
1
2
J2
VREFP
VIN
2
TEMP
3GND 4
TRIM/NR 5
VOUT 6
REF5025AIDGKT
U3A
1uF
C12
1uF
C15
10V
10µF
C13
100 µF
C16
AVDD
150nFC11
1.00kR23
2.00kR17
47.0R21
25V
0.1µF
C14
5
6
7
B
OPA2320AQDGKRQ1
U2B
0
R18
0
R20 VREFN
10V
10µF
C10
0
R22
GND
VREFext
VREFN
Figure 2-7. Reference Voltage Circuit
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2.7 Clock Sources
The onboard PLL of the PHI controller board provides the default clock for the ADS1278 EVM. This clock is
configurable for arbitrary frequencies using the Clock Settings dialogue of the GUI. The ADS1278 EVM can
also be configured to use an onboard hardware oscillator or an external clock. Figure 2-8 shows the different
on-board clock options for the ADS1278 EVM.
GND
1
2 3 4 5
J7
IOVDD
25V
0.1µF
C23
GND
GND
CLK
1
2
3
JP2
TSM-103-01-L-SV
OSC DISABLE
100k
R42
GND
1
2
3
JP1
TSM-103-01-L-SV
OSC ENABLE
EVM CLK
PHI CLK
MCLK_IN CLK49.9R41
VCC
4
ST
1
OUT 3
GND 2
Y1
SG-210STF27.0000ML0
PHI_CLK
Alternate: LMK6CA027000CDLFR
Figure 2-8. Clock Source Circuit
When jumper JP2 is in the default position (1-2), the CLK pin on the ADS1278 is routed to the PHI clock output.
Change the shunt on jumper JP2 to position 2-3 if the ADS1278 EVM is used with the onboard clocking options.
Moving jumper JP1 to position 1-2 disables the local 27MHz oscillator (Y1) on the ADS1278 EVM, allowing an
external clock supplied on the SMA connector (J7).
To use an external clock source, apply a CMOS square-wave signal with an amplitude equal to IOVDD (3.3 V)
and a frequency within the specified range of the ADS1278. Additionally, the appropriate clock frequencies must
be programmed into the GUI Clock Settings dialogue to verify the communication speed is correct.
Note
Writing the same frequency repeatedly to the onboard PLL of the PHI controller sometimes causes
the PLL to become stuck at that frequency. To prevent this, the GUI software prevents repeated writes
of the same frequency to the PLL. However, the PLL has a limited frequency resolution and repeated
writes to different frequencies can cause the PLL to become stuck if the entered frequencies are
coerced to the same frequency. If this occurs, then disconnect and reconnect the GUI to reset the
PLL.
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2.8 Power Supplies
The ADS1278 EVM requires a 6V input through the J10 terminal block and typically draws under 500mA of
current. Three low-noise TPS7A4700 low dropout (LDO) voltage regulators (U9-U11) provide the three voltage
rails used by the ADS1278 and the external circuitry. By default, AVDD is configured for 5V, IOVDD is configured
for 3.3V, and DVDD is configured for 1.8V. DVDD can be configured to 2.1V for up to 37MHz operation in
high-speed mode by installing zero-ohm resistors at locations R69 and R70.
Each voltage rail also features an indicator LED and a test point for convenient verification of power supply
functionality.
AVDD
GND
GND
OUT 1
NC 2
SENSE 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4700RGWR
U9
1uF
C32
0
R56
0
R53
AVDD
GND
100k
R49
GND
+6V
10V
10µF
C27
22uF
C26
0
R54
0
R55
0
R57
0
R58
GND
AVDD 5V, Max 145mA
16V
22uF
C25
EXT_PWR
EXT_PWR
12
Green
D1
6.65k
R45
12
Green
D2
6.65k
R46
AVDD
DVDD
12
Green
D3
6.65k
R47
GND
IOVDD
IOVDD
GND
GND
OUT 1
NC 2
SENSE 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4700RGWR
U10
0
R62
0
R59
IOVDD
GND
100k
R50
GND
10V
10µF
C29
22uF
C28
0
R60
0
R61
0
R63
0
R64
GND
IOVDD 3.3V, Max 1mA
DVDD
GND
GND
OUT 1
NC 2
SENSE 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4700RGWR
U11
1uF
C34
0
R68
0
R65
DVDD
GND
100k
R51
GND
10V
10µF
C31
22uF
C30
0
R66
0
R67
0
R69
0
R70
GND
DVDD 1.8V, Max 30mA, 0.111W heat at LDO
GND
5.6V
D6
MMSZ4690T1G
AVDD_ADC
GND
3.6V
D5
MMSZ5227B-7-F
GND
IOVDD_ADC
3.6V
D4
GND
DVDD_ADC
1
2 3
Q2
BSS138W
1
2 3
Q3
BSS138W
DVDD
GND
EXT_PWR
1
2 3
Q1
BSS138W
GND
AVDD
EXT_PWREXT_PWR
IOVDD
100k
R52
J9
D3082-05
GNDGND
J8
D3082-05
GNDGND
35V
2.2uF
C33
IOVDD
EXT_PWR EXT_PWR
1 2
J10
ED555/2DS
GNDGND +6V
External +6V Power
Figure 2-9. Power Supply Circuitry
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3 Software
3.1 ADS1278EVM Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS1278 EVM
and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the antivirus settings, an error message can appear
or the installer.exe file can be deleted.
As shown in Figure 3-1, accept the license agreements and follow the on-screen instructions to complete the
installation.
Figure 3-1. GUI Installation Prompts
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As a part of the ADS1278 EVM GUI installation, install the Device Driver as shown in Figure 3-2. Click Next to
proceed.
Figure 3-2. Device Driver Installation Prompts
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The ADS1278 EVM requires the LabVIEW™ run-time engine and can prompt for the installation of this software
if the LabVIEW run-time engine is not already installed, as shown in Figure 3-3.
Figure 3-3. LabVIEW Runtime Installation Prompts
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3.2 Hardware Connection
Connect the EVM as shown in Figure 3-4 after installing the software:
1. Physically connect P2 of the PHI to J5 of the ADS1278 EVM.
2. Install the screws to provide a robust connection. Connect the USB on the PHI to the computer.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with
the PC.
3. Power the ADS1278 EVM through the J10 terminal with 6V.
4. Start the software GUI. Notice that the LEDs on the PHI blink slowly when the FPGA firmware is loaded on
the PHI. Loading takes a few seconds.
5. Connect the signal generator. The input range is 0 V to 5 V. A common input is a 4.9VPP signal with a 2.5V
offset. This signal is adjusted just below the full-scale range to avoid clipping.
Op onal signals
5. Connect Input
Signals
1. Connect PHI to
ADS1278 EVM
2. Install screws and
connect USB.
3. Connect
Power to the
ADS1278 EVM
3. PHI Indicator LEDs
Figure 3-4. Hardware Connections
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3.3 Optional EVM Configuration
Figure 3-5 shows optional connections to the configuration pins, clock, voltage reference and VCM. These
connections are not required for initial setup of the EVM but can be helpful to configure the EVM more closely to
the user's end application configuration. Review Section 2 and Section 4.1 to understand how these connections
are used.
Vcm out
Vref IN
Channel
Shutdown Pins
Mode and Format
Pins
Digital
Communica on
pins
External Clock
Figure 3-5. Optional EVM Connections
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3.4 GUI Settings for ADC Control
Figure 3-6 shows that the EVM global controls are located on the left-hand side of the GUI. These controls
include the number of samples, clock frequencies, sampling rate, and other important parameters. In the upper
left-hand side of the GUI is the Pages tree, which allows access to the other key pages in the GUI.
ADC mode and
communica

on format se

ngs
Vref se

ng
Number of samples to capture
Clock Se

ngs
Figure 3-6. EVM Settings
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3.5 Time Domain Display
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is useful
for both studying the behavior and debugging any gross problems with the ADC or drive circuits. The user can
capture the selected number of samples from the ADS1278 EVM by using the Capture button. The sample
indices are on the x-axis and two y-axes show the corresponding output codes and the equivalent analog
voltages based on the specified reference voltage. Switching pages to any of the analysis tools described in the
subsequent sections causes calculations to be performed on the same set of data.
Figure 3-7. Time Domain Display
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3.6 Frequency Domain Display
The spectral analysis tool shown in Figure 3-8 is intended to evaluate the dynamic performance (SNR, THD,
SFDR, SINAD, and ENOB) of the ADS1278 ADC through single-tone sinusoidal signal FFT analysis using
the 7-term Blackman-Harris window setting. The FFT tool includes windowing options that are required to
mitigate the effects of non-coherent sampling (this discussion is beyond the scope of this document). The
7-Term Blackman-Harris window is the default option and has sufficient dynamic range to resolve the frequency
components of up to a 24-bit ADC. The None option corresponds to not using a window (or a rectangular
window) and is not recommended.
Figure 3-8. Frequency Domain Display
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3.7 Histogram Display
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the various
sources connected to the ADC when measuring a dc signal. The cumulative effect of noise coupling to the
ADC output from sources (such as the input drive circuits, reference drive circuit, ADC power supply, and the
ADC) is reflected in the standard deviation of the ADC output code histogram. The histogram is obtained by
performing multiple conversions of a dc input applied to a given channel. As shown in Figure 3-9, the histogram
corresponding to a dc input is displayed on clicking the Capture button.
Figure 3-9. Histogram Display
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4 Hardware Design Files
This section contains the ADS1278 EVM schematics, and PCB layout, and bill of materials (BOM)
4.1 Schematics
This section shows the schematics for the ADS1278 EVM.
25V
0.1µF
C2
25V
0.1µF
C3
25V
0.1µF
C4
25V
0.1µF
C5
GND
AVDD
DVDD
GND
49.9R7
IOVDD
GND
VCOM_ADC
VREFP
CHAN_P1
CHAN_N1
CHAN_P2
CHAN_N2
CHAN_P3
CHAN_N3
CHAN_P4
CHAN_N4
CHAN_P5
CHAN_N5
CHAN_P6
CHAN_N6
CHAN_P7
CHAN_N7
CHAN_P8
CHAN_N8
49.9R8
49.9R9
49.9R10
49.9R11
49.9R12
49.9R13
49.9R14
/PWDN1
/PWDN2
/PWDN3
/PWDN4
/PWDN5
/PWDN6
/PWDN7
/PWDN8
GND
1
2
J2
VREFP
AVDD
25V
0.1µF
C9
GND
25V
0.1µF
C8
100kR25
100kR26
100kR28
100kR30
100kR32
100kR34
100kR36
100kR38
GND
CONTROL.MODE0
CONTROL.MODE1
CONTROL.FORMAT0
CONTROL.FORMAT1
CONTROL.FORMAT2
GND
/PWDN1
/PWDN2
/PWDN3
/PWDN4
/PWDN5
/PWDN6
/PWDN7
/PWDN8
CONTROL.CLKDIV
GND
100kR27
100kR29
100kR31
100kR33
100kR35
100kR37
CONTROL.MODE0
CONTROL.MODE1
CONTROL.FORMAT0
CONTROL.FORMAT1
CONTROL.FORMAT2
CONTROL.CLKDIV
IOVDD_ADC
IOVDD_ADC
1 2
3 4
5 6
7 8
9 10
11 12
J4
TSW-106-07-G-D
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
16
18
J3
TSW-109-07-G-D
VIN
2
TEMP
3GND 4
TRIM/NR 5
VOUT 6
REF5025AIDGKT
U3A
1uF
C12
1uF
C15
10V
10µF
C13
100 µF
C16
AVDD
150nFC11
1.00kR23
2.00kR17
47.0R21
25V
0.1µF
C14
GND
DNC 1
NC 7
DNC 8
REF5025AIDGKT
U3B
49.9R4
49.9R6
49.9R16
CLK
1.00k
R19
49.9
R15
GND
GND
1
2
J1
100kR24
DVDD_ADC
AVDD_ADC
IOVDD_ADC
/THSPD
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT1
DATA
DATA
VCOM
CONTROL
CLKDIV
MODE0
FORMAT0
MODE1
FORMAT1
FORMAT2
CONTROL
2
3
1
A
OPA2320AQDGKRQ1
U2A
5
6
7
B
OPA2320AQDGKRQ1
U2B
VREFP
GND
CONTROL.CLKDIV
AVDD
5
AVDD
44
AVDD
53
AVDD
60
DVDD
26
IOVDD
22
IOVDD
23
AINP1
3
AINP2
1
AINP3
63
AINP4
61
AINP5
51
AINP6
49
AINP7
47
AINP8
45
AINN1
4
AINN2
2
AINN3
64
AINN4
62
AINN5
52
AINN6
50
AINN7
48
AINN8
46 TEST0 8
TEST1 9
DOUT1 20
DOUT2 19
DOUT3 18
DOUT4 17
DOUT5 16
DOUT6 15
DOUT7 14
DOUT8 13
DRDY/FSYNC 29
PWDN1 42
PWDN2 41
PWDN3 40
PWDN4 39
PWDN5 38
PWDN6 37
PWDN7 36
PWDN8 35
SYNC 11
CLK 27
CLKDIV 10
DIN 12
SCLK 28
VCOM
55
VREFN
57 VREFP
56 FORMAT0 32
FORMAT1 31
FORMAT2 30
MODE0 34
MODE1 33
AGND 6
AGND 43
AGND 54
AGND 58
AGND 59
DGND 7
DGND 21
DGND 24
DGND 25
PowerPAD 65
ADS1278IPAPR
U1
0
R18
0
R20 VREFN
VREFN
10V
10µF
C10
V+
8V- 4
OPA2320AQDGKRQ1
U2C
/DRDY_FSYNC
SCLK
DIN
/SYNC
IO
IO
AVDD
49.9R5
GND
VCOM
0
R22
GND
VREFext
0
R1
0
R3
0
R2
10V
10µF
C7
10V
10µF
C6
10V
10µF
C1
VCOM_ADC
VREFN
Figure 4-1. ADS1278 Connections Schematic
Hardware Design Files www.ti.com
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