Texas Instruments ADS9817 User manual

User's Guide
ADS9817 Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS9817EVM evaluation module
(EVM). This kit is an evaluation platform for the ADS9817, which is an 8-channel, 18-bit, 2-MSPS per channel,
successive approximation register (SAR) analog-to-digital converter (ADC). The EVM eases the evaluation of
the ADS9817 device with hardware, software, and computer connectivity through the universal serial bus (USB)
interface. This user's guide includes complete circuit descriptions, schematic diagrams, and a bill of materials
(BOM). Throughout this document, the terms demonstration kit, evaluation board, evaluation module, and EVM
are synonymous with the ADS9817EVM.
ADS9817EVM Evaluation Module
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Table of Contents
1 Overview..................................................................................................................................................................................3
1.1 ADS9817EVM Features.....................................................................................................................................................3
2 ADS9817EVM Quick Start Guide........................................................................................................................................... 5
3 Analog Interface......................................................................................................................................................................7
3.1 ADC Input SMA Connections.............................................................................................................................................7
3.2 Voltage Reference..............................................................................................................................................................7
4 Digital Interface and Clock Inputs.........................................................................................................................................8
4.1 Digital Interface Connections............................................................................................................................................. 8
4.2 Clock Select..................................................................................................................................................................... 10
5 Power Supplies..................................................................................................................................................................... 11
5.1 USB Power and When to Power the Board Externally.....................................................................................................11
6 ADS9817EVM Software Reference......................................................................................................................................12
6.1 ADS9817EVM Software Installation.................................................................................................................................12
6.2 USB Driver Installation..................................................................................................................................................... 14
6.3 Using the CONFIG Tab.................................................................................................................................................... 15
6.4 Using the Capture Tab..................................................................................................................................................... 16
6.5 Using the INL/DNL Tool....................................................................................................................................................17
6.6 Using the Histogram Tab..................................................................................................................................................18
7 Schematics, Layouts, and Bill of Materials........................................................................................................................ 19
7.1 Schematics.......................................................................................................................................................................19
7.2 Layout.............................................................................................................................................................................. 22
7.3 Bill of Materials (BOM)..................................................................................................................................................... 24
8 Revision History................................................................................................................................................................... 27
List of Figures
Figure 1-1. System Using FMC to FPGA Kit................................................................................................................................3
Figure 1-2. System Using GUI and TSWDC155EVM..................................................................................................................4
Figure 1-3. ADS9817EVM Block Diagram...................................................................................................................................4
Figure 2-1. Connecting the Hardware..........................................................................................................................................5
Figure 2-2. Initial Required Setup on the Config Tab...................................................................................................................6
Figure 3-1. Input SMA Connections Digital Interface...................................................................................................................7
Figure 3-2. REF7040................................................................................................................................................................... 7
Figure 4-1. Digital I/O...................................................................................................................................................................8
Figure 4-2. Connections to ADS9817.......................................................................................................................................... 9
Figure 4-3. Sample Clock Selection.......................................................................................................................................... 10
Figure 5-1. Power Entry and Regulators....................................................................................................................................11
Figure 6-1. Initial Software Installation.......................................................................................................................................12
Figure 6-2. Installation Process................................................................................................................................................. 13
Figure 6-3. Open Device Manager............................................................................................................................................ 14
Figure 6-4. Update Driver With Device Manager.......................................................................................................................14
Figure 6-5. Initial Required Setup on the Config Tab.................................................................................................................15
Figure 6-6. Initial Required Setup on the Capture Tab.............................................................................................................. 16
Figure 6-7. Using the INL/DNL Tool...........................................................................................................................................17
Figure 6-8. Using the Histogram Tab......................................................................................................................................... 18
Figure 7-1. ADS9817 Device Connections Schematic.............................................................................................................. 19
Figure 7-2. Power Connections and Regulators Schematic...................................................................................................... 20
Figure 7-3. Digital Connector Schematic................................................................................................................................... 21
Figure 7-4. ADS9817 PCB Layout (Top Layer)..........................................................................................................................22
Figure 7-5. ADS9817 PCB GND1 Layer (Signal Layer 1)......................................................................................................... 22
Figure 7-6. ADS9817 PCB GND2 Layer (Signal Layer 2)......................................................................................................... 23
Figure 7-7. ADS9817 PCB Layout (Bottom Layer).................................................................................................................... 23
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 3
Table 7-1. Bill of Materials..........................................................................................................................................................24
Trademarks
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
All trademarks are the property of their respective owners.
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1 Overview
The ADS9817EVM is a platform for evaluating the performance of the ADS9817 SAR ADC, which includes a
PGA front-end to support input voltages of ±12-V, ±10-V, ±7-V, ±5-V, ±3.5-V, and ±2.5-V, both in single-ended
and differential configurations. The ADC core supports 18-bit resolution at 2-MSPS/channel. The evaluation
board includes the ADS9817EVM PCB with standard FMC connecter which mates with many FPGA kits,
including the TSWDC155EVM (sold separately). The TSWDC155EVM is a digital controller board that is
necessary for the EVM software GUI to communicate with the device, graph measured results, and compute
common figures of merit (for example, SNR and THD).
The following related documents are available for download through the Texas Instruments web site at
www.ti.com.
Table 1-1. Related Documentation
Device Literature Number
TSWDC155EVM SLAU870
TPS61070 SLVS510
TPS7A20 SBVS338
LM66100 SLVSEZ8
REF7040 SNAS781
1.1 ADS9817EVM Features
The ADS9817EVM includes the following features:
• Hardware required for diagnostic testing and accurate performance evaluation of the ADS9817 ADC.
• The TSWDC155EVM controller (sold separately) provides all necessary digital I/O signals and power rails
required for operating the ADS9817EVM.
• Easy-to-use evaluation GUI for Microsoft® Windows® 10, 64-bit operating systems requires the
TSWDC155EVM (sold separately) for operation.
• The included software suite features graphical tools for data capture, histogram analysis, spectral analysis,
and linearity measurements.
•Figure 1-3 depicts the connections and basic subsystems of the EVM.
Included in kit
ADS9817EVM
Not provided by Texas
Instruments
FPGA Kit
Option for external
5.2 V to 5.5 V DC
power
Signal Source
Signal Source
Custom
Software
Figure 1-1. System Using FMC to FPGA Kit
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Included in kit
ADS9817EVM
TSWDC155EVM
Signal
Source
Sold Separately from
Texas Instruments
Power supplied by
TSWDC155EVM
over USB
Signal
Source
ADS9817
GUI
Figure 1-2. System Using GUI and TSWDC155EVM
Power
FMC
connector
Power
SMA
SMA
SMA
SMA
SMA
SMA
AIN1M
AIN1P
AIN8M
AIN8P
AIN7M
AIN7P
SMASMA
AIN7M AIN7P
SMASMA
AIN7M AIN7P
SMASMA
AIN7M AIN7P
SMASMA
AIN7M AIN7P
SMA
SMA
AIN2M
AIN2P
Reference
REF7040
Clock
Select
External Clock
ADS9817
SMA
Figure 1-3. ADS9817EVM Block Diagram
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2 ADS9817EVM Quick Start Guide
The following instructions are a step-by-step guide to connecting the ADS9817EVM to the computer and
evaluating the performance of the ADS9817:
1. Review the default jumper settings in Figure 2-2 below as well as the power guidelines in Section 5.1.
2. Physically connect J1 of the TSWDC155EVM to J27 of the ADS9817EVM. This component is the digital
communications and power signal connection in default configuration.
3. Set jumper J18 to the FMC_PWR position so the TSWDC155EVM provides power. Otherwise, set J18 to
EXT_PWR and connect an external 5.2-V to 5.5-V supply on screw terminal connection J17.
4. Bypass any external USB hub and connect the USB on the TSWDC155EVM directly to the computer.
TSWDC155
(DC155C)
(Default) J2 set to
USB_PWR position
(5V EXT position
optional)
(Default) J8: USB-C to
USB-A cable. 5V
(Optional)
J10: 5V, 3A benchtop PSU
(or wall power adapter J13)
(Optional)
J17: 5.2V -
5.5V, 1A, bench
supply
(Default) J18 set to
FMC_PWR position
(EXT_PWR position
optional)
ADS9817EVM
(DC233)
Jumpers shorting
negative input to
GND as needed:
J19 … J26
(Default) J29 in
FPGA_CLK
position
(Default) J5
set to V_ADJ
= 2.5V
(Default) J4
covered to
lock JTAG
Figure 2-1. Connecting the Hardware
1. Start the software GUI as described in Section 6.1.
2. Press the Initialize USB, Power Up, Program FPGA, and Initialize ADS98xx buttons, in order from top to
bottom, on the Config tab to power up and configure the EVM, as shown in Figure 2-2, (see Section 6.3 for
details).
3. Connect a +/-5-V, single-ended sine wave signal from a function generator to any AINxP SMA input
connector.
4. Press the EN SYNC button on the Capture tab.
5. Select the number of samples to be at least 32k points, and choose the Hanning window type for best
frequency domain results.
6. Press the Start Capture button to collect and analyze the data displayed on the appropriate CHx tab; see
Figure 6-6.
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Figure 2-2. Initial Required Setup on the Config Tab
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3 Analog Interface
This section details the analog input connections to the ADS9817EVM.
3.1 ADC Input SMA Connections
Each ADC channel is connected to two SMA input connectors. 0402 footprints are provided to add a first-order,
low-pass filter network on all ADC channels. By default, the filter capacitors are uninstalled and the filter
resistors are populated with 0 ohms. Use NP0/C0G type capacitors and low-tolerance resistors to maintain AC
performance when choosing to populate these footprints with a low-pass filter circuit.
Additionally, the ADC negative input connectors (for example, AIN1M) have the option to be shorted to GND with
a jumper to allow for single-ended input signals. Figure 3-1 shows the input connections for a digital interface.
GND
AIN1P
AIN1M
0
R4
50V
10pF
C9
0
R8
GND
10k
R6
1
2
J19
1
2 3 4
5
J1
GND
1
2 3 4
5
J2
Figure 3-1. Input SMA Connections Digital Interface
3.2 Voltage Reference
The ADS9817 uses an internal 4.096-V reference voltage, which can be measured on the REFIO pin when
configured as an output (default). For applications which require improved drift performance, configure the
REFIO pin as an input and apply an external reference voltage to the pin.
The ADS9817EVM includes a provision for evaluating the REF7040 reference IC. The REF70xx family of high
precision series voltage references offers the industry’s lowest noise (0.23 ppmp-p), very low temperature drift
coefficient (2 ppm/°C), and high accuracy (±0.025%). In addition, these precision reference devices feature high
PSRR, low drop-out voltage and excellent load and line regulation to help meet strict transient requirements. The
REF7040 on the EVM is the 4.096-V output voltage option. To connect the REF7040 to the ADS9817, configure
the REFIO pin as an input via the GUI and then install a shunt on jumper J30.
VIN
2
EN
1
OUTF 7
OUTS 6
GND 3
GND 4
GND 5
GND 8
REF7040QFKHT
U7
10V
C22
0.1µF
GND
5V
GND
10V
10uF
C29
GND
2 1
J30
REFIO
Figure 3-2. REF7040
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4 Digital Interface and Clock Inputs
This section details the digital interface connections and clocking options for the ADS9817EVM.
4.1 Digital Interface Connections
The ADS9817 uses an SPI to configure the internal device registers (SCLK, SDI, SDO, CSn, and SPI_EN). A
separate CMOS interface is used for capturing conversion data for each ADC channel using up to four output
data lanes (D0, D1, D2, and D3). The SPI and CMOS interface signals connect to the FMC connector. Figure
4-1 provides the FMC connector signal definition. These signals are also available via test points for scope
measurements as indicated in PCB silkscreen.
A1
A2
A3
A1
A2
A3
A4
A5 A4
A5
A6
A7 A6
A7
A8
A9 A8
A9
A10
A11 A1
A10
1
A12
A13 A12
A13
A14
A15 A14
A15
A16
A17 A16
A17
A18
A19 A18
A19
A20
A21 A20
A21
A22
A23 A22
A23
A24
J27A
ASP-134488-01
B1
A25
A35
A26
A27
A28
A29
A30
A32
A33
A34
A36
A37
A38
A39
A40
A31
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B13
B14 B13
B14
B15
B16 B15
B16
B1
B10
B12
B2
B3
B4
B5
B6
B7
B8
B9
1B1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B12
1
B17
B18 B17
B18
B19
B20 B19
B20
B21
B22 B21
B22
B23
B24 B23
B24
B25
B26 B25
B26
B27
B28 B27
B28
B29
B30 B29
B30
B31
B32 B31
B32
B33
J27B
ASP-134488-01
C1
B35
B34
B36
B37
B38
B39
B40
B33
B34
B35
B36
B37
B38
B39
B40
C2
C3
C1
C2
C3
C4
C5 C4
C5
C6
C7 C6
C7
C8
C9 C8
C9
C10
C11 C1
C10
1
C12
C13 C12
C13
C14
C15 C14
C15
C16
C17 C16
C17
C18
C19 C18
C19
C20
C21 C20
C21
C22
C23 C22
C23
C24
J27C
ASP-134488-01
D1
C25
C35
C26
C27
C28
C29
C30
C32
C33
C34
C36
C37
C38
C39
C40
C31
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D13
D14 D13
D14
D15
D16 D15
D16
D1
D10
D12
D2
D3
D4
D5
D6
D7
D8
D9
1D1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D12
1
D17
D18 D17
D18
D19
D20 D19
D20
D21
D22 D21
D22
D23
D24 D23
D24
D25
D26 D25
D26
D27
D28 D27
D28
D29
D30 D29
D30
D31
D32 D31
D32
D33
J27D
ASP-134488-01
E1
D35
D34
D36
D37
D38
D39
D40
D33
D34
D35
D36
D37
D38
D39
D40
E3
E2 E1
E2
E3
E4
E5 E4
E5
E6
E7 E6
E7
E8
E9 E8
E9
E10
E11 E1
E10
1
E12
E13 E12
E13
E14
E15 E14
E15
E16
E17 E16
E17
E18
E19 E18
E19
E20
E21 E20
E21
E22
E23 E22
E23
E24
J27E
ASP-134488-01
F1
E25
E26
E27
E28
E29
E30
E32
E33
E34
E35
E36
E37
E38
E39
E40
E31
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
F13
F14 F13
F14
F15
F16 F15
F16
F1
F10
F12
F2
F3
F4
F5
F6
F7
F8
F9
1F1
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F12
1
F17
F18 F17
F18
F19
F20 F19
F20
F21
F22 F21
F22
F23
F24 F23
F24
F25
F26 F25
F26
F27
F28 F27
F28
F29
F30 F29
F30
F31
F32 F31
F32
F33
J27F
ASP-134488-01
H1
F35
F34
F36
F37
F38
F39
F40
F33
F34
F35
F36
F37
F38
F39
F40
H13
H14 H13
H14
H15
H16 H15
H16
H1
H10
H12
H3
H4
H5
H6
H7
H8
H9
H2
1H1
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H12
1
H17
H18 H17
H18
H19
H20 H19
H20
H21
H22 H21
H22
H23
H24 H23
H24
H25
H26 H25
H26
H27
H28 H27
H28
H29
H29
H30
H30
H31
H31
H32
H32
H33
H33
H34
H35
H36
H34
H35
H36
J27H
ASP-134488-01
H37
H38
H39
H40
H37
H38
H39
H40
G1
G2
G3
G1
G2
G3
G4
G5 G4
G5
G6
G7 G6
G7
G8
G9 G8
G9
G10
G11 G1
G10
1
G12
G13 G12
G13
G14
G15 G14
G15
G16
G17 G16
G17
G18
G19 G18
G19
G20
G21 G20
G21
G22
G23 G22
G23
G24
J27G
ASP-134488-01
J1
J
J
3
2J
J
J
1
2
3
J4
G25
G27
G28
G29
G33
G35
G37
G38
G39
G26
G30
G32
G34
G36
G40
G31
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
J5 J
J
4
5
J6
J7 J
J
6
7
J8
J9 J
J
8
9
J10
J11 J
J
1
10
1
J12
J13 J
J
12
13
J14
J15 J
J
14
15
J16
J17 J
J
16
17
J18
J19 J
J
18
19
J20
J21 J
J
20
21
J22
J23 J
J
22
23
J24
J24
J25
J26
J27
J
J
J
25
26
27
J
J
J
28
29
30
J
J
J
28
29
30
J
J
32
31 J
J
31
32
J33 J33
J27I
ASP-134488-01
K1
J
J
J
J
J
J
J
34
35
36
37
38
39
40
J
J
J
J
J
J
J
34
35
36
37
38
39
40
K6
K8
K9 K8
K9
K5
K2
K3
K4
K6
K7
K1
K2
K3
K4
K5
K7
K10 K1
K1
K12
1K1
K12
1
0
K13
K14 K13
K14
K15
K16 K15
K16
K17
K18 K17
K18
K19
K20 K19
K20
K21
K22 K21
K22
K23
K24 K23
K24
K25
K26 K25
K26
K27
K28 K27
K28
K29
K29
K30
K30
K31
K31
K32
K32
K33
K33
K34
K35
K36
K34
K35
K36
J27J
ASP-134488-01
SDI
SDO
SMPL_SYNC
SPI_EN
K37
K38
K39
K40
K37
K38
K39
K40
DCLKOUT
SMPL_CLKP
SMPL_CLKM
GND GND GND GND GND
GND GND GND GNDGND
3P3V
3P3VAUX
3P3V
3P3V VADJ VADJ
VADJ
12P0V
VADJ
12P0V
3P3V
SCL
SDA
FCLKOUT
D0
D2
D3
D1
PWDNz
SCLK
RESETz
CSz
H2 tie to GND for
PRSNT_M2C_L
Figure 4-1. Digital I/O
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The digital communications lines for the ADC (shown in Figure 4-2) are CMOS interface and are connected with
optional termination resistors. A digital serial peripheral interface (SPI) port is used to configure registers in the
device. The SDO output line includes a termination. Figure 4-2 also shows the analog inputs and the decoupling
and filter capacitors.
AIN1M
55 AIN1P
54
AIN2M
2AIN2P
1
AIN3M
4AIN3P
3
AIN4M
6AIN4P
5
AIN5M
10 AIN5P
9
AIN6M
12 AIN6P
11
AIN7M
14 AIN7P
13
AIN8M
17 AIN8P
16
SMPL_CLKP 44
45
SMPL_SYNC
25
CS
32
PWDN
RESET 31
D0 34
D1 35
D2 36
D3 37
43
SMPL_CLKM
33
DCLKOUT
40
FCLKOUT
SCLK 26
SDI/EXTREF 27
SDO 28
SPI_EN 24
VBIAS
20
NC
38
NC
39
NC
50
NC
51
ADS9817IRSHT
U1A
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
AIN7P
AIN7M
AIN8P
AIN8M
RESETz
SMPL_CLKP
SMPL_SYNC
DCLKOUT
FCLKOUT
D0
D1
D2
D3
SPI_EN
CSz
SCLK
SDI
SDO
PWDNz
DCLKOUT
FCLKOUT
D0DATA_
D1DATA_
D2DATA_
D3DATA_
SPI_EN
SCLK
CSz
SDI
SDO
PWDNz
RESETz
SMPL_CLKP
SMPL_SYNC
33
R10
33
R11
33
R12
33
R13
33
R14
33
R15
SMPL_CLKM SMPL_CLKM
TP_NC_20
21 AVDD_1V8
49 AVDD_1V8
15 AVDD_5V
56 AVDD_5V
DVDD_1V8
22
DVDD_1V8
47
DVDD_1V8
48
IOVDD
30
IOVDD
41
GND 7
GND 23
GND 46
IOGND 29
IOGND 42
57
Thermal_Pad
REFM 8
REFM 18
19
REFOUT_2V5
REFIO 52
REFM 53
ADS9817IRSHT
U1B
10V
C19
1µF
10V
C20
0.1µF
10V
C21
0.1µF
GND GND GND
5V
10V
C15
1µF
10V
C16
0.1µF
GND GND
10V
C23
0.1µF
GND
1V8_VDD
1V8_VDD
10V
C24
0.1µF
10V
C25
0.1µF
GND GND
1V8_IOVDD
GND GND
REFOUT_2V5
REFIO
REFOUT_2V5
10V
C27
10µF
10V
C26
10µF
GND
GND
REFIO
Figure 4-2. Connections to ADS9817
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4.2 Clock Select
The ADS9817EVM uses a single-ended sampling clock for ADC conversions. The positive sampling clock input
(SMPL_CLKP) is selected using jumper J29. Install a shunt in the [2-3] position (default) to source the clock
signal from the TSWDC155EVM through the FMC connector. This allows the user to select the clock frequency
from the options listed in the EVM GUI.
An external clock source can also be used to control ADC conversions. Connect a low-jitter clock source to SMA
connector J28 and install a shunt in the [1-2] position on J29.
The negative source of the sample clock (SMPL_CLKM) can be sourced from either the FMC connector
(FMC_SMPL_CLKM) or GND through R22 or R35, respectively. By default, R35 is populated and R22 is
uninstalled.
1
2
3
J29
1
MNT_1
MNT_2
MNT_3
MNT_4
J28
60312002114503
GND
EXT_SMPL_CLKP
EXT_SMPL_CLKP
SMPL_CLKP
FMC_SMPL_CLKP
0
R22
0
R35
GND
FMC_SMPL_CLKM
SMPL_CLKM
Figure 4-3. Sample Clock Selection
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5 Power Supplies
By default, the TSWDC155EVM provides the ADS9817EVM with a 3.3-V supply. The ADS9817EVM has
a TPS61070 boost converter that boosts the 3.3-V supply to 5.4 V. This voltage is applied to low-dropout
regulators (LDOs) to derive the AVDD, DVDD, and IOVDD supplies. U3 (TPS7A2050) provides the 5-V AVDD
supply and U4 and U6 (TPS7A2018) provide the 1.8-V DVDD and IOVDD supplies, respectively. The LDO
input voltage (LDO_IN) can be changed to an external source (5.2 V to 5.5V) applied to terminal block J17 by
placing a shunt on J18 in the [2-3] position. In this case U2 (LM66100), provides reverse polarity protection if the
connection is wired incorrectly. Figure 5-1 shows the power tree schematic for the ADS9817EVM.
2
1
J17
GND
OUT 5
GND 2
IN
1
EN
3
NC
4
TPS7A2050PDBVR
U3
5V
GND
16V
1µF
C1
16V
1µF
C2
GND GND
IN
1
GND
2
CE
3N/C 4
ST 5
OUT 6
LM66100DCKR
U2
GND
1V8_VDD
GND
16V
C3
1µF
16V
1µF
C4
GND GND
1V8_IOVDD
GND
16V
1µF
C7
16V
1µF
C8
GND GND
2.2k
R1
Green
12
D2
APT2012LZGCK
GND
AVDD
VDD
IOVDD
EN
3
IN
1
NC
4
OUT 5
GND 2
TPS7A2018PDBVR
U4
EN
3
IN
1
NC
4
OUT 5
GND 2
TPS7A2018PDBVR
U6
SW 1
GND
2
EN
3
FB 4
VOUT 5
6VBAT
TPS61070DDCR
U5
10uH
L1
GND
16V
10uF
C5
GND
1.96M
R2
200k
R3
GND
25V
C6
22µF
GND
LDO_IN
6V
D1
GND 3
2
1
J18
16V
C28
1µF
GND
3P3V
Figure 5-1. Power Entry and Regulators
5.1 USB Power and When to Power the Board Externally
As discussed in Section 2, the USB-C connector is able to provide power to the TSWDC155EVM and
ADS9817EVM using the default configuration. The combined peak current consumption reaches 600mA (typical)
during the ADC conversion process and 520mA RMS (typical) after the ADS9817EVM is initialized in the GUI, as
described in Section 6.3.
The TWDC155EVM is a high-power SuperSpeed (USB 3.0) device. This means a PC supplies up to 900 mA
from a compliant USB 3.0 port. However, many PC USB port configurations allow much less than this limit
depending on the unit load handshake process, usually resulting from other devices on the bus. Tripping the
current limit on a USB can result in cutting power to the USB port, excessive power dissipation or heating,
depending on the PC port configuration. As a result, TI highly recommends to consider switching to an externally
powered ADS9817EVM and/or TSWDC155EVM if:
• Only USB 1.0 or USB 2.0 ports are available.
• There are multiple devices connected to the PC by USB at the same time.
• The USB 3.0 port configuration for the PC is unknown.
To switch to the external power configuration on the ADS9817EVM, move the jumper on J18 to the EXT_PWR
position and use the J17 terminal block to provide the required 5.2-V to 5.5-V supply. To switch to the external
power configuration on TSWDC155EVM, move the jumper on J2 to the 5 V (external) position and use the J10
terminal block or barrel jack connector to provide the required 5-V supply.
USB hubs can cause possible device enumeration issues and are not recommended when communicating
through the TSWDC155EVM.
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6 ADS9817EVM Software Reference
6.1 ADS9817EVM Software Installation
This section details the installation and operation of the ADS9817EVM software graphical user interface (GUI).
This software requires the TSWDC155EVM (sold separately) controller to operate. The first steps to installing
the software (as shown in Figure 6-1) is to download the latest version of the EVM GUI installer from the Tools
and Software folder of the ADS9817EVM, and run the GUI installer to install the EVM GUI software on the
computer. Accept all the license agreements and choose the destination location, project directory, and start
menu. Typically, the default values work, but these values can be customized as needed based on the user's
requirements.
Figure 6-1. Initial Software Installation
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Next, the installer prompts the user to create a desktop icon and summarize the installation plan. Clicking Install
begins copying software onto the computer. This process takes a few minutes. At completion, the user can
launch a readme text file and the application. Figure 6-2 shows these steps.
Figure 6-2. Installation Process
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6.2 USB Driver Installation
This section describes the steps for installing the USB driver.
1. a. For the TSWDC155, connect J8 to the workstation using a USB-C to USB-A cable.
b. Bypass any USB hub and connect directly to the computer.
2. Open the Windows® Device Manager, as shown in Figure 6-3, and right-click on the WestBridge folder in the
Device Manager window and select the Update Driver button (see Figure 6-4).
3. In the next window that appears, select Browse my computer for driver software.
4. Then select Let me pick from a list of available drivers on my computer in the next pop-up window.
5. Click on Have Disk in the pop-up window and navigate to C:\Program Files\Texas
Instruments\ADS98xx\bin\proj_lib\Sparrow\Bootloader.
Figure 6-3. Open Device Manager
Figure 6-4. Update Driver With Device Manager
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6.3 Using the CONFIG Tab
After the EVM GUI is started, press the Initialize USB, Power Up, Program FPGA, and Initialize ADS98xx
buttons to setup the initial configurations. As shown in Figure 6-5, press these buttons in order from top to
bottom. Wait after each button press for the status to indicate that the step is complete. For the Power Up and
Program FPGA buttons, some status LEDs on the hardware illuminate. The power-up step takes the longest
time (approximately 30 seconds). After all four buttons are pressed, the power on the ADS9817EVM is on and
the ADS9817 device registers are configured.
Figure 6-5. Initial Required Setup on the Config Tab
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6.4 Using the Capture Tab
In Figure 6-6, the device and EVM are powered up and configured. In this step, the necessary updates to the
Capture settings are made to capture the time domain data and to get a good frequency domain result. First, the
EN SYNC button is pressed to synchronize the communication channel. Next, update the number of samples to
at least 32k to get good frequency domain results (for example, accurate FFT display, SNR data, and THD data).
Finally, select the Hanning type window to eliminate spectral leakage in the FFT result.
When these changes are made, press the Start Capture button to collect time domain and frequency domain
data. Select the appropriate tab to view data for channel 1 or channel 2.
Figure 6-6. Initial Required Setup on the Capture Tab
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6.5 Using the INL/DNL Tool
The INL/DNL tool measures the linearity of the of the ADS9817EVM by applying a full-scale, low-distortion
sinusoidal input signal. The accuracy improves if the number of hits per code is increased at the cost of extra
test time. Select the channel to measure and the hits per code, then press the GET INL/DNL button (as shown in
Figure 6-7) to run this tool.
Figure 6-7. Using the INL/DNL Tool
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6.6 Using the Histogram Tab
The Histogram tool represents the distribution of ADC output codes for a given sample set. The accuracy of
the statistical summary can be improved by increasing hits per code, which increases the sample size at the
cost of extra test time. Select the channel to measure and the hits per code, channel, resolution, and insert the
reference voltage value. Then, press the GET HISTOGRAM button as shown in Using the Histogram Tab figure.
The cumulative effect of noise coupling to the ADC output from sources such as the input drive circuits, the
reference drive circuit, the ADC power supply, and the ADC is reflected in the standard deviation of the ADC
output code histogram that is obtained by performing multiple conversions of a DC input applied to a given
channel. Selecting the correct reference voltage gives the result in units of voltage instead of codes.
Note that any data collected the histogram tab is not saved or stored on the Capture Tab. As a result, switching
between the tabs results in lost data. Saving data on this screen does not provide the raw ADC codes but
instead saves the data presented on this tab. As a result, saving the raw codes from the capture tab and
processing the raw data is recommended.
Figure 6-8. Using the Histogram Tab
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7 Schematics, Layouts, and Bill of Materials
This section contains the ADS9817EVM schematics, printed-circuit board (PCB) layout, and bill of materials (BOM).
7.1 Schematics
Figure 7-1 through Figure 7-2 show the various connections to the ADS9817 device. The digital signals connect to J27, and the analog signals connect to
SMA connectors and input filtering. Figure 7-1 also shows the decoupling for the device.
AIN1M
55 AIN1P
54
AIN2M
2AIN2P
1
AIN3M
4AIN3P
3
AIN4M
6AIN4P
5
AIN5M
10 AIN5P
9
AIN6M
12 AIN6P
11
AIN7M
14 AIN7P
13
AIN8M
17 AIN8P
16
44
SMPL_CLKP
45
SMPL_SYNC
CS 25
32
PWDN
RESET 31
D0 34
D1 35
D2 36
D3 37
SMPL_CLKM 43
33
DCLKOUT
40
FCLKOUT
SCLK 26
SDI/EXTREF 27
SDO 28
SPI_EN 24
VBIAS
20
NC
38
NC
39
NC
50
NC
51
ADS9817IRSHT
U1A
21 AVDD_1V8
49 AVDD_1V8
15 AVDD_5V
56 AVDD_5V
22 DVDD_1V8
DVDD_1V8
47
48 DVDD_1V8
IOVDD
30
IOVDD
41
GND 7
GND 23
GND 46
IOGND 29
IOGND 42
57
Thermal_Pad
REFM 8
REFM 18
REFOUT_2V5 19
REFIO 52
REFM 53
ADS9817IRSHT
U1B
10V
C19
1µF
10V
C20
0.1µF
10V
C21
0.1µF
GND GND GND
5V
10V
C15
1µF
10V
C16
0.1µF
GND GND
10V
C23
0.1µF
GND
1V8_VDD
1V8_VDD
10V
C24
0.1µF
10V
C25
0.1µF
GND GND
1V8_IOVDD
GND GND
GND
AIN1P
AIN1M
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
AIN7P
AIN7M
AIN8P
AIN8M
REFOUT_2V5
REFIO
REFOUT_2V5
0
R4
50V
10pF
C9
0
R8
RESETz
SMPL_CLKP
SMPL_SYNC
DCLKOUT
FCLKOUT
D0
D1
D2
D3
SPI_EN
CSz
SCLK
SDI
SDO
PWDNz
DCLKOUT
FCLKOUT
D0DATA_
D1DATA_
D2DATA_
D3DATA_
SPI_EN
SCLK
CSz
SDI
SDO
PWDNz
RESETz
SMPL_CLKP
SMPL_SYNC
33
R10
33
R11
33
R12
33
R13
33
R14
33
R15
GND
10k
R6
AIN2P
AIN2M
0
R16
50V
10pF
C11
0
R20
10k
R18
AIN3P
AIN3M
0
R23
50V
10pF
C13
0
R27
10k
R25
AIN4P
AIN4M
0
R29
50V
10pF
C17
0
R33
10k
R31
AIN5P
AIN5M
0
R5
50V
10pF
C10
0
R9
10k
R7
AIN6P
AIN6M
0
R17
50V
10pF
C12
0
R21
10k
R19
AIN7P
AIN7M
0
R24
50V
10pF
C14
0
R28
10k
R26
AIN8P
AIN8M
0
R30
50V
10pF
C18
0
R34
10k
R32
GND
GND
GND
GND
GND
GND
GND
1
2
J19
1
2
J23
1
2
J20
1
2
J24
1
2
J21
1
2
J25
1
2
J22
1
2
J26
1
2 3 4
5
J1
GND
1
2 3 4
5
J2
GND
1
2 3 4
5
J9
GND
1
2 3 4
5
J10
GND
1
2 3 4 5
J3
GND
1
2 3 4 5
J4
GND
1
2 3 4 5
J11
GND
1
2 3 4 5
J12
GND
1
2
3
4
5
J5
GND
1
2
3 4 5
J6
GND
1
2 3 4 5
J7
GND
1
2 3 4
5
J8
GND
1
2
3
4
5
J13
GND
1
2
3 4 5
J14
GND
1
2 3 4 5
J15
GND
1
2 3 4
5
J16
SMPL_CLKM SMPL_CLKM
10V
C27
10µF
10V
10µF
C26
GND
GND
1
2
3
J29
1
MNT_1
MNT_2
MNT_3
MNT_4
J28
GND
60312002114503
EXT_SMPL_CLKP
EXT_SMPL_CLKP
SMPL_CLKP
FMC_SMPL_CLKP
0
R22
0
R35
GND
FMC_SMPL_CLKM
SMPL_CLKM
TP_NC_20
VIN
2
EN
1
OUTF 7
OUTS 6
GND 3
GND 4
GND 5
GND 8
REF7040QFKHT
U7
10V
C22
0.1µF
GND
5V
GND
10V
10uF
C29
GND
2 1
J30
REFIO
REFIO
Figure 7-1. ADS9817 Device Connections Schematic
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2
1
J17
GND
OUT 5
GND 2
IN
1
EN
3
NC
4
TPS7A2050PDBVR
U3
5V
GND
16V
C1
1µF
16V
1µF
C2
GND GND
IN
1
GND
2
CE
3N/C 4
ST 5
OUT 6
LM66100DCKR
U2
GND
1V8_VDD
GND
16V
C3
1µF
16V
1µF
C4
GND GND
1V8_IOVDD
GND
16V
C7
1µF
16V
C8
1µF
GND GND
2.2k
R1
Green
12
D2
APT2012LZGCK
GND
AVDD
VDD
IOVDD
EN
3
IN
1
NC
4
OUT 5
GND 2
TPS7A2018PDBVR
U4
EN
3
IN
1
NC
4
OUT 5
GND 2
TPS7A2018PDBVR
U6
SW 1
GND
2
EN
3
FB 4
VOUT 5
6VBAT
TPS61070DDCR
U5
10uH
L1
GND
16V
10uF
C5
GND
1.96M
R2
200k
R3
GND
25V
C6
22µF
GND
LDO_IN
GND 3
2
1
J18
16V
C28
1µF
GND
3P3V
6V
D1
Figure 7-2. Power Connections and Regulators Schematic
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