Texas Instruments THS4601EVM User manual

THS4601EVM
October 2002 High Performance Linear Products
User’s Guide
SLOU150

IMPORTANT NOTICE
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Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumesno liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the specified input and output ranges described in
the EVM User’s Guide.The input supply voltage (VS) should be 5 V minimum and no
greater than 15 V. Differential input signal should be no greater than 4 V. The output
current (IO) should be no greater than 100 mA.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

Information About Cautions and Warnings
v
Preface
Read This First
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It gen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.

Trademarks
vi
Electrostatic Sensitive Components
This EVM contains components that can potentially be damaged by
electrostatic discharge, Always transport and store the EVM in its
supplied ESD bag when not in use. Handle using an antistatic
wristband. Operate on an anti-static work surface. For more
information on proper handling, refer to SSYA008.
Related Documentation From Texas Instruments
The URL’s below are correct as of the date of publication of this manual. Texas
Instruments applications apologizes if they change over time.
-THS4601 data sheet (literature number SLOS388)
-Application report (literature number SLMA002), Power Pad Thermally
Enhanced Package,
http://www-s.ti.com/sc/psheets/slma004/slma002.pdf
-Application report (literature number SLMA004), Power Pad Made Easy,
http://www-s.ti.com/sc/psheets/slma004/slma004.pdf
-Application report (literature number SSYA008), Electrostatic Discharge
(ESD), http://www-s.ti.com/sc/psheets/ssya008/ssya008.pdf
-Application report (literature number SLOA102), High Speed PCB Layout
Tips, http://www-s.ti.com/sc/psheets/sloa102/sloa102.pdf
Trademarks
PowerPAD is a trademark of Texas Instruments.

Contents
vii
Contents
1 Introduction and Description 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Evaluation Schematic 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Using the EVM 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 EVM Applications 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Noninverting Gain Stages 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Inverting Gain Stages 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Transimpedance Amplifier 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 T-Network Gain Stages 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Transimpedance Networks 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 EVM Hardware Description 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viii
Figures
1-1 Schematic of the THS4601EVM 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Test Equipment Connections 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Default Configuration—DC-Coupled, Dual Power Supply, Non-Inverting Gain Stage 3-1. . .
3-2 AC-Coupled, Single Power Supply, Noninverting Gain Stage 3-2. . . . . . . . . . . . . . . . . . . . . . .
3-3 DC-Coupled, Dual Power Supply, Inverting Gain Stage 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 AC-Coupled, Single Power Supply, Inverting Gain Stage 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 Wideband Photodiode Transimpedance Amplifier 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 Parasitic Capacitances in Photodiode Applications 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 Transimpedance Circuit Bode Plot 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 Transimpedance Gains 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 Simplified EVM Schematic for Inverting Gain 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 SimplifiedEVM Schematic for Noninverting Gain 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 Single Real Pole 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12 Single Real Zero 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-13 Single Real Pole and Single Real Zero (Second Configuration) 3-11. . . . . . . . . . . . . . . . . . . .
3-14 Two Real Poles, One Real Zero 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-15 One Real Pole, Two Complex Zeros 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 Board Layout Views 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
4-1 THS4601EVM Bill of Materials 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction and Description
Introduction and Description
This EVM provides a platform for testing the THS4601 in 8-pin SOIC
PowerPADt(DDA) package. It contains the high-speed op amp, a number of
passive components, and various features and footprints that enable the user
to experiment, test, and verify various operational amplifier circuit
implementations.
Chapter 1

Evaluation Schematic
1-2
1.1 Evaluation Schematic
As delivered, the EVM has a fully functional example circuit—just add power
supplies, a signal source, and monitoring instrument. See Figure 1-1 for a
complete schematic diagram. EVM features include:
-Wide operating supply voltage range: ±5 V to ±15 V operation (see the
device data sheet)
-Inverting and noninverting gain configurations supported
-Single supply capability—R5 through R7 to provide internal or external
reference to the noninverting input
-Z1 through Z3 for ac coupling
-Nominal 50-Ωinput impedance (R2 or R1). Termination can be configured
according to the application requirement.
-1-kΩ load resistor R8. 1-kΩis the standard data sheet load impedance.
-Footprints for a series resistor (Z3) or an A/D compensation network (Z3
and Z9)
-T-network in the feedback path can also be used to implement
transimpedance networks
-Power supply ripple rejection capacitors (C3 and C6)
-Decoupling capacitors (C4, C5, C7, C8, C9, C10)
-Test point for connection of a high impedance scope probe to op amp
output (TP3)
-Convenient GND test points (TP1 and TP2)
-PowerPAD heatsinking capability
-A good example of high-speed amplifier PCB design and layout

Evaluation Schematic
1-3
Introduction and Description
Figure 1-1.Schematic of the THS4601EVM
R3
100 Ω
VS+
C6
22 µF
J3
Vout
Z4 *
+C3
22 µF
R7
*
R6
*
C5
1000 pF C2
100 pF
Z5
100 Ω
TP1
J2
Vin+
C4
0.1 µFC8
1000 pF
TP2
J5
GND
R5
*
-
+
U1
THS4601
6
C1
100 pF
VS+
R2
49.9 ΩR8
1 kΩ
Z1 0 Ω
Z6
*
J4
VS-
FB2
FB1
Z3
49.9 Ω
VS-
C7
0.1 µF
VS+
VS-
*
J7
Vref
Z9
*
Z2
R4 *
J1
Vin-
R1
0
7
2
3
4
TP3
Vout
J6
VS+
0 Ω
+
* Means the associated component is not installed on the EVM

2-1
Using the EVM
Using the EVM
Figure 2-1 shows how to connect power supplies, signal source and monitor-
ing instrument. It is recommended that the user connect the EVM as shown
to avoid damage to the EVM or the op amp installed on the board.
Figure 2-1.Test Equipment Connections
Chapter 2

3-1
EVM Applications
EVM Applications
Example applications are presented in this chapter. These applications are
meant to demonstrate the most popular circuits to the user, but many other
circuits can be constructed. The user is encouraged to experiment with
different circuits, exploring new and creative design techniques. That is the
function of an evaluation board.
3.1 Noninverting Gain Stages
Figure 3-1.Default Configuration—DC-Coupled, Dual Power Supply, Noninverting Gain
Stage
R2
49.9 Ω
Z1 0
VS-
-+
U1
THS4601
2
36
7
4
Z3
49.9 Ω
R3
100 Ω
J2
Vin+
TP3
Vout
R8
1 kΩ
Z5
100 Ω
R1
0
VS+
J3
Vout
Z2 0
*Power supply decoupling is not shown
Note: This schematic reflects the default THS4601EVM configuration.
The gain measured from J2 to J3 is 2 when measured with a high impedance
instrument at TP3 or J3, as determined by:
Vout
Vin)
+1)Z5
R3
The user might note that R3 and Z5 appear to be rather small resistances.
These values were selected to avoid creating a low pass pole with the input
capacitance of the THS4601.
Chapter 3

Noninverting Gain Stages
3-2
Figure 3-2.AC-Coupled, Single Power Supply, Noninverting Gain Stage
R8
1 kΩ
R6
Z1
Z2
J7Vref
J2
Vin+ -
+
U1
THS4601
2
36
7
4
J3
Vout
TP3
Vout
R1
0
VS+
Z3
VS+
R5
Z5
100 Ω
R7
R2
49.9 Ω
R3
100 Ω
*Power supply decoupling is not shown
Ω
Z1 through Z3 are populated with dc-blocking capacitors, selected so they do
not interfere with the frequencies that are of interest. These capacitors create
high pass characteristics. R5 through R7 are selected to produce a dc
potential on the noninverting input equal, or close to VS+ divided by 2. The
THS4601 has low input bias currents, which allow larger bias setting resistors.
If the user prefers, an external potential can be introduced at J7—use only R7
and R5. If the source of VS+ in the system is noisy, and there is a less noisy
potential available in the system, it can be connected to J7. R7 and R5 can then
be used as a voltage divider off of the reference attached to J7 to create the
VS+ divided by 2 potential.
The gain measured from J2 to J3 is 2, and is still determined by:
Vout
Vin)
+1)Z5
R3 (in the passband of the stage).

Inverting Gain Stages
3-3
EVM Applications
3.2 Inverting Gain Stages
Figure 3-3.DC-Coupled, Dual Power Supply, Inverting Gain Stage
VS-
-
+
U1
THS4601
7
4
VS+
J1
Vin- Z1 0 R3
100 
R1
61.9 
Z5
100 
2
36
TP3
Vout
Z3
49.9 
R8
1 k 
J3
Vout
Z2 0 
R2
0 
*Power supply decoupling is not shown
The Gain measured from J1 to J3 is 1, as determined by:
Vout
Vin*
+*Z5
R3
The circuit provides approximately 50 Ωof input impedance, as determined
by R1 || R3 (because R3 is at ground potential due to the action of the ideal
op amp model).
Figure 3-4.AC-Coupled, Single Power Supply, Inverting Gain Stage
-U1
THS4601
27
VS+
J1
Vin- Z1
R1
64.9 
R3
100 
Z5
100 
R6
R7
R5
R2
0 
Z2
J7
Vref
VS+
3
4
+6
TP3
Vout
Z3
R8
1 k
J3
Vout
*Power supply decoupling is not shown
Z1 and Z3 are populated with dc-blocking capacitors, selected so they do not
interfere with the frequencies that are of interest. These capacitors create high
pass characteristics. R5 through R7 are selected to produce a dc potential on
the noninverting input equal, or close to VS+ divided by 2. The THS4601 has
low input bias currents, which allow larger bias setting resistors. If the user

Transimpedance Amplifier
3-4
prefers, an external potential can be introduced at J7, and use only resistors
R7 and R5. If the source of VS+ in the system is noisy, and there is a less noisy
potential available in the system, it can be connected to J7. R7 and R5 can then
be used as a voltage divider off the reference attached to J7 to create the VS+
divided-by-2 potential.
The gain measured from J1 to J3 is 1 in the passband, and is still determined
by:
Vout
Vin*
+*
Z5
R3 (in the passband of the stage).
The circuit provides approximately 50 Ωof input impedance within the
passband, as determined by R1 || R3 (because R3 is at a virtual ground
potential due to the action of the ideal op amp model and the decoupling
capacitor Z2).
3.3 Transimpedance Amplifier
At first sight this may not appear to be an amplifier at all, but in reality the input
is a current and the gain of the amplifier is measured in Ω, rather than volts/volt.
This configuration is often used in applications where the output of a
transducer is current or charge, i.e., photodiode. Applications include optical
power measurements in optical networks, x-ray machines (measuring light
power once the x-rays have been converted to light), and photomultiplier tube
amplifiers.
Due to the capacitance associated with the transducer, a pole has to be
created in the feedback loop to ensure stability.
The wide bandwidth and high operating voltage capability of the THS4601
make it unique in the applications by enabling it to offer wide output swings,
thereby delivering higher dynamic ranges in a single stage.
Typically, design of a transimpedance circuit is driven by the characteristics of
the current source that provides the input to the gain block. A photodiode is the
most common example of a capacitive current source that would interface with
a transimpedance gain block. Continuing with the photodiode example, the
system designer traditionally chooses a photodiode based on two opposing
criteria: speed and sensitivity. Faster photodiodes cause a need for faster gain
stages, and more sensitive photodiodes require higher gains, in order to
develop appreciable signal levels at the output of the gain stage.
These parameters affect the design of the transimpedance circuit in a few
ways. First, the speed of the photodiode signal determines the required
bandwidth of the gain circuit. However, the required gain, based on the
sensitivity of the photodiode, limits the bandwidth of the circuit. Additionally,
the larger capacitance associated with a more sensitive signal source detracts
from the achievable speed of the gain block. The dynamic range of the input

Transimpedance Amplifier
3-5
EVM Applications
signal also places requirements on the amplifier’s dynamic range. Knowledge
of the source’s output current levels, coupled with a desired voltage swing on
the output, dictates the value of the feedback resistor, R4. The transfer
function from input to output is VOUT = IINRF.
The large gain-bandwidth product of the THS4601 provides the capability for
achieving both high transimpedance gain and wide bandwidth simultaneously.
In addition, the high power supply rails provide the potential for a very wide
dynamic range at the output, allowing for the use of input sources which
possess wide dynamic range. The combination of these characteristics makes
the THS4601 a design option for systems that require transimpedance
amplification of wideband, low-level input signals. A standard transimpedance
circuit is shown in Figure 3-5.
Figure 3-5.Wideband Photodiode Transimpedance Amplifier
U1
7
VS+
-Vbias
J1
Vin-
PHOTODIODE
Z1 0 R3 0 
Z5
R4 Z4 0 
2
3
4
6
THS4601
VS+
VS-
TP3
Vout
-
+
R5
0 
Z3 0 
J3
Vout
As indicated, the current source typically sets the requirements for gain,
speed, and dynamic range of the amplifier. For a given amplifier and source
combination, achievable performance is dictated by the following parameters:
the amplifier’s gain-bandwidth product, the amplifier’s input capacitance, the
source capacitance, the transimpedance gain, the amplifier’s slew rate, and
the amplifier’s output swing. From this information, the optimal performance
of a transimpedance circuit using a given amplifier can be determined. Optimal
is defined here as providing the required transimpedance gain with a
maximally flat frequency response.
For the circuit shown in Figure 3-5, all but one of the design parameters are
known; the feedback capacitor must be determined. Proper selection of the
feedback capacitor prevents an unstable design, controls pulse response
characteristics, provides maximally flat transimpedance bandwidth, and limits
broadband integrated noise. The maximally flat frequency response results in
Z5 calculated as shown below, where Z5 is the feedback capacitor, R4 is the
feedback resistor, CSis the total source capacitance (including amplifier input
capacitance and parasitic capacitance at the inverting node), and GBP is the
gain-bandwidth product of the amplifier in Hertz.

Transimpedance Amplifier
3-6
Z5 +
1
p(R4)GBP )ǒ1 p(R4)GBPǓ2
)4CS
p(R4)GBP
Ǹ2
Once the optimal feedback capacitor has been selected, the transimpedance
bandwidth can be calculated:
F–3dB +GBP
2p(R4)ǒCS)Z5Ǔ
Ǹ
The total source capacitance CSis the sum of several distinct capacitances
as shown in Figure 3-6.
Figure 3-6.Parasitic Capacitances in Photodiode Applications
_
+
CIDIFF
CICM
CPRF
CF
CD
IDIODE
CS= CICM + CIDIFF + CP+ CD
where
CICM is the common-mode input capacitance.
CIDIFF is the differential input capacitance.
CDis the diode capacitance.
CPis parasitic capacitance at the inverting node.
As shown in Figure 3-7, the feedback capacitor provides a pole in the noise
gain of the circuit, counteracting the zero in the noise gain caused by the
source capacitance. The pole is set such that the noise gain achieves a 20 dB
per decade rate-of-closure with the open-loop gain response of the amplifier,
resulting in a stable circuit. As indicated, the formula given provides the
feedback capacitance for maximally flat bandwidth. Reduction in the value of
the feedback capacitor can increase the signal bandwidth, but this occurs at
the expense of peaking in the ac response.

Transimpedance Amplifier
3-7
EVM Applications
Figure 3-7.Transimpedance Circuit Bode Plot
20 dB/Decade
Rate-of-Closure
GBP
20 dB/
Decade
-20 dB/
Decade
AOL
Noise Gain
0
Gain
Zero Pole f
The performance of the THS4601 has been measured for a variety of
transimpedance gains with a variety of source capacitances. The achievable
bandwidths of the various circuit configurations are summarized numerically
in the data sheet, SLOS388.
Note that the feedback capacitances do not correspond exactly with the values
predicted by the equation. They have been tuned to account for the parasitic
capacitance of the feedback resistor (typically 0.2 pF for 0805 surface mount
devices) as well as the additional capacitance associated with the PC board.
The equation should be used as a starting point for the design, with final values
for Z5 optimized in the laboratory. Figure 3-8 shows 10 kΩ, 100 kΩ, and 1 MΩ
transimpedance gains for various values of feedback capacitors.

T-Network Gain Stages
3-8
Figure 3-8.Transimpedance Gains
65
70
75
80
85
90
10 k 100 k 1 M 10 M 100 M
Frequency - Hz
Transimpedance Gain - dB
10 kΩTRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
CS= 18 pF, CF= 2.2 pF
CS= 47 pF,
CF= 3.3 pF
CS= 100 pF,
CF= 3.9 pF
CS= 220 pF,
CF= 5.6 pF 60
65
70
75
80
85
90
95
100
105
10 k 100 k 1 M 10 M
CS= 18 pF,
CF= 0.6 pF
CS= 47 pF,
CF= 0.6 pF
CS= 100 pF,
CF= 1.5 pF
CS= 220 pF,
CF= 1.8 pF
Frequency - Hz
Transimpedance Gain - dB
100 kΩTRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
90
95
100
105
110
115
120
125
130
10 k 100 k 1 M 10 M
CS= 18 pF, CF= 0
CS= 47 pF,
CF= 0
CS= 100 pF,
CF= 0
CS= 220 pF,
CF= 0.4 pF
Frequency - Hz
Transimpedance Gain - dB
1 MΩTRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
3.4 T-Network Gain Stages
To get higher transimpedance gains a T-Network is sometimes used. The
components in the feedback path of the op amp that are shown in Figure 3-9
can be used to create either a purely resistive T-Network covered in this
section, or a transimpedance network which is covered in the next section.