T
D
tDtSU tSD tDtSU tSD tDtSU tSD
DMIN DMAX
T T
DIM
IF
Tt+t
=
DSUD
MIN
1
=T PWM
fT
=tT - SD
DMAX
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Pulse Width Modulation (PWM) Dimming
R.35 = 0.2 / IF(3)
This resistor should be rated to handle the power dissipation of the LED current. For example, the closest
5% tolerance resistor to set an LED current of 0.35A is 0.56Ω. In steady state this resistor will dissipate
(0.352x 0.56) = 69 mW, indicating that a resistor with a 1/8W rating is more than capable of dissipating
the power.
5 Pulse Width Modulation (PWM) Dimming
The DIM1 terminal on the PCB provides an input for a logic-level pulse width modulation signal for
dimming of the LED array. In order to fully enable and disable the LM3406HV the PWM signal should
have a maximum logic low level of 0.8V and a minimum logic high level of 2.2V. Graphical representations
of minimum and maximum PWM duty cycle are illustrated in Figure 3. The interval tDrepresents the delay
from a logic high at the DIM pin to the rise in output current. The quantities tSU and tSD represent the time
needed for the output current to slew up to steady state and slew down to zero, respectively. It is
important to note that tDis a property of the LM3406HV and remains fixed in all applications. The slew
rates tSU and tSD are a function of the external circuit parameters VIN, VO, IF, inductance (L) and the
LM3406HV parameter tOFF-MIN. Response times for a circuit driving three white LEDs at 1A from 24V are
shown in the Typical Performance Characteristics section, but the user should test every new circuit to
determine the actual PWM dimming response.
Figure 3. PWM Dimming Limits
The logic of DIM1 is active low, hence the LM3406HV will deliver regulated output current when the
voltage at DIM1 is high, and the current output is disabled when the voltage at DIM1 is low. Connecting a
constant logic low will disable the output. Note that an internal pullup esnures that the LM3406HV is
enabled if the DIM pin is open-circuited. The DIM1 function disables only the power MOSFET, leaving all
other circuit blocks functioning to minimize the converter response time, tD.
The DIM2 terminal provides a second method for PWM dimming by connecting to the gate of MOSFET
Q1 through the driver U5.Q1 provides a parallel path for the LED current. Shunting the output current
through a parallel MOSFET reduces the PWM dimming delays because the inductor current remains
continuous, providing faster response time for higher frequency and/or greater resolution in the PWM
dimming signal. The trade-off in this method is that the full current flows through Q1 while the LED is off,
resulting in lower efficiency. The LM3406HV evaluation board includes an output capacitor to reduce
output current ripple which is not initially populated, but the drawback of this output capacitor if used is
that it causes significant delays when using parallel MOSFET dimming. The output capacitor should be
removed to take full advantage of parallel MOSFET dimming.
3
SNVA407B–August 2009–Revised May 2013 AN-1993 LM3406HV Evaluation Board with 2 Wire Dimming
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