Texas Instruments bq24195/L User manual

User's Guide
SLUUA18–October 2012
bq24195/L EVM (PWR193) User’s Guide
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Features ...................................................................................................... 2
1.2 Design Considerations ............................................................................................ 2
1.3 General Descriptions .............................................................................................. 2
1.4 I/O Description ...................................................................................................... 2
2 Test Summary ............................................................................................................... 3
2.1 Equipment ........................................................................................................... 3
2.2 Equipment Setup ................................................................................................... 5
2.3 Procedure ........................................................................................................... 6
3 PCB Layout Guideline .................................................................................................... 10
4 Board Layout, Schematic, and Bill of Materials ....................................................................... 11
4.1 Board Layout ...................................................................................................... 11
4.2 Schematic ......................................................................................................... 17
4.3 Bill of Materials .................................................................................................... 18
List of Figures
1 Connections of the HPA172 Kit........................................................................................... 5
2 Original Test Setup for PWR193 (bq24195/L EVM) ................................................................... 5
3 Main Window of the bq24195x Evaluation Software for bq24195/L ................................................. 6
4 CHG Mode Ripple and Duty Cycle: VBUS = 5 V, VBAT = 3.7 V.......................................................... 8
5 Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V ...................................................................... 9
6 bq24195/L EVM Top Layer............................................................................................... 11
7 bq24195/L EVM Second Layer.......................................................................................... 12
8 bq24195/L EVM Third Layer............................................................................................. 13
9 bq24195/L EVM Bottom Layer........................................................................................... 14
10 bq24195/L EVM Top Assembly.......................................................................................... 15
11 bq24195/L EVM Bottom Assembly...................................................................................... 16
12 bq24195/L EVM Schematic .............................................................................................. 17
List of Tables
1 EVM Connections........................................................................................................... 2
2 Jumper Connections........................................................................................................ 3
3 Recommended Operating Conditions.................................................................................... 3
4 Device ID JEITA Settings.................................................................................................. 9
5 Bill of Materials............................................................................................................. 18
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Introduction www.ti.com
1 Introduction
1.1 EVM Features
Refer to the data sheet (SLUSB97) for detailed features and operation.
1.2 Design Considerations
This EVM has protection circuitry, external to the IC, to protect against applying a power source to the
input (VBUS) when the IC is in boost mode, converting battery power to a 5-VDC PMID output. This is
accomplished by two circuits on the EVM schematic by (1) adding an isolation circuit consisting of Q1, its
drive Q3, to apply input power when available and disconnect it when not available and (2) by pulling OTG
low, with Q2, when the input is available. Pulling OTG low disables the boost-mode operation.
The OTG pin should be pulled low at least a few microseconds before the input power is applied via Q1.
This is accomplished on this EVM by setting the drive resistance for Q2 (OTG ckt.) lower and drive
resistance for Q3 (VBUS connection) higher. The voltage threshold and resistance of the driver along with
the input capacitance of Q2 and Q3 set the desired timing sequencing. Q3 (VBUS turn on) has a
Thevinen-equivalent drive of 72k and for Q2 (OTG ckt.) is 35k, allowing the OTG signal to be pulled low
(disables Boost Mode) prior to the input voltage being applied.
1.3 General Descriptions
The bq24195/L evaluation module is a complete charger module for evaluating an I2C Controlled single
NVDC-1 charge using the bq2419x devices.
The bq24195/L EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24195/L EVM
must order USB-to-GPIO interface board separately.
For details, see bq24195/L data sheet.
1.4 I/O Description
Table 1 contains the jumper connections for this EVM.
Table 1. EVM Connections
Jack Description
J1–VIN Input: positive terminal
J1–GND Input: negative terminal (ground terminal)
J2-SYS Connected to system
J2-BAT+ Connected to battery pack
J2-GND Ground
J3 USB-to-GPIO connector (USB Interface Adapter
Connector - HPA172)
J4–INT INT pin connection
J4– OTG OTG pin connection
J4-CE CE pin connection
J4-GND Ground
J5-PMID PMID pin connection or power bank output
J5-GND Ground
J6-TS2 External TS2 pin connection
J6-GND Ground
J7 Mini_USB Connector
J5-TS2 External TS2 pin connection
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www.ti.com Test Summary
Table 2 lists the controls and key parameter settings for this EVM.
Table 2. Jumper Connections
Jack Description Factory Setting
JP1 TS1 to TS2 connection Shunt installed
JP2 D- 20k pull down Shunt not installed
JP3 VSYS pull-up for STAT, CE, INT Shunt installed
JP4 USB current limit selection pin during buck mode and PSEL is high (JP1-High); Shunt not installed
enable pin during boost mode.
In buck mode: OTG = High, IIN limit = 500 mA;
OTG = Low, IIN limit = 100 mA.
The boost mode is activated when the REG01[5:4] = 10 and OTG pin is HIGH.
JP5 /CE pin setting: Pull low to enable the charge Shunt not installed
(GUI also can pull CE low)
JP6 200-Ωshort between D+ and D- Shunt not installed
JP7 TS2 resistor divider pull-up source (REGN) connection Shunt installed
JP8 Internal 10k to ground to TS2 Shunt installed
JP9 D+ 20k Pull down Shunt not installed
Table 3 lists the recommended operating conditions for this EVM.
Table 3. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
Supply voltage, VIN Input voltage from AC adapter input 3.9 5/12 6 V
Battery voltage, VBAT Voltage applied at VBAT terminal 0 3.7 4.25 V
Supply current, IAC Maximum input current from AC adapter 0 3 A
input
Output current, IOUT Output current 0 4 A
Operating junction temperature 0 125 °C
range, TJ
2 Test Summary
Section 2.1 –Section 2.3 explain the equipment, the equipment setup, and the test procedures.
2.1 Equipment
2.1.1 Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle larger voltage and current, it is not necessary for this procedure.
2.1.2 Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V)
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
2.1.3 Load #2 – Use with Boost Mode
PMID-to-GND load, 10 Ω, 5 W or greater
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Test Summary www.ti.com
2.1.4 Meters
Six Fluke 75 multimeters, (equivalent or better)
Or:
Four equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 5 A+ current.
2.1.5 Computer
A computer with at least one USB port and a USB cable. The bq2419xEVM evaluation software must be
properly installed.
2.1.6 USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
2.1.7 Software
Unzip the bq2419xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Windows™ XP and Windows 7 operating systems.
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S
PWR193
bq2419x-EVM
J4
To Computer
USB Port
USB Interface
Adapter
I/O
USB
10-pin
Ribbon Cable
‘To EVM’
Texas Instruments
©2006
www.ti.com Test Summary
2.2 Equipment Setup
1. Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VBUS and GND).
3. Connect a voltage meter across J1 (VBUS) and J1 (GND).
4. Turn on the Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load. Connect
Load in series with a current meter (multimeter), ground side, to J2 (BAT+ and GND) as shown in
Figure 2.
5. Connect a voltage meter across J2 (BAT+ and GND).
6. Connect the HPA172 USB interface adapter to the computer with a USB mini-cable and to J3 with the
10-pin ribbon cable. The connections are shown in Figure 1.
Figure 1. Connections of the HPA172 Kit
Figure 2 shows the test setup for PWR193.
7. Install shunts as shown in Table 2.
Figure 2. Original Test Setup for PWR193 (bq24195/L EVM)
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Test Summary www.ti.com
8. Turn on the computer. Launch the bq2419xEVM evaluation software. The main window of the software
is shown in Figure 3.
Figure 3. Main Window of the bq24195x Evaluation Software for bq24195/L
2.3 Procedure
Follow the steps and verify the outputs and IC for the EVM.
2.3.1 Current Settings
1. Make Sure EQUIPMENT SETUP steps are followed.
ILIM Setting: Set the potentiometer to its lowest value for max input current by connecting an ohm-
meter between point TP9 and ground. Turn the screw on the potentiometer counterclockwise until the
resistance drops to its lowest point (approximately 169 Ω, the value of R7)
2. Launch the BQ2419x EVM GUI software, if not already done
3. Turn on PS#1
Measure →V (J2(SYS), J2(GND)) = 4.10 ±300 mV
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www.ti.com Test Summary
2.3.2 Charge Voltage and Current Regulation of VIN and Device ID Verification
Follow the steps and verify the outputs and IC for the EVM.
2.3.2.1 Software setup (all of Section 2.3.2.1 is done in the GUI):
1. Device address: bq24195/L (6B)
2. Click the Read button
3. Select Disabled for I2C Watchdog Timer Limit
4. Set Input Voltage Limit to 4.2 V
5. Set Input Current Limit to 500 mA
6. Set Charge Voltage Limit to 4.208 V
7. Set Fast Charge Current, ICHG to 512 mA
8. Set Pre-Charge Current to 256 mA
9. Deselect Enable Termination (see the following image)
10. Click the Read button twice
Observe →Everything normal at FAULT box
Observe →D1 (STAT) is on, except the bq24192IEVM
2.3.2.2 Enable Load#1 from Section 2.2 step 4. Measure the voltage across J2 at two different points:
V(J2(SYS), J2(GND)) and V(J2(BAT), J2(GND))
Measure →V(J2(SYS), J2(GND)) = 3.65 V ±300 mV
Measure →V(J2(BAT), J2(GND)) = 2.5V ±200 mV
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CHG Mode: Vbus = 5 V Vbat = 3.7 V
Vsw
Vpmid_AC coupled
Vsys_AC coupled
C2
C1
C3
Test Summary www.ti.com
2.3.2.3 Increase the Constant Voltage Load to 3.7 VDC
Measure →V(J2(SYS), J2(GND)) = 3.75 V ±200 mV
Measure →IBAT = 500 mA ±200 mA
Measure →V(J2(BAT), J2(GND)) = 3.7 V ±200 mV
2.3.2.4 In the software, set Fast Charge Current, ICHG to 1.012 A
Measure →IIN = 500 mA ±200 mA
2.3.2.5 Verify Scope Measurements (See Figure 4 – 500 ns/div)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high frequency spikes < 10 mV
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.25 MHz and 1.5 MHz, duty cycle between 73% and
81%
C3 (AC coupled 20 mV/div): Vac_VSYS (TP3 to GND) - excluding high frequency spikes < 15 mV
Figure 4. CHG Mode Ripple and Duty Cycle: VBUS =5V,VBAT = 3.7 V
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Boost Mode: Vbat = 3.7 V
Vsw
Vprnid_AC coupled
C2
C1
www.ti.com Test Summary
2.3.2.6 Switch to Boost Mode
1. Turn off and disconnect PS#1
2. If the constant voltage load connected from BAT+ to GND is not a four-quadrant supply (sources
current) remove the load and use the power source disconnected in step one, set to 3.7 V and 2 A
current limit and connect between BAT+ and GND
3. Apply 10 Ω(5 W or greater) across J5 (PMID(+) to GND(–)
4. Uncheck the OTG Low box in the GUI
5. Select OTG in the Configuration drop-down window
6. Verify VPMID to GND on J5 is between 4.9 V and 5.3 V
7. Verify scope measurement (Figure 5)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high-frequency spikes
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.2 MHz and 1.7 MHz, Duty cycle between 67%
and 74%
Figure 5. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
2.3.2.7 Verify Device ID JEITA shown in software matches Table 4
Table 4. Device ID JEITA Settings
Assembly Number EVM Part Number Device ID JEITA
PWR193-001 bq24195LEVM-021 100 Disabled
PWR193-002 bq24195EVM-021 100 Disabled
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PCB Layout Guideline www.ti.com
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ωresistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
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www.ti.com Board Layout, Schematic, and Bill of Materials
4 Board Layout, Schematic, and Bill of Materials
4.1 Board Layout
Figure 6 through Figure 11 illustrate the board layouts for this EVM.
Figure 6. bq24195/L EVM Top Layer
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Figure 7. bq24195/L EVM Second Layer
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Figure 8. bq24195/L EVM Third Layer
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Board Layout, Schematic, and Bill of Materials www.ti.com
Figure 9. bq24195/L EVM Bottom Layer
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www.ti.com Board Layout, Schematic, and Bill of Materials
Figure 10. bq24195/L EVM Top Assembly
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Board Layout, Schematic, and Bill of Materials www.ti.com
Figure 11. bq24195/L EVM Bottom Assembly
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VIN
3.4 - 4.4V, 2.5A
BAT+
TS2
GND
GND
NC
SW
TEST POINTS
INT
OTG
/CE
GND
PGND PGND
1
2
3
4
5
Mini_USB
GND
System Output
3.9 to 6V
1Not installed
2
PMID
2See BOM for component usage
1
11
1
1
2 2
1
1
1
GND
3.9 to 6V
2
1
1
1VBUS
2D+/PSEL
3D-/PG
4STAT
5SCL
6SDA
7INT
8OTG/IUSB
9CE
10ILIM
11 TS1 12TS2
13
BAT
14
BAT
15
SYS
16
SYS
17
PGND
18
PGND
19
SW
20
SW
21
BTST
22
REGN
23
PMID
24
VBUS
25
PWPD
U1
BQ24195(L)RGE
C5 47nF
C6 4.7uF
C10
1.0uF
R14
2.21k
R7
169
R21
30.1k
R22
5.23k
1
2
J6
R12 200
R13 200
1
2
3
4
J4
JP8
R20
10.0k
1
2
3
J2
TP2
TP10
TP6 TP7 TP8
TP9
TP1
TP3
TP4
TP5
TP12
TP11
D1
LTST-C190GKT
TP13
TP14 TP15 TP16 TP17
JP7
C1
1.0uF
C4
10uF
C7
10uF
C8
10uF
C9
0.1uF
C11
10uF
TP18
R8
10.0k
JP5
1
2
3
4
5
6
7
8
9
10
J3
R23
R6
R11
10.0k
JP4
R4 200
JP6
JP3
R24
768
R15
10.0k
C13
R1
0
R2
0
C15
10uF
J7
C3 C12
C16
10uF
C17 C18
TP19
L1
2.2uH
JP1
3
1
2
5
6
7
4
8
Q1
CSD25302Q2
R16
10.0k
R5 100k
R1710.0k
R18 261k
R19121k
R2549.9k
C19
10uF
JP2
JP9
R9
20k
R26
20k
R27
200
C20
1.0uF
C14
Open
C2
C21
C22
1
2
J1
1
2
J5
R3
0
1
3
2
Q3
Si2312DS
1
3
2
Q2
Si2312DS
TP20
1
1
1
1
1
1 1 1 1
1
1
1
1
1
11
1
1
1
1
1
1
1
1 1 1 1
1
1
1
1
1
TS1
TS2
STAT
STAT
PULL-UP
REGN
TS2
D-
D+
D+
REGN
STAT
D-
ILIM
SDA SCL
D+ INT
OTG /CE TS1 TS2
INT
OTG
/CE
REGN
PULL-UP
PULL-UP
PULL-UP
INT
PULL-UP
/CE
OTG
SCL
SDA
SCL
/CE
SDA
VBUS
VIN
D-
PULL-UP
ILIM
SYS
VIN
www.ti.com Board Layout, Schematic, and Bill of Materials
4.2 Schematic
Figure 12 illustrates the schematic for this EVM.
Figure 12. bq24195/L EVM Schematic
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4.3 Bill of Materials
Table 5 contains the bill of materials.
Table 5. Bill of Materials
-001 -002 RefDes Value Description Size Part MFR
Number
2 2 C1, C20 1.0 µF Capacitor, ceramic, 25 V, X7R, 10% 1206 STD STD
1 1 C10 1.0 µF Capacitor, ceramic, 10 V, X7R, 10% 0805 STD STD
1 1 C11 10 µF Capacitor, ceramic, 10 V, X5R, 10% 0603 STD STD
1 1 C14 Open Capacitor, ceramic, 10 V X5R, 10% 0805 STD STD
0 1 C16 10 µF Capacitor, ceramic, 10 V, X5R, 10% 1206 STD STD
0 2 C17, C18 22 µF Capacitor, ceramic, 10 V, X5R, 20% 1206 STD STD
3 3 C2, C21, C22 Open Capacitor, ceramic 0603 STD STD
2 2 C3, C12 Open Capacitor, ceramic, 10 V X5R, 10% 1206 STD STD
2 2 C4, C15 10 µF Capacitor, ceramic, 25 V, X5R, 10% 0805 STD STD
1 1 C5 47 nF Capacitor, ceramic, 16 V, X7R, 10% 0603 STD STD
1 1 C6 4.7 µF Capacitor, ceramic, 16 V, X7R, 10% 0603 STD STD
3 3 C7, C8, C19 10 µF Capacitor, ceramic, 25 V X5R, 10% 0805 STD STD
2 2 C9, C13 0.1 µF Capacitor, ceramic, 25 V, X7R, 10% 0603 STD STD
1 1 D1 LTST-C190GKT Diode, LED, green, 2.1 V, 20 mA, 6 mcd 0603 LTST-C190GKT Lite On
2 2 J1, J5 ED120/2DS Connector, 15 A, 300 V male 2 pole, 5.08 mm 9 × 12 mm ED120/2DS On Shore
Tech
1 1 J2 ED120/3DS Terminal block, 3 pin, 15 A, 5.1mm 0.60 × 0.35 inch ED120/3DS OST
1 1 J3 N2510-6002RB Connector, male straight 2 × 5 pin, 100 mil 0.338 × 0.788 in N2510-6002RB 3M
spacing, 4 wall
1 1 J4 ED555/4DS Terminal block, 4 pin, 6 A, 3.5 mm 0.55 × 0.25 in ED555/4DS OST
1 1 J6 PEC02SAAN Header, Male 2 pin, 100 mil spacing, 0.100 in × 2 PEC02SAAN Sullins
1 1 J7 A-USB B-M5 Connector, USB-B, mini, 5 pins 0.354 × 0.307 in A-USB B-M5
9 9 JP1, JP2, JP3, PEC02SAAN Header, Male 2 pin, 100mil spacing, 0.100 in × 2 PEC02SAAN Sullins
JP4, JP5, JP6,
JP7, JP8, JP9
1 1 L1 2.2 µH Inductor, SMT, 5 A, 37 mΩ0.204 × 0.216 in IHLP2020BZER2R2M11 Vishay
1 1 Q1 CSD25302Q2 Trans, P-Channel NexFET, 20 V, 5 A, 56 mΩSON 2 × 2 CSD25302Q2 TI
2 2 Q2, Q3 Si2312DS MOSFET, N-Channel, 20 V, 4.9 A, 33 mΩSOT23 Si2312DS Vishay
1 1 R1 0 ΩResistor, chip, 1/16W, 0603 STD STD
1 1 R14 2.21 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R15 10.0 kΩPotentiometer, 3/8 cermet, single-turn 0.25 × 0.17 in 3266W-1-103LF Bourns
1 1 R18 261 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R19 121 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R2 0 ΩResistor, chip, 0.6W, 1% 2010 STD STD
1 1 R21 30.1 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R22 5.23 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R24 768 ΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R25 49.9 kΩResistor, chip, 1/16W, 1% 0603 STD STD
1 1 R3 0 ΩResistor, chip,1/2W, yy% 1210 STD STD
4 4 R4, R12, R13, 200 ΩResistor, chip, 1/16W, 1% 0603 STD STD
R27
1 1 R5 100 kΩResistor, chip, 1/16W, 1% 0603 STD STD
2 2 R6, R23 Open Resistor, chip, 1/16W 0603 STD STD
1 1 R7 169 ΩResistor, chip, 1/16W, 1% 0603 STD STD
5 5 R8, R11, R16, 10.0 kΩResistor, chip, 1/16W, 1% 0603 STD STD
R17, R20
2 2 R9, R26 20 kΩResistor, chip, 1/16W, 1% 0603 STD STD
17 17 TP1, TP3, TP4, 5002 Test point, white, thru hole color keyed 0.100 × 0.100 in 5002 Keystone
TP5, TP6, TP7,
TP8, TP9, TP10,
TP11, TP13,
TP14, TP15,
TP16, TP17,
TP19, TP20
2 2 TP12, TP18 5001 Test point, black, thru hole color keyed 0.100 × 0.100 in 5001 Keystone
1 1 TP2 131-4244-00 Adaptor, 3.5-mm probe clip ( or 131-5031-00) 0.200 in 131-4244-00 Tektronix
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www.ti.com Board Layout, Schematic, and Bill of Materials
Table 5. Bill of Materials (continued)
-001 -002 RefDes Value Description Size Part MFR
Number
1 0 U1 BQ24195LRGE IC, I2C Controlled 2.5A Single Cell USB / QFN-23 BQ24195LRGE TI
Adaptor Charger With Narrow VDC Power Path
Management and USB OTG
0 1 U1 BQ24195RGE QFN-24 BQ24195RGE TI
IC, I2C controlled 2.5-A single cell USB/adaptor
charger with narrow VDC power-path
management and USB OTG
1 1 -- PCB 3 in × 3 in × 0.031 PWR193 Any
in
1 1 -- Label (See note 5) 1.25 × 0.25 in THT-13-457-10 Brady
4 4 - SJ-5303 Rubber foot (see note 6) 0.044 × 0.20 in SJ-5303 3M
Notes: 1. These assemblies are ESD sensitive, observe ESD precautions.
2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label after final wash. Text shall be 8 pt font. Text shall be per Label Information.
6. Install after final wash.
Label Information
Assembly number Text
PWR193-001 bq24195LEVM-021
PWR193-002 bq24195EVM-021
19
SLUUA18–October 2012 bq24195/L EVM (PWR193) User’s Guide
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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.