Texas Instruments bq24195/L User manual

User's Guide
SLUUA18–October 2012
bq24195/L EVM (PWR193) User’s Guide
Contents
1 Introduction .................................................................................................................. 2
1.1 EVM Features ...................................................................................................... 2
1.2 Design Considerations ............................................................................................ 2
1.3 General Descriptions .............................................................................................. 2
1.4 I/O Description ...................................................................................................... 2
2 Test Summary ............................................................................................................... 3
2.1 Equipment ........................................................................................................... 3
2.2 Equipment Setup ................................................................................................... 5
2.3 Procedure ........................................................................................................... 6
3 PCB Layout Guideline .................................................................................................... 10
4 Board Layout, Schematic, and Bill of Materials ....................................................................... 11
4.1 Board Layout ...................................................................................................... 11
4.2 Schematic ......................................................................................................... 17
4.3 Bill of Materials .................................................................................................... 18
List of Figures
1 Connections of the HPA172 Kit........................................................................................... 5
2 Original Test Setup for PWR193 (bq24195/L EVM) ................................................................... 5
3 Main Window of the bq24195x Evaluation Software for bq24195/L ................................................. 6
4 CHG Mode Ripple and Duty Cycle: VBUS = 5 V, VBAT = 3.7 V.......................................................... 8
5 Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V ...................................................................... 9
6 bq24195/L EVM Top Layer............................................................................................... 11
7 bq24195/L EVM Second Layer.......................................................................................... 12
8 bq24195/L EVM Third Layer............................................................................................. 13
9 bq24195/L EVM Bottom Layer........................................................................................... 14
10 bq24195/L EVM Top Assembly.......................................................................................... 15
11 bq24195/L EVM Bottom Assembly...................................................................................... 16
12 bq24195/L EVM Schematic .............................................................................................. 17
List of Tables
1 EVM Connections........................................................................................................... 2
2 Jumper Connections........................................................................................................ 3
3 Recommended Operating Conditions.................................................................................... 3
4 Device ID JEITA Settings.................................................................................................. 9
5 Bill of Materials............................................................................................................. 18
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Introduction www.ti.com
1 Introduction
1.1 EVM Features
Refer to the data sheet (SLUSB97) for detailed features and operation.
1.2 Design Considerations
This EVM has protection circuitry, external to the IC, to protect against applying a power source to the
input (VBUS) when the IC is in boost mode, converting battery power to a 5-VDC PMID output. This is
accomplished by two circuits on the EVM schematic by (1) adding an isolation circuit consisting of Q1, its
drive Q3, to apply input power when available and disconnect it when not available and (2) by pulling OTG
low, with Q2, when the input is available. Pulling OTG low disables the boost-mode operation.
The OTG pin should be pulled low at least a few microseconds before the input power is applied via Q1.
This is accomplished on this EVM by setting the drive resistance for Q2 (OTG ckt.) lower and drive
resistance for Q3 (VBUS connection) higher. The voltage threshold and resistance of the driver along with
the input capacitance of Q2 and Q3 set the desired timing sequencing. Q3 (VBUS turn on) has a
Thevinen-equivalent drive of 72k and for Q2 (OTG ckt.) is 35k, allowing the OTG signal to be pulled low
(disables Boost Mode) prior to the input voltage being applied.
1.3 General Descriptions
The bq24195/L evaluation module is a complete charger module for evaluating an I2C Controlled single
NVDC-1 charge using the bq2419x devices.
The bq24195/L EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24195/L EVM
must order USB-to-GPIO interface board separately.
For details, see bq24195/L data sheet.
1.4 I/O Description
Table 1 contains the jumper connections for this EVM.
Table 1. EVM Connections
Jack Description
J1–VIN Input: positive terminal
J1–GND Input: negative terminal (ground terminal)
J2-SYS Connected to system
J2-BAT+ Connected to battery pack
J2-GND Ground
J3 USB-to-GPIO connector (USB Interface Adapter
Connector - HPA172)
J4–INT INT pin connection
J4– OTG OTG pin connection
J4-CE CE pin connection
J4-GND Ground
J5-PMID PMID pin connection or power bank output
J5-GND Ground
J6-TS2 External TS2 pin connection
J6-GND Ground
J7 Mini_USB Connector
J5-TS2 External TS2 pin connection
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www.ti.com Test Summary
Table 2 lists the controls and key parameter settings for this EVM.
Table 2. Jumper Connections
Jack Description Factory Setting
JP1 TS1 to TS2 connection Shunt installed
JP2 D- 20k pull down Shunt not installed
JP3 VSYS pull-up for STAT, CE, INT Shunt installed
JP4 USB current limit selection pin during buck mode and PSEL is high (JP1-High); Shunt not installed
enable pin during boost mode.
In buck mode: OTG = High, IIN limit = 500 mA;
OTG = Low, IIN limit = 100 mA.
The boost mode is activated when the REG01[5:4] = 10 and OTG pin is HIGH.
JP5 /CE pin setting: Pull low to enable the charge Shunt not installed
(GUI also can pull CE low)
JP6 200-Ωshort between D+ and D- Shunt not installed
JP7 TS2 resistor divider pull-up source (REGN) connection Shunt installed
JP8 Internal 10k to ground to TS2 Shunt installed
JP9 D+ 20k Pull down Shunt not installed
Table 3 lists the recommended operating conditions for this EVM.
Table 3. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
Supply voltage, VIN Input voltage from AC adapter input 3.9 5/12 6 V
Battery voltage, VBAT Voltage applied at VBAT terminal 0 3.7 4.25 V
Supply current, IAC Maximum input current from AC adapter 0 3 A
input
Output current, IOUT Output current 0 4 A
Operating junction temperature 0 125 °C
range, TJ
2 Test Summary
Section 2.1 –Section 2.3 explain the equipment, the equipment setup, and the test procedures.
2.1 Equipment
2.1.1 Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle larger voltage and current, it is not necessary for this procedure.
2.1.2 Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V)
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
2.1.3 Load #2 – Use with Boost Mode
PMID-to-GND load, 10 Ω, 5 W or greater
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Test Summary www.ti.com
2.1.4 Meters
Six Fluke 75 multimeters, (equivalent or better)
Or:
Four equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 5 A+ current.
2.1.5 Computer
A computer with at least one USB port and a USB cable. The bq2419xEVM evaluation software must be
properly installed.
2.1.6 USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
2.1.7 Software
Unzip the bq2419xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Windows™ XP and Windows 7 operating systems.
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S
PWR193
bq2419x-EVM
J4
To Computer
USB Port
USB Interface
Adapter
I/O
USB
10-pin
Ribbon Cable
‘To EVM’
Texas Instruments
©2006
www.ti.com Test Summary
2.2 Equipment Setup
1. Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VBUS and GND).
3. Connect a voltage meter across J1 (VBUS) and J1 (GND).
4. Turn on the Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load. Connect
Load in series with a current meter (multimeter), ground side, to J2 (BAT+ and GND) as shown in
Figure 2.
5. Connect a voltage meter across J2 (BAT+ and GND).
6. Connect the HPA172 USB interface adapter to the computer with a USB mini-cable and to J3 with the
10-pin ribbon cable. The connections are shown in Figure 1.
Figure 1. Connections of the HPA172 Kit
Figure 2 shows the test setup for PWR193.
7. Install shunts as shown in Table 2.
Figure 2. Original Test Setup for PWR193 (bq24195/L EVM)
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Test Summary www.ti.com
8. Turn on the computer. Launch the bq2419xEVM evaluation software. The main window of the software
is shown in Figure 3.
Figure 3. Main Window of the bq24195x Evaluation Software for bq24195/L
2.3 Procedure
Follow the steps and verify the outputs and IC for the EVM.
2.3.1 Current Settings
1. Make Sure EQUIPMENT SETUP steps are followed.
ILIM Setting: Set the potentiometer to its lowest value for max input current by connecting an ohm-
meter between point TP9 and ground. Turn the screw on the potentiometer counterclockwise until the
resistance drops to its lowest point (approximately 169 Ω, the value of R7)
2. Launch the BQ2419x EVM GUI software, if not already done
3. Turn on PS#1
Measure →V (J2(SYS), J2(GND)) = 4.10 ±300 mV
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www.ti.com Test Summary
2.3.2 Charge Voltage and Current Regulation of VIN and Device ID Verification
Follow the steps and verify the outputs and IC for the EVM.
2.3.2.1 Software setup (all of Section 2.3.2.1 is done in the GUI):
1. Device address: bq24195/L (6B)
2. Click the Read button
3. Select Disabled for I2C Watchdog Timer Limit
4. Set Input Voltage Limit to 4.2 V
5. Set Input Current Limit to 500 mA
6. Set Charge Voltage Limit to 4.208 V
7. Set Fast Charge Current, ICHG to 512 mA
8. Set Pre-Charge Current to 256 mA
9. Deselect Enable Termination (see the following image)
10. Click the Read button twice
Observe →Everything normal at FAULT box
Observe →D1 (STAT) is on, except the bq24192IEVM
2.3.2.2 Enable Load#1 from Section 2.2 step 4. Measure the voltage across J2 at two different points:
V(J2(SYS), J2(GND)) and V(J2(BAT), J2(GND))
Measure →V(J2(SYS), J2(GND)) = 3.65 V ±300 mV
Measure →V(J2(BAT), J2(GND)) = 2.5V ±200 mV
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CHG Mode: Vbus = 5 V Vbat = 3.7 V
Vsw
Vpmid_AC coupled
Vsys_AC coupled
C2
C1
C3
Test Summary www.ti.com
2.3.2.3 Increase the Constant Voltage Load to 3.7 VDC
Measure →V(J2(SYS), J2(GND)) = 3.75 V ±200 mV
Measure →IBAT = 500 mA ±200 mA
Measure →V(J2(BAT), J2(GND)) = 3.7 V ±200 mV
2.3.2.4 In the software, set Fast Charge Current, ICHG to 1.012 A
Measure →IIN = 500 mA ±200 mA
2.3.2.5 Verify Scope Measurements (See Figure 4 – 500 ns/div)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high frequency spikes < 10 mV
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.25 MHz and 1.5 MHz, duty cycle between 73% and
81%
C3 (AC coupled 20 mV/div): Vac_VSYS (TP3 to GND) - excluding high frequency spikes < 15 mV
Figure 4. CHG Mode Ripple and Duty Cycle: VBUS =5V,VBAT = 3.7 V
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Boost Mode: Vbat = 3.7 V
Vsw
Vprnid_AC coupled
C2
C1
www.ti.com Test Summary
2.3.2.6 Switch to Boost Mode
1. Turn off and disconnect PS#1
2. If the constant voltage load connected from BAT+ to GND is not a four-quadrant supply (sources
current) remove the load and use the power source disconnected in step one, set to 3.7 V and 2 A
current limit and connect between BAT+ and GND
3. Apply 10 Ω(5 W or greater) across J5 (PMID(+) to GND(–)
4. Uncheck the OTG Low box in the GUI
5. Select OTG in the Configuration drop-down window
6. Verify VPMID to GND on J5 is between 4.9 V and 5.3 V
7. Verify scope measurement (Figure 5)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high-frequency spikes
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.2 MHz and 1.7 MHz, Duty cycle between 67%
and 74%
Figure 5. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
2.3.2.7 Verify Device ID JEITA shown in software matches Table 4
Table 4. Device ID JEITA Settings
Assembly Number EVM Part Number Device ID JEITA
PWR193-001 bq24195LEVM-021 100 Disabled
PWR193-002 bq24195EVM-021 100 Disabled
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PCB Layout Guideline www.ti.com
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ωresistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
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