Texas Instruments AFE20408EVM User manual

EVM User's Guide: AFE20408EVM
AFE20408 Evaluation Module
Description
The AFE20408EVM is an easy-to-use platform to
evaluate the functionality and performance of the
AFE20408 device. The AFE20408EVM has optional
circuits and jumpers to configure the device for
different applications.
The AFE20408 is a highly integrated power-amplifier
monitor and control device capable of temperature,
current, and voltage supervision. The AFE20408 bias
controller features eight digital-to-analog converters
(DAC) with programmable output ranges. The eight
gate bias outputs are switched on and off through
dedicated control pins.
Get Started
1. Order the EVM.
2. Configure EVM jumpers.
3. Install AFE20408EVM GUI from ti.com.
4. Download the latest libraries.
5. Connect USB and external power supplies.
6. Launch AFE20408EVM GUI.
Features
• Configurable circuit to evaluate the AFE20408
• Onboard VDD (5-V) and VIO (3.3-V) support via
USB
• Onboard VSSA and VSSB (−10.5-V or −7-V)
support
• FT4222 easily writes to the AFE using
AFE20408EVM GUI
• External SPI and I2C connections available
Applications
•Macro remote radio unit (RRU)
•Active antenna system mMIMO (AAS)
•Outdoor backhaul unit
•Radar
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1 Evaluation Module Overview
1.1 Introduction
The AFE20408 supervisor also features a highly-accurate multi-channel analog-to-digital converter (ADC). The
device integrates two high-voltage inputs, two high-side current-sense amplifiers, and an on-chip temperature
sensor.
The function integration and wide operating temperature range make the AFE20408 an excellent choice for an
all-in-one, bias control circuit for the power amplifiers found in RF communication systems.
This user's guide describes the characteristics, operation, and recommended use cases of the AFE20408EVM.
This document provides examples and instructions on how to use the AFE20408EVM board and included
software. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous
with the AFE20408EVM. This document also includes schematics, the reference printed circuit board (PCB)
layouts, and a complete bill of materials (BOM).
1.2 Kit Contents
Table 1-1 details the contents of the EVM kit. Contact the TI Product Information Center at [phone] if any
component is missing. Download the latest versions of the related software on the TI website, www.ti.com.
Table 1-1. AFE20408EVM Kit Contents
Item Quantity
AFE20408EVM board 1
USB micro-B plug to USB-A plug cable 1
1.3 Specification
The EVM is intended to provide basic functional evaluation of the device. The layout is not intended to be a
model for the target circuit, nor laid out for electromagnetic compatibility (EMC) testing. The EVM consists of a
printed-circuit board (PCB), which has the AFE20408 installed.
1.4 Device Information
The documents in Table 1-2 provide information regarding Texas Instruments integrated circuits used in the
assembly of the AFE20408EVM. This user's guide is available from the TI web site under literature number
SLAU917. Any letter appended to the literature number corresponds to the document revision that is current at
the time of the writing of this document. Newer revisions are available from the TI web site at www.ti.com, or call
the Texas Instruments Literature Response Center at [phone] or the Product Information Center at (972)
644-5580. When ordering, identify the document by both title and literature number.
Table 1-2. Related Device Documentation
Document Literature Number
AFE20408 product data sheet SLASF96
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2 Hardware
2.1 Hardware Setup
This section describes the overall system setup for the EVM. A personal computer (PC) runs software that
communicates with the FTDI controller onboard using I2C or SPI protocols. External power supplies are required
for certain EVM inputs, such as the VCCA and VCCB supplies.
2.1.1 Hardware Theory of Operation
The AFE20408EVM is connected to the computer through the on-board FTDI digital controller using the
USB cable that is supplied with the EVM. The evaluation board features connectors and test points for all
communication lines, DAC outputs, supplies, and the ADC inputs. Figure 2-1 shows a block diagram of the
AFE20408EVM.
AFE20408 Power Supplies
USB Micro
LDOs
FTDI Controller
Digital
Headers
Supply
Selection
AFE20408 AFE20408
Outputs
AFE20408 ADC
Inputs
Figure 2-1. Theory of Operation Block Diagram
The USB provides the 5-V supply to the EVM. A voltage regulator generates 3.3 V from the USB 5-V supply.
These 5-V and 3.3-V supplies are used to power the FTDI controller. By default, the AFE20408 VDD supply
is powered by the USB 5-V and the VIO supply is powered by the LDO 3.3-V supply through the jumper J13
settings. Alternatively, VDD and VIO can be supplied externally through banana jacks J5 and J8, respectively.
Remove the jumper connector on J13 before connecting external supplies to VDD and VIO. The VSSA and
VSSB supplies can be powered by the on-board voltage regulator with jumper J29. The voltage regulator is
powered by an external negative power supply (VNEG) through banana jack J7. VSSA and VSSB can also
be supplied externally through banana jacks J11 and J12, respectively. Remove the jumper connector on J29
before connecting external supplies to VSSA and VSSB. The remaining device power supplies VCCA and VCCB
must be powered externally through banana jacks J3 and J4, respectively.
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2.1.2 Jumper Definitions
Table 2-1 shows the jumper definitions of the AFE20408EVM.
Table 2-1. Jumper Definitions
Designator Name Positions
J2 VCCA-GND-VSSA
SHORT 1-2 - VCCA is grounded.
SHORT 2-3 - VSSA is grounded (default).
OPEN - This jumper is closed.
J6 VCCB = VCCA SHORT 1-2 - VCCA and VCCB are connected (default).
OPEN - VCCA and VCCB are not connected.
J9 VCCB-GND-VSSB
SHORT 1-2 - VCCB is grounded.
SHORT 2-3 - VSSB is grounded (default).
OPEN - This jumper is closed.
J13 USB-VDD-VIO
SHORT 1-2 - VIO is connected to on-board 3.3-V (default).
SHORT 3-4 - VDD is connected to on-board 5-V (default).
OPEN - VDD and VIO are powered by external supplies.
No other jumper orientation allowed.
J17 CS - SCL
SHORT 1-2 - Uses the FTDI CS pin for SPI mode (default).
SHORT 2-3 - Uses the FTDI SCL pin for I2C Mode.
OPEN - Open if external communication is used.
J18 SCLK - SDA
SHORT 1-2 - Uses the FTDI SCLK pin for SPI mode (default).
SHORT 2-3 - Uses the FTDI SDA pin for I2C Mode.
OPEN - Open if external communication is used.
J19 I2C ADDR SELECTION
SHORT 1-2 and 11-12 - SPI configuration (default).
SHORT all else - I2C configuration, see Table 2-6 for jumper configurations.
OPEN - Open if external communication is used.
J23 DRVEN DIS
SHORT 1-2 - Connects DRVEN0 to FTDI controller.
SHORT 3-4 - Connects DRVEN1 to FTDI controller.
OPEN - DRVENx is pulled up high (default).
J24 S0+ = HV0 SHORT 1-2 - Connects ADCHV0 and SENSE0+ together.
OPEN - ADCHV0 and SENSE0+ are separate (default).
J28 VNEG Select
SHORT 1-2 - VNEG regulator output is –10.5-V.
SHORT 3-4 - VNEG regulator output is –7-V.
OPEN - VNEG regulator is not used (default).
J29 VSS Select
SHORT 1-2 - VSSA is connected to the VNEG regulator output.
SHORT 3-4 - VSSB is connected to the VNEG regulator output.
OPEN - VSSA and VSSB are powered externally (default).
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2.1.3 Connector Definitions
Table 2-2 shows the power connector definitions of the AFE20408EVM.
Table 2-2. Power Connector Definitions
Designator Definition
J1 USB connector
J3 AFE20408 VCCA supply (3-V to 11-V)
J4 AFE20408 VSSA supply (−11-V to −3-V)
J5 AFE20408 VDD supply (3-V to 5.5-V)
J7 VNEG supply (−10-V to −33-V)
J8 AFE20408 VIO supply (1.65-V to 3.6-V)
J10 AFE20408 Ground
J11 AFE20408 VCCB supply (3-V to 11-V)
J12 AFE20408 VSSB supply (−11-V to −3-V)
When powering the EVM, follow these guidelines:
• Choose between onboard power or external power for VIO and VDD using the J13 jumper. Do not short this
jumper and use external power at the same time.
• The VNEG supply can be used in place of the VSSA and VSSB supplies. Do not short the J29 jumper and
use external supplies for VSSA and VSSB at the same time.
• The VSSA voltage must always be less than (more negative) or equal to the VSSB voltage.
• To operate the group A DACs in the positive range, apply a positive voltage to VCCA and ground VSSA. To
operate the group A DACs in the negative range, apply a negative voltage to VSSA and ground VCCA.
• To operate the group B DACs in the positive range, apply a positive voltage to VCCB and ground VSSB. To
operate the group B DACs in the negative range, apply a negative voltage to VSSB and ground VCCB.
• To operate in the mixed voltage range, the group B DACs must be positive and the group A DACs must be
negative. Apply a positive voltage to VCCB and ground VSSB for the group B DACs, and apply a negative
voltage to VSSA and ground VCCA for the group A DACs.
Table 2-3 shows other connector definitions for the AFE20408EVM. All of these terminal blocks are unpopulated
by default.
Table 2-3. Terminal Block Connector Definitions
Designator Definition
J14 Connector for DACA3, OUTA2, DACA2, and
VSSA
J15 Connector for DACA1, OUTA1, DACA0, and
VSSA
J20 Connector for DACB3, OUTB2, DACB2, and
VSSB
J21 Connector for DACB1, OUTB1, DACB0, and
VSSB
J25 Connector for current sense pins SENSE1+
and SENSE1-
J26 Connector for current sense pins SENSE0-,
SENSE0+, and ADCHV0
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2.1.4 Test Points
The AFE20408EVM has a variety of test points available for measuring and debugging purposes. Table 2-4
explains the purpose of each test point.
Table 2-4. AFE20408EVM Test Points
Test Point Net Description
TP1 SENSE0+ High side of SENSE0 resistor
TP2 SENSE0- Low side of SENSE0 resistor
TP3 SENSE1+ High side of SENSE1 resistor
TP4 SENSE1- Low side of SENSE1 resistor
TP5 VLDO Output of VNEG regulator
TP6 ADCHV0 ADCHV0 test point
TP7 PAON AFE20408 PAON test point
TP8 VCCA AFE20408 VCCA supply
TP9 VCCB AFE20408 VCCB supply
TP10 VSSA AFE20408 VSSA supply
TP11 VSSB AFE20408 VSSB supply
TP12 SENSE0+ SENSE0+ test point
TP13 SENSE0- SENSE0- test point
TP14, TP15, TP16,
TP17 GND Ground connections
TP18 VIO AFE20408 VIO supply
TP19 VDD AFE20408 VDD supply
TP20 SENSE1+ SENSE1+ test point
TP21 SENSE1- SENSE1- test point
TP22 FTDI_IO2 FTDI GPIO2 testpoint. Can be connected to DRVEN0 by
shorting positions 1-2 on J23 with a jumper
TP23 FTDI_IO3 FTDI GPIO3 testpoint. Can be connected to DRVEN1 by
shorting positions 3-4 on J23 with a jumper
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2.2 Hardware Overview
This section details how to configure the EVM for and voltage outputs using I2C and SPI. The following
subsections provide detailed information on the EVM hardware and jumper positions for the two communication
modes (see also Section 2.1.2).
2.2.1 Electrostatic Discharge Caution
CAUTION
Many of the components on the AFE20408EVM are susceptible to damage by electrostatic
discharge (ESD). Customers are advised to observe proper ESD handling precautions when
unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD
workstation.
2.2.2 Connecting the FTDI Digital Controller
To connect the FTDI digital controller on the EVM board to the PC, align and firmly connect the USB connector
to the J3 connector. Verify the connection is snug; a loose connection can cause intermittent operation. A 100
mil header (J22) is available for external communication. Table 2-5 lists the J22 pin definitions. To use external
communcation, disconnect jumpers J17 and J18 to remove the connection to the FTDI controller. Resistors R7
and R9 can be populated for pullups for I2C. These resistors do not need to be populated for the FTDI driver.
Table 2-5. Digital Header J22 Pin Definitions
Designator Definition
2 AFE20408 SCL/CS
4 AFE20408 SDA/SCLK
6 AFE20408 A0/SDI
8 AFE20408 A1/SDO
10 AFE20408 DRVEN0
12 AFE20408 DRVEN1
14 AFE20408 RESET
16 AFE20408 PAON
1,3,5,7,9,11,13,15 Ground
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2.2.3 SPI Configuration
The following figure shows the AFE20408EVM configured for SPI communication.
Figure 2-2. AFE20408EVM Configuration for SPI
2.2.4 I2C Configuration
The following figure shows the AFE20408EVM configured for I2C communication.
Figure 2-3. AFE20408EVM Configuration I2C
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The jumper connections on J19 determine the device address of the AFE20408. The following table shows the
required configuration of the A1 and A0 jumpers for specific device addresses.
Table 2-6. I2C Device Address Map
Device Pins I2C Device Address
A1 A0 [A6:A0]
GND GND 101 0000
GND VIO 101 0001
GND SDA 101 0010
GND SCL 101 0011
VIO GND 101 0100
VIO VIO 101 0101
VIO SDA 101 0110
VIO SCL 101 0111
SDA GND 101 1000
SDA VIO 101 1001
SDA SDA 101 1010
SDA SCL 101 1011
SCL GND 101 1100
SCL VIO 101 1101
SCL SDA 101 1110
SCL SCL 101 1111
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3 Software
3.1 Software Setup
This section provides the procedure for EVM software installation.
3.1.1 Software Installation
Note
Do not connect the EVM to the PC when the software is installing.
Download the latest version of the EVM graphical user interface (GUI) installer from the Order and start
development subsection of the AFE20408EVM tool folder on TI.com. Run the GUI installer to install the
AFE20408EVM GUI software on your PC. The software installation automatically copies the required LabVIEW™
software files and drivers to the PC.
When the AFE20408EVM GUI is launched, an installation dialog window opens and prompts the user to select
an installation directory. If left unchanged, Figure 3-1 shows that the software location defaults to C:\Program
Files (x86)\Texas Instruments\AFE20408EVM.
Figure 3-1. Software Installation Path
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The EVM software also installs the Future Technology Devices International Limited (FTDI) USB drivers using
a separate executable file. Figure 3-2 shows the FTDI USB drivers installation window that is automatically
launched after the AFE20408EVM software installation is complete.
Figure 3-2. FTDI USB Drivers
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3.2 Software Overview
This section discusses how to use the AFE20408EVM software.
3.2.1 Launching the Software
If installed in the default directory, launch the AFE20408EVM software by searching for "AFE20408EVM" in the
Windows® Start menu.
Figure 3-3 shows the initial configuration menu that is present when the GUI is launched. From this menu, select
the interface protocol, as well as the I2C address, if desired. Select the CONFIG button to save the current
settings and launch the main GUI.
Figure 3-3. AFE20408EVM Interface Settings at Launch
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Figure 3-4 shows the GUI after launch. If the FTDI controller is not connected to the PC when the software
is launched, then the GUI defaults to demo mode. Figure 3-5 illustrates the bottom-left corner of the GUI that
shows the hardware connection status: DEMO MODE or CONNECTED. After the FTDI controller is properly
connected to the PC, restart the AFE20408EVM software to detect the device.
Figure 3-4. AFE20408EVM GUI at Launch
Figure 3-5. FTDI Digital Controller Connection Status
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3.2.2 Software Features
The AFE20408EVM GUI allows for I2C or SPI communication to the AFE20408 and control of the digital pins.
Although the entire register map is available for use, some features have been abstracted into user controls in
the High-Level Configuration page for easy operation.
3.2.2.1 Low Level Configuration Page
Figure 3-6 shows the AFE20408EVM Low Level Configuration page of the AFE20408EVM GUI. This page
allows direct access to all registers on the AFE20408. The GUI handles page address management, allowing
seamless access to registers.
The Register Map section in the center of the page lists all the registers, grouped by the pages in the device.
Directly above the Register Map section are four buttons that allow for read and write access to all registers.
Select a register on the Register Map list to show a description of the values in that register, as well as
information on the register address, default value, size, and current value. Data are written to the registers by
entering a value in the value column of the GUI.
Figure 3-6. Low Level Configuration Page
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3.2.2.2 High Level Configuration Page
The High Level Configuration page is used to set the configuration of the AFE20408EVM GUI. The page
is comprised of two tabs: DAC Control and ADC Control. These two tabs act as shortcuts to configure the
AFE20408 for basic functionality and testing.
Figure 3-7 shows the DAC Control tab of the High Level Configuration page. This tab is used to set the range
and outputs for the DACs. Alarms and status information is also displayed on this tab.
Figure 3-7. DAC Control Tab of the High Level Configuration Page
DACs
DACs DACA0, DACA2, DACB0, and DACB2 are powered on by checking the respective PDACxx box. DACs
DACA1, DACA3, DACB1, and DACB3 are powered on by checking the respective PDACxx box and by clicking
the DRVEN_DACxx box. Write to the DAC buffers by entering hex values into the DACxx_BUFFER boxes.
DRIVE ENABLE
By default, all of the DACs are connected to the software drive enable. To enable the DRVEN hardware pins,
unselect the sofware DRVEN and select one of the hardware DRVEN options (DRVEN0, DRVEN1, or FLEXIO).
The DRVEN0 and DRVEN1 hardware pins be controlled by the GUI if jumper J23 1-2 and 3-4 are shorted.
OUT PINS
By default, OUTA0, OUTA2, OUTB0, and OUTB2 are connected to the VSSA/VSSB power supply. The
CLAMP_SEL_OUTxx box sets the OUTxx pins to the respective DACxx pin. Table 3-1 shows the Output pin
configurations.
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Table 3-1. Output Pin CLAMP Configuration
Output Pin CLAMP Bit CLAMP_SEL = 0 CLAMP_SEL = 1
OUTA0 CLAMP_SEL_OUTA0 VSSA DACA1
OUTA2 CLAMP_SEL_OUTA2 VSSA DACA3
OUTB0 CLAMP_SEL_OUTB0 VSSB DACB1
OUTB2 CLAMP_SEL_OUTB2 VSSB DACB3
Furthermore, the output pins can toggle between the respective odd DACs and even DACs using the even
DAC's DRVEN bit. The CLAMP bit needs to be set to 1 to toggle between the two DACs, as otherwise the OUT
pin is clamped to VSS. Table 3-2 shows the DRVEN configurations.
Table 3-2. Output Pin DRVEN Configuration
Output Pin DRVEN Bit DRVEN = 0 DRVEN = 1
OUTA0 DRVEN_DACA0 DACA1 DACA0
OUTA2 DRVEN_DACA2 DACA3 DACA2
OUTB0 DRVEN_DACB0 DACB1 DACB0
OUTB2 DRVEN_DACB2 DACB3 DACB2
Figure 3-8 shows the ADC Control tab from the High Level Configuration page. This tab configures and reads
data from the ADC in the AFE20408.
Figure 3-8. ADC Control Tab of the High Level Configuration Page
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4 Hardware Design Files
4.1 Schematics
The AFE20408EVM schematics are shown in Figure 4-1 through Figure 4-3.
USB_3.3V
SCLK
PICO
CS
POCI
GPIO2
GPIO3
SDA
SCL
USB_5V
FTDI Input Circuit
DC265_AFE20408EVM_PG1.SchDoc
RESET
SDA/SCLK
SCL/CS
DRVEN1
DRVEN0
A0/SDI
A1/SDO DACA0
OUTA0
DACA1
DACA2
OUTA2
DACA3
DACB0
OUTB0
DACB1
DACB2
OUTB2
DACB3
ADCHV0
SENSE0+
SENSE0-
PAON
SENSE1+
SENSE1-
DUT Circuit
DC265_AFE20408EVM_PG2.SchDoc
1
2
3
J17
1
2
3
J18
GND
VIO
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
16
18
20
J19
I2C ADDR SELECTION
A1/SDO
A0/SDI
PICO
POCI
GND
GND
VIO
VIO
SDA
SDA
SCL
SCL
1 2
3 4
J23
DRVEN DIS
DRVEN0_FTDI
DRVEN1_FTDI
10.0k
R12
10.0k
R11
10.0k
R10
VIO VIO VIO
GND
A0/SDI A1/SDO SCL/CS SDA/SCLK
DRVEN0 DRVEN1
RESET
DRVEN0
DRVEN1
SCL/CS
SDA/SCLK
VCCA VCCB VSSBVSSA
VDD
VIO
1µF
C36
1µF
C37
GND
GND
J10
GND
VCCA
VCCB VSSB
VSSA
GND
VDD
VIO
GND
63V
10uF
C32
63V
10uF
C33
63V
10uF
C34
63V
10uF
C35
GND GND GND GND
J8
VIO
J5
VDD
J3
VCCA
J11
VCCB
J12
VSSB
J4
VSSA
1
2 3
J2
VCCA-GND-VSSA
1
2
3
J9
VCCB-GND-VSSA
1
2
J6
VCCB=VCCA
GND
GND
1
2 3
4
J14
A2-A3
1
2 3
4
J15
A0-A1
0.51
R14
0.51
R13
TP3
S1+
TP4
S1-
TP1
S0+
TP2
S0-
1
2
J24
HV0=S0+
VSSA VSSA
VSSB VSSB
TP14
GND
TP15
GND
TP16
GND
TP17
GND
TP18
VIO
TP19
VDD
TP8
VCCA
TP9
VCCB
TP10
VSSA
TP11
VSSB
TP21
S1-
TP6
ADCHV0
TP7
PAON
TP12
S0+
TP13
S0-
TP20
S1+
OUT
1
NC
2
FB
3
NC 4
NC 5
NC 6
GND
7
NC 8
NC 9
NC 10
NC 11
NC 12
EN 13
NR/SS
14
IN 15
IN 16
NC
17 NC
18 NC
19
OUT
20
PAD
21
TPS7A3301RGWR
U4
J7
VNEG
GND
63V
10uF
C39
1µF
C41
GND
63V
10uF
C40
GND GNDGND
63V
10uF
C38
1.50M
R16
487k
R15
97.6k
R17
187k
R18
1 2
3 4
J28
VNEG Select
GNDGND
VSS = -7 V
VSS = -10.5 V
-10.5Vsel-7Vsel
VLDO VNEG
TP5
VLDO
GND GND GND GND
VDDVIO VCCA VCCB VSSBVSSA
12
34
56
78
910
1112
1314
15
17
19
21
23
16
18
20
22
24
J16
DAC OUTPUTS
1 2 3
J26
SENSE0
1 2 3 4
J21
B0-B2
1 2 3 4
J20
B2-B3
10.0k
R7
10.0k
R9
VIO VIO
1 2
3 4
J29
VSS Select
1 2
3 4
J13
USB-VDD-VIO
VCCA VCCB VSSBVSSA
63V
10uF
C42
63V
10uF
C43
63V
10uF
C44
63V
10uF
C45
GND GND GND GND
Diode is to prevent VSSA

VSSB. VSSA

VSSB is required.
D4
10.0k
R32
VDD
1 2
J25
SENSE1
1 2 3 4
5 6 7 8 9 10
11 12
13 14 15 16
J22
DIGITAL
PAON
PAON
Figure 4-1. AFE20408EVM Schematic Page 1
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VBUS 1
D- 2
D+ 3
ID 4
GND 5
67 8
11 10
9
J1
L1
4.7µF
C23
100nF
C24
100nF
C27
GND GND
GND
GND GND GND
GNDUSB_SHIELD
USB_DP_P
USB_DM_N
100nF
C29 GND
1 2
Y1
1.00M
R8
GND GND
FTDI_SCL_GPIO_0
FTDI_SDA_GPIO_1
FTDI_GPIO_3
FTDI_SS0
FTDI_SCK
FTDI_PICO
FTDI_POCI
FTDI_IO2
FTDI_IO3
FTDI_XSCI
FTDI_XSCO
USB_3.3V
4.7µF
10V
C25
GND
USB_3.3V
USB_3.3V
USB_VBUS
50V
100pF
C28
100nF
C26
330
R5 12k
R6
SCLK
GPIO2
GPIO3
SDA
SCL
FTDI_GPIO_2
USB_5V
VIN
1
GND 2
EN
3
N/C
4
VOUT 5
LP5907MFX-3.3/NOPB
U2
1 2
Y2
18pF
C30
18pF
C31
TP23
IO3
TP22
IO2
VCCIN
26
VCCIO
7
VOUT3V3
25
DCNF0
4
DCNF1
5
IO2 11
IO3 12
SS 32
SS0O 17
RESET
3
BCD_DET
31
DEBUGGER
1
DM
22 DP
23
EP 33
INTR/WAKEUP/GPIO3 16
MISO 9
MOSI 10
RREF
21
SCK 8
SCL/SS1O/GPIO0 13
SDA/SS2O/GPIO1 14
STEST_RST
2
SUSP_OUT/SS3O/GPIO2 15
VBUS_DET
30
VPP
29
XSCI
18
XSCO
19
AGND 27
DGND 6
DGND 28
UGND 20
UGND 24
U3
FT4222HQ-D-R
10.0
R1
10.0
R4
USB_VBUS
USB_3.3V
USB_DM_N
USB_DP_P
GND USB_3.3V
USB_3.3V
USB_3.3V
USB_3.3V
USB_VBUS
GND
CS
POCI
PICO
3.0k
R2
3.0k
R3
1 2
TPD1E01B04DPYQ1
D1
1 2
TPD1E01B04DPYQ1
D2
1 2
TPD1E01B04DPYQ1
D3
Figure 4-2. AFE20408EVM FTDI Schematic
0.1uF
C2
0.1uF
C1
GND
GND
GND
VDD
VIO
RESET
SDA/SCLK
SCL/CS
1µF
C3
GND
GND
DRVEN1
DRVEN0
1µF
C16
GND
GND
GND
GND
1µF
C9
GND
VCCA
VSSB
1µF
C13
GND
VCCB
1µF
C12
GND
VSSA
A0/SDI
A1/SDO
DACA0
OUTA0
DACA1
DACA2
OUTA2
DACA3
DACB0
OUTB0
DACB1
DACB2
OUTB2
DACB3
1µF
C10
GND
1µF
C14
GND
GND
GND
GND
GND
1µF
C19
GND
ADCHV0
SENSE0+
SENSE0-
PAON
SENSE1+
SENSE1-
1µF
C6
GND
1µF
C18
GND
1µF
C11
GND
1µF
C20
GND
0
R25
0
R24
0
R22
0
R21
0
R20
0
R19
0
R31
0
R30
0
R29
0
R28
0
R27
0
R26
25V
1000pF
C5
25V
1000pF
C7
25V
1000pF
C21
25V
1000pF
C22
25V
1000pF
C4
25V
1000pF
C8
25V
1000pF
C17
25V
1000pF
C15
0
R23
VCCB
1
DACB0 2
OUTB0 3
DACB1 4
DACB2 5
OUTB2 6
DACB3 7
DRVEN0
9
VSSB 8
SENSE1- 28
SENSE1+ 29
U1C
AMC7908RHB
SDA/SCLK
10
SCL/CS
11
A0/SDI
12
A1/SDO
13
VIO
14
RESET/FLEXIO
15
GND 25
VDD
26
THERMAL PAD 33
PAON 27
U1A
AMC7908RHB
DRVEN1
16
VSSA 17
DACA3 18
OUTA2 19
DACA2 20
DACA1 21
OUTA0 22
DACA0 23
VCCA
24
SENSE0- 30
SENSE0+ 31
ADCHV0 32
U1B
AMC7908RHB
Figure 4-3. AFE20408EVM DUT Schematic
Hardware Design Files www.ti.com
18 AFE20408 Evaluation Module SLAU917 – OCTOBER 2023
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4.2 PCB Layout
Figure 4-4 through Figure 4-7 show the board layout for the AFE20408EVM.
Figure 4-4. AFE20408EVM PCB Top Layer Layout
Figure 4-5. AFE20408EVM PCB Mid Layer 1 Layout (Ground Plane)
www.ti.com Hardware Design Files
SLAU917 – OCTOBER 2023
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AFE20408 Evaluation Module 19
Copyright © 2023 Texas Instruments Incorporated

Figure 4-6. AFE20408EVM PCB Mid Layer 2 Layout (Ground Plane)
Figure 4-7. AFE20408EVM PCB Bottom Layer Layout
Hardware Design Files www.ti.com
20 AFE20408 Evaluation Module SLAU917 – OCTOBER 2023
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Copyright © 2023 Texas Instruments Incorporated